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| author | Nigel Spon <nigel@adi.co.nz> | 2014-11-21 11:15:22 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-11-21 13:47:42 -0600 |
| commit | 502609c80d5f8c5ec852845c4632c905811b3ac3 (patch) | |
| tree | 3ca172b6f6017f03df58aa81f4e3c7567bf95f82 /c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h | |
| parent | objectsetname.c: Fix always true condition (Coverity ID 1063874) (diff) | |
| download | rtems-502609c80d5f8c5ec852845c4632c905811b3ac3.tar.bz2 | |
powerpc/haleakala: Add network driver
close 1405
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h | 75 |
1 files changed, 72 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h index 8c7c9f1d83..9cf46a780a 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h @@ -36,6 +36,25 @@ enum { EBC0_CFG = 0x23 }; +/* MAL DCRs, have to be #defines */ +#define MAL0_CFG 0x180 +#define MAL0_ESR 0x181 +#define MAL0_IER 0x182 +#define MAL0_TXCASR 0x184 +#define MAL0_TXCARR 0x185 +#define MAL0_TXEOBISR 0x186 +#define MAL0_TXDEIR 0x187 +#define MAL0_RXCASR 0x190 +#define MAL0_RXCARR 0x191 +#define MAL0_RXEOBISR 0x192 +#define MAL0_RXDEIR 0x193 +#define MAL0_TXCTP0R 0x1A0 +#define MAL0_TXCTP1R 0x1A1 +#define MAL0_RXCTP0R 0x1C0 +#define MAL0_RXCTP1R 0x1C1 +#define MAL0_RCBS0 0x1E0 +#define MAL0_RCBS1 0x1E1 + /* Memory-mapped registers */ typedef struct EthernetRegisters_GP { @@ -51,19 +70,28 @@ typedef struct EthernetRegisters_GP { uint32_t VLANTPID; uint32_t VLANTCI; uint32_t pauseTimer; - uint32_t indivHash[4]; - uint32_t groupHash[4]; + uint32_t g_indivHash[4]; /* EX non-IP multicast addr/mask */ + uint32_t g_groupHash[4]; uint32_t lastSrcLo; uint32_t lastSrcHi; uint32_t IPGap; uint32_t STAcontrol; uint32_t xmtReqThreshold; - uint32_t rcvWatermark; + uint32_t rcvWatermarks; uint32_t bytesXmtd; uint32_t bytesRcvd; + uint32_t e_unused2; + uint32_t e_revID; + uint32_t e_unused3[2]; + uint32_t e_indivHash[8]; + uint32_t e_groupHash[8]; + uint32_t e_xmtPause; } EthernetRegisters_GP; +typedef struct EthernetRegisters_GP EthernetRegisters_EX; + enum { EMACAddress = 0xEF600800 }; +enum { EMAC0GPAddress = 0xEF600800 }; enum { // Mode 0 bits @@ -75,12 +103,19 @@ enum { // Mode 1 bits kEMACFullDuplex = 0x80000000, + kEMACDoFlowControl = 0x10000000, kEMACIgnoreSQE = 0x01000000, kEMAC100MBbps = 0x00400000, kEMAC4KRxFIFO = 0x00300000, kEMAC2KTxFIFO = 0x00080000, kEMACTx0Multi = 0x00008000, kEMACTxDependent= 0x00014000, + kEMAC100Mbps = 0x00400000, + kgEMAC4KRxFIFO = 0x00300000, + kgEMAC2KTxFIFO = 0x00080000, + kgEMACTx0Multi = 0x00008000, + kgEMACTxDependent= 0x00014000, + // Tx mode bits kEMACNewPacket0 = 0x80000000, @@ -98,6 +133,25 @@ enum { kEMACHashRcv = 0x00200000, kEMACBrcastRcv = 0x00100000, kEMACMultcastRcv = 0x00080000, + keEMACNonIPMultcast = 0x00040000, + keEMACRxFIFOAFMax = 7, + + // EMAC_STACR bits + kgSTAComplete = 0x8000, + kSTAErr = 0x4000, + + // Interrupt status bits + kEMACIOverrun = 0x02000000, + kEMACIPause = 0x01000000, + kEMACIBadPkt = 0x00800000, + kEMACIRuntPkt = 0x00400000, + kEMACIShortEvt= 0x00200000, + kEMACIAlignErr= 0x00100000, + kEMACIBadFCS = 0x00080000, + kEMACIOverSize= 0x00040000, + kEMACILLCRange= 0x00020000, + kEMACISQEErr = 0x00000080, + kEMACITxErr = 0x00000040, // Buffer descriptor control bits kMALTxReady = 0x8000, @@ -108,6 +162,21 @@ enum { kMALRxFirst = 0x0800, kMALInterrupt = 0x0400, + kMALReset = 0x80000000, + kMALLowPriority = 0, + kMALMedLowPriority = 0x00400000, + kMALMedHiPriority = 0x00800000, + kMALHighPriority = 0x00C00000, + kMALLatency8 = 0x00040000, + kMALLockErr = 0x8000, + kMALCanBurst = 0x4000, + kMALLocksOPB = 0x80, + kMALLocksErrs = 0x2, + + // MAL channel masks + kMALChannel0 = 0x80000000, + kMALChannel1 = 0x40000000, + // EMAC Tx descriptor bits sent kEMACGenFCS = 0x200, kEMACGenPad = 0x100, |