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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-11-26 18:04:12 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-11-27 17:03:40 +0100 |
| commit | d2202ac56d6edc94a813257b1bdf97d6e7c543e2 (patch) | |
| tree | 7889e44ce5fcd00afcbb4f573bcefc481e1165da /c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c | |
| parent | bsps/powerpc: Delete unused EXC_DAR field (diff) | |
| download | rtems-d2202ac56d6edc94a813257b1bdf97d6e7c543e2.tar.bz2 | |
powerpc: Add CPU_Exception_frame
The powerpc port uses now a unified CPU_Exception_frame. This resulted
in a CPU_Exception_frame layout change for the MPC5XX.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c index d9bb872f57..b239cdd60b 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c @@ -27,6 +27,74 @@ #include <bsp/vectors.h> #include <bsp/bootcard.h> +#define PPC_EXC_ASSERT_OFFSET(field, off) \ + RTEMS_STATIC_ASSERT( \ + offsetof(CPU_Exception_frame, field) + FRAME_LINK_SPACE == off, \ + CPU_Exception_frame_offset_ ## field \ + ) + +#define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \ + PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET) + +PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET); +PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET); +PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET); +PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR); +PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR); +PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER); +PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR); +#ifdef __SPE__ + PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET); + PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET); +#endif +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30); +PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31); + +RTEMS_STATIC_ASSERT( + PPC_EXC_MINIMAL_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0, + PPC_EXC_MINIMAL_FRAME_SIZE +); + +RTEMS_STATIC_ASSERT( + PPC_EXC_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0, + PPC_EXC_FRAME_SIZE +); + +RTEMS_STATIC_ASSERT( + sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE, + CPU_Exception_frame +); + uint32_t ppc_exc_cache_wb_check = 1; #define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix)) |