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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-05-14 16:56:44 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-05-14 16:56:44 +0000 |
| commit | 0d776cd24743625f2888d04d72188b2e3f416a3e (patch) | |
| tree | 3f146379e2bd7bdd9f4ee85485fb5039fc036b71 /c/src/lib/libcpu/powerpc/configure.ac | |
| parent | 2001-05-14 Till Straumann <strauman@slac.stanford.edu> (diff) | |
| download | rtems-0d776cd24743625f2888d04d72188b2e3f416a3e.tar.bz2 | |
2001-05-14 Till Straumann <strauman@slac.stanford.edu>
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
the following:
- support for the MPC74000 (AKA G4); there is no
AltiVec support yet, however.
- the cache flushing assembly code uses hardware-flush on the G4.
Also, a couple of hardcoded numerical values were replaced
by more readable symbolic constants.
- extended interrupt-disabled code section so enclose the entire
cache flush/invalidate procedure (as recommended by the book).
This is not (latency) critical as it is only used by
init code but prevents possible corruption.
- Trivial page table support as been added.
(1:1 effective-virtual-physical address mapping which is only
useful only on CPUs which feature hardware TLB replacement,
e.g. >604. This allows for write-protecting memory regions,
e.g. text/ro-data which makes catching corruptors a lot easier.
It also frees one DBAT/IBAT and gives more flexibility
for setting up address maps :-)
- setdbat() allows changing BAT0 also (since the BSP may use
a page table, BAT0 could be available...).
- asm_setdbatX() violated the SVR ABI by using
r20 as a scratch register; changed for r0
- according to the book, a context synchronizing instruction is
necessary prior to and after changing a DBAT -> isync added
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/configure.ac | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/configure.ac b/c/src/lib/libcpu/powerpc/configure.ac index f43c487202..cb98da911f 100644 --- a/c/src/lib/libcpu/powerpc/configure.ac +++ b/c/src/lib/libcpu/powerpc/configure.ac @@ -28,6 +28,7 @@ RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP) RTEMS_CHECK_BSP_CACHE(RTEMS_BSP) AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "mpc750" \ +|| test "$RTEMS_CPU_MODEL" = "mpc7400" \ || test "$RTEMS_CPU_MODEL" = "ppc603e" \ || test "$RTEMS_CPU_MODEL" = "mpc604" \ || test "$RTEMS_CPU_MODEL" = "mpc6xx" \ @@ -40,6 +41,7 @@ AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "mpc750" \ AM_CONDITIONAL(mpc505, test "$RTEMS_CPU_MODEL" = "mpc505") AM_CONDITIONAL(mpc6xx, test "$RTEMS_CPU_MODEL" = "mpc6xx" \ || test "$RTEMS_CPU_MODEL" = "mpc604" \ +|| test "$RTEMS_CPU_MODEL" = "mpc7400" \ || test "$RTEMS_CPU_MODEL" = "mpc750" ) AM_CONDITIONAL(mpc8xx, test "$RTEMS_CPU_MODEL" = "mpc8xx" \ || test "$RTEMS_CPU_MODEL" = "mpc821" \ |