diff options
author | Hesham ALMatary <heshamelmatary@gmail.com> | 2014-09-16 12:30:46 -0500 |
---|---|---|
committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-09-16 12:46:42 -0500 |
commit | c080c3434b9e4911078e40a697ec1f5d01b6cf24 (patch) | |
tree | 41f8725edb497483ce1cc45c76b9010881a5a09c /c/src/lib/libcpu/or1k | |
parent | or1ksim: Update README (diff) | |
download | rtems-c080c3434b9e4911078e40a697ec1f5d01b6cf24.tar.bz2 |
or1k: New cache manager.
Implement new cache functions for or1k and create new bspstart function
for or1ksim to initialize instruction and data caches. Also, sim.cfg
is modified to enable/confiure cache units.
Diffstat (limited to 'c/src/lib/libcpu/or1k')
-rw-r--r-- | c/src/lib/libcpu/or1k/Makefile.am | 3 | ||||
-rw-r--r-- | c/src/lib/libcpu/or1k/preinstall.am | 4 | ||||
-rw-r--r-- | c/src/lib/libcpu/or1k/shared/cache/cache.c | 241 | ||||
-rw-r--r-- | c/src/lib/libcpu/or1k/shared/cache/cache_.h | 2 |
4 files changed, 248 insertions, 2 deletions
diff --git a/c/src/lib/libcpu/or1k/Makefile.am b/c/src/lib/libcpu/or1k/Makefile.am index f4a637216d..8971f4d65b 100644 --- a/c/src/lib/libcpu/or1k/Makefile.am +++ b/c/src/lib/libcpu/or1k/Makefile.am @@ -10,8 +10,9 @@ include_libcpudir = $(includedir)/libcpu ## shared/cache include_libcpu_HEADERS = ../shared/include/cache.h +include_libcpu_HEADERS += shared/cache/cache_.h noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h +shared_cache_rel_SOURCES = shared/cache/cache.c ../shared/src/cache_manager.c shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am index ee9d0da7b1..84864cb86b 100644 --- a/c/src/lib/libcpu/or1k/preinstall.am +++ b/c/src/lib/libcpu/or1k/preinstall.am @@ -22,3 +22,7 @@ $(PROJECT_INCLUDE)/libcpu/cache.h: ../shared/include/cache.h $(PROJECT_INCLUDE)/ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h +$(PROJECT_INCLUDE)/libcpu/cache_.h: shared/cache/cache_.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h + diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c new file mode 100644 index 0000000000..039be369ee --- /dev/null +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c @@ -0,0 +1,241 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> + * + * COPYRIGHT (c) 1989-2006 + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems/score/cpu.h> +#include <rtems/score/interr.h> +#include <rtems/score/or1k-utility.h> +#include <libcpu/cache.h> + +static inline void _CPU_OR1K_Cache_enable_data(void) +{ + uint32_t sr; + ISR_Level level; + + _ISR_Disable (level); + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_disable_data(void) +{ + uint32_t sr; + ISR_Level level; + + _ISR_Disable (level); + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE)); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_enable_instruction(void) +{ + uint32_t sr; + ISR_Level level; + + _ISR_Disable (level); + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_disable_instruction(void) +{ + uint32_t sr; + ISR_Level level; + + _ISR_Disable (level); + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE)); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) +{ + ISR_Level level; + + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_instruction_block_prefetch +(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_instruction_block_invalidate +(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr); + + _ISR_Enable(level); +} + +static inline void _CPU_OR1K_Cache_instruction_block_lock +(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr); + + _ISR_Enable(level); +} + +/* Implement RTEMS cache manager functions */ + +void _CPU_cache_flush_1_data_line(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _CPU_OR1K_Cache_data_block_flush(d_addr); + + //asm volatile("l.csync"); + + _ISR_Enable(level); +} + +void _CPU_cache_invalidate_1_data_line(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _CPU_OR1K_Cache_data_block_invalidate(d_addr); + + _ISR_Enable(level); +} + +void _CPU_cache_freeze_data(void) +{ + /* Do nothing */ +} + +void _CPU_cache_unfreeze_data(void) +{ + /* Do nothing */ +} + +void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) +{ + ISR_Level level; + _ISR_Disable (level); + + _CPU_OR1K_Cache_instruction_block_invalidate(d_addr); + + _ISR_Enable(level); +} + +void _CPU_cache_freeze_instruction(void) +{ + /* Do nothing */ +} + +void _CPU_cache_unfreeze_instruction(void) +{ + /* Do nothing */ +} + +void _CPU_cache_flush_entire_data(void) +{ + +} + +void _CPU_cache_invalidate_entire_data(void) +{ + +} + +void _CPU_cache_invalidate_entire_instruction(void) +{ + +} + +void _CPU_cache_enable_data(void) +{ + _CPU_OR1K_Cache_enable_data(); +} + +void _CPU_cache_disable_data(void) +{ + _CPU_OR1K_Cache_disable_data(); + +} + +void _CPU_cache_enable_instruction(void) +{ + + _CPU_OR1K_Cache_enable_instruction(); +} + +void _CPU_cache_disable_instruction(void) +{ + _CPU_OR1K_Cache_disable_instruction(); +} diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h index 08d9eccf4f..5f08410aea 100644 --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h @@ -5,7 +5,7 @@ #ifndef __OR1K_CACHE_H #define __OR1K_CACHE_H -#include <libcpu/cache.h> +#include <bsp/cache_.h> #endif /* end of include file */ |