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| author | Martin Erik Werner <martinerikwerner.aac@gmail.com> | 2016-11-25 19:21:42 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-11-28 07:30:44 +0100 |
| commit | 3b4ddafe99eb4b88a0687507deb864d6e2b3140b (patch) | |
| tree | f583e2c8684e56b05c54d9c9902c5c00b09b0f00 /c/src/lib/libcpu/or1k/shared/cache/cache_.h | |
| parent | or1k: Indent & comment fix in cache.c (diff) | |
| download | rtems-3b4ddafe99eb4b88a0687507deb864d6e2b3140b.tar.bz2 | |
or1k: Avoid excessive ISR toggle in cache manager
Previously _ISR_Local_{disable,enable}() was executed twice for each
cache line operation, and since operations over the entire cache were
implemented by calling the single-line operations in a loop, this made
those operations rather costly.
Fix the double-toggle by calling _OR1K_mtspr() directly, and removing
the now-unused corresponding _CPU_OR1K_Cache_* functions.
Fix the entire-operations by moving the ISR toggle outside of the
loop, and by calling _OR1K_mtspr() directly instead of the single-line
operations.
Also implement range functions, since otherwise the cache manager falls
back on looping over the single-line operations.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libcpu/or1k/shared/cache/cache_.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h index 0ea939f847..8d96595cf6 100644 --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h @@ -8,5 +8,11 @@ #include <bsp/cache_.h> #include <libcpu/cache.h> +#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1 + +void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes); +void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes); +void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes); + #endif /* end of include file */ |