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authorJennifer Averett <jennifer.averett@OARcorp.com>2012-04-04 08:39:46 -0500
committerJoel Sherrill <joel.sherrill@oarcorp.com>2012-04-04 08:43:08 -0500
commit0c0181dee26d64835f0cd4f47ef81f681ea553e8 (patch)
tree2f8aef096fa1ed345176328b805d9bb8394fd2f8 /c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c
parentbsp/mpc55xx: Add and use chip features (diff)
downloadrtems-0c0181dee26d64835f0cd4f47ef81f681ea553e8.tar.bz2
PR 1993 - Convert MIPS to PIC IRQ model
Diffstat (limited to '')
-rw-r--r--c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c30
1 files changed, 0 insertions, 30 deletions
diff --git a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c
deleted file mode 100644
index e56989a297..0000000000
--- a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file contains the maximum number of vectors. This can not
- * be determined without knowing the RTEMS CPU model.
- *
- * COPYRIGHT (c) 1989-2000.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp
- */
-
-/*
- * Reserve first 32 for exceptions.
- */
-
-/*
- * The Toshiba TX4925 attaches 5 of the eight interrupt bits to an
- * on-CPU interrupt controller so that these five bits map to 32
- * unique interrupts. So you have: 2 software interrupts, an NMI,
- * and 32 others.
- */
-
-#include <rtems.h>
-#include <libcpu/tx4925.h>
-
-unsigned int mips_interrupt_number_of_vectors = TX4925_MAXIMUM_VECTORS;
-