diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 17:52:53 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 17:52:53 +0000 |
| commit | b4d0d18eeda3ee81816c33140de46bb6bc724d43 (patch) | |
| tree | 13ff75e525be655fcfa9119b7f379d71de069635 /c/src/lib/libcpu/mips/tx39/include/tx3904.h | |
| parent | changed version to ss-20001211 (diff) | |
| download | rtems-b4d0d18eeda3ee81816c33140de46bb6bc724d43.tar.bz2 | |
2000-12-13 Joel Sherrill <joel@OARcorp.com>
* shared/.cvsignore, shared/Makefile.am,
shared/cache/.cvsignore, shared/cache/Makefile.am,
shared/cache/cache.c, shared/cache/cache_.h,
shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
shared/interrupts/installisrentries.c,
shared/interrupts/isr_entries.S,
shared/interrupts/maxvectors.c, tx39/.cvsignore,
tx39/Makefile.am, tx39/include/.cvsignore,
tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
Moved some pieces of interrupt processing from score/cpu to
libcpu/mips since many interrupt servicing characteristics are
CPU model dependent. This patch addresses the number of interrupt
sources and where the ISR prologues are located. The only way to
currently install the ISR prologues requires that the prologues
be installed into RAM.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libcpu/mips/tx39/include/tx3904.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/mips/tx39/include/tx3904.h b/c/src/lib/libcpu/mips/tx39/include/tx3904.h new file mode 100644 index 0000000000..ac0efae1f6 --- /dev/null +++ b/c/src/lib/libcpu/mips/tx39/include/tx3904.h @@ -0,0 +1,63 @@ +/* + * MIPS Tx3904 specific information + * + * NOTE: This is far from complete. --joel (13 Dec 2000) + * + * $Id$ + */ + +#ifndef __TX3904_h +#define __TX3904_h + +/* + * Timer Base Addresses and Offsets + */ + +#define TX3904_TIMER0_BASE 0xFFFFF000 +#define TX3904_TIMER1_BASE 0xFFFFF100 +#define TX3904_TIMER2_BASE 0xFFFFF200 + +#define TX3904_TIMER_TCR 0x00 +#define TX3904_TIMER_TISR 0x04 +#define TX3904_TIMER_CPRA 0x08 +#define TX3904_TIMER_CPRB 0x0C +#define TX3904_TIMER_ITMR 0x10 +#define TX3904_TIMER_CCDR 0x20 +#define TX3904_TIMER_PGMR 0x30 +#define TX3904_TIMER_WTMR 0x40 +#define TX3904_TIMER_TRR 0xF0 + +#define TX3904_TIMER_READ( _base, _register ) \ + *((volatile unsigned32 *)((_base) + (_register))) + +#define TX3904_TIMER_WRITE( _base, _register, _value ) \ + *((volatile unsigned32 *)((_base) + (_register))) = (_value) + +/* + * Interrupt Vector Numbers + * + * NOTE: Numbers 0-15 directly map to levels on the IRC. + * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. + */ + +#define TX3904_IRQ_INT1 0 +#define TX3904_IRQ_INT2 1 +#define TX3904_IRQ_INT3 2 +#define TX3904_IRQ_INT4 3 +#define TX3904_IRQ_INT5 4 +#define TX3904_IRQ_INT6 5 +#define TX3904_IRQ_INT7 6 +#define TX3904_IRQ_DMAC3 7 +#define TX3904_IRQ_DMAC2 8 +#define TX3904_IRQ_DMAC1 9 +#define TX3904_IRQ_DMAC0 10 +#define TX3904_IRQ_SIO0 11 +#define TX3904_IRQ_SIO1 12 +#define TX3904_IRQ_TMR0 13 +#define TX3904_IRQ_TMR1 14 +#define TX3904_IRQ_TMR2 15 +#define TX3904_IRQ_INT0 16 +#define TX3904_IRQ_SOFTWARE_1 17 +#define TX3904_IRQ_SOFTWARE_2 18 + +#endif |