Whitespace removal.

5 files changed, 38 insertions, 38 deletions

diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
index 5b284bc463..af832cfdbd 100644
--- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
+++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
@@ -172,8 +172,8 @@ MG5UART_STATIC int mg5uart_set_attributes(
 
   cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
 
-  MG5UART_SETREG( pMG5UART, 
-		  MG5UART_COMMAND_REGISTER, 
+  MG5UART_SETREG( pMG5UART,
+		  MG5UART_COMMAND_REGISTER,
 		  (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
 
   MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
@@ -305,8 +305,8 @@ MG5UART_STATIC int mg5uart_open(
 
   MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
 
-  MG5UART_SETREG( pMG5UART, 
-		  MG5UART_COMMAND_REGISTER, 
+  MG5UART_SETREG( pMG5UART,
+		  MG5UART_COMMAND_REGISTER,
 		  cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
 
   rtems_interrupt_enable(Irql);
@@ -352,8 +352,8 @@ MG5UART_STATIC int mg5uart_close(
   rtems_interrupt_disable(Irql);
   cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
 
-  MG5UART_SETREG( pMG5UART, 
-		  MG5UART_COMMAND_REGISTER,  
+  MG5UART_SETREG( pMG5UART,
+		  MG5UART_COMMAND_REGISTER,
 		  (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
   rtems_interrupt_enable(Irql);
 
@@ -393,7 +393,7 @@ MG5UART_STATIC void mg5uart_write_polled(
    */
   timeout = 2000;
 
-  while( --timeout ) 
+  while( --timeout )
   {
     status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
 
@@ -411,7 +411,7 @@ MG5UART_STATIC void mg5uart_write_polled(
      */
 
 #if 0
-     if(_System_state_Is_up(_System_state_Get())) 
+     if(_System_state_Is_up(_System_state_Get()))
      {
        rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
      }
@@ -473,8 +473,8 @@ __ISR(rx_ready, MG5UART_IRQ_RX_READY)
 
 
 MG5UART_STATIC void mg5uart_process_isr_rx_error(
-   int  minor, 
-   uint32_t   mask 
+   int  minor,
+   uint32_t   mask
 )
 {
   uint32_t                pMG5UART;
@@ -524,7 +524,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
 {
    uint32_t        pMG5UART;
    int             shift;
-   
+
    pMG5UART      = Console_Port_Tbl[minor].ulCtrlPort1;
 
    mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
@@ -533,7 +533,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
       shift = MONGOOSEV_UART0_IRQ_SHIFT;
    else
       shift = MONGOOSEV_UART1_IRQ_SHIFT;
-      
+
    MG5UART_SETREG(
       pMG5UART,
       MG5UART_STATUS_REGISTER,
@@ -549,7 +549,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
     *  There are no more characters to transmit.  The tx interrupts are be cleared
     *  by writing data to the uart, so just disable the tx interrupt sources.
     */
-  
+
    Console_Port_Data[minor].bActive = FALSE;
 
    /* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */
@@ -659,7 +659,7 @@ MG5UART_STATIC int mg5uart_write_support_int(
 
   MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
 
-  if( Console_Port_Data[minor].bActive == FALSE ) 
+  if( Console_Port_Data[minor].bActive == FALSE )
   {
      Console_Port_Data[minor].bActive = TRUE;
      mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
@@ -690,7 +690,7 @@ MG5UART_STATIC int mg5uart_write_support_polled(
   /*
    * poll each byte in the string out of the port.
    */
-  while (nwrite < len) 
+  while (nwrite < len)
   {
     mg5uart_write_polled(minor, *buf++);
     nwrite++;
@@ -734,11 +734,11 @@ MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled(
      status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
   }
 
-  if ( status & MONGOOSEV_UART_RX_READY ) 
+  if ( status & MONGOOSEV_UART_RX_READY )
   {
      return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
-  } 
-  else 
+  }
+  else
   {
      return -1;
   }
diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
index b81d851fb2..316896665a 100644
--- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
+++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
@@ -20,13 +20,13 @@
 #ifndef _MG5UART_MULTIPLIER
 #define _MG5UART_MULTIPLIER 1
 #define _MG5UART_NAME(_X) _X
-#define _MG5UART_TYPE uint32_t  
+#define _MG5UART_TYPE uint32_t
 #endif
 
 #define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \
   (_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER ))
 
-/* 
+/*
  *  MG5UART Get Register Routine
  */
 
diff --git a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
index 57fa593a91..b4e6403b6f 100644
--- a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
+++ b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
@@ -122,10 +122,10 @@
 #define MONGOOSEV_UART_ALL_RX_STATUS_BITS          0x0013
 #define MONGOOSEV_UART_ALL_STATUS_BITS             0x001F
 
-/* 
- *  The Peripheral Interrupt Status, Cause, and Mask registers have the 
- *  same bit assignments although some revisions of the document have 
- *  the Cause and Status registers incorrect.  
+/*
+ *  The Peripheral Interrupt Status, Cause, and Mask registers have the
+ *  same bit assignments although some revisions of the document have
+ *  the Cause and Status registers incorrect.
  */
 
 #define MONGOOSEV_UART0_IRQ_SHIFT 11
@@ -193,7 +193,7 @@
 ** Peripheral Command bits (non-uart, those are defined above)
 */
 #define MONGOOSEV_COMMAND_ENABLE_EDAC	MONGOOSEV_EDAC_SERR_BIT
-#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT         
+#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT
 
 
 
diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
index 6f40a79df9..6933eb7553 100644
--- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
+++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
@@ -1,6 +1,6 @@
-/* 
+/*
  *  This file contains the maximum number of vectors.  This can not
- *  be determined without knowing the RTEMS CPU model. 
+ *  be determined without knowing the RTEMS CPU model.
  *
  *  COPYRIGHT (c) 1989-2000.
  *  On-Line Applications Research Corporation (OAR).
@@ -17,9 +17,9 @@
  */
 
 /*
- *  The Synova Mongoose-V attached one of the eight interrupt bits 
+ *  The Synova Mongoose-V attached one of the eight interrupt bits
  *  to a Peripheral Function Interrupt Cause Register on-CPU.
- *  This results in: 2 software interrupts, 5 interrupts 
+ *  This results in: 2 software interrupts, 5 interrupts
  *  through the IP bits, and 32 more from the PFICR.  Some of
  *  these are reserved but for simplicity in processing, we
  *  reserve slots for those bits anyway.
diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
index ba1499433d..421f95da58 100644
--- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
@@ -91,7 +91,7 @@ int assertSoftwareInterrupt( uint32_t   n )
 static volatile uint32_t   _ivcause, _ivsr;
 
 
-static uint32_t   READ_CAUSE(void) 
+static uint32_t   READ_CAUSE(void)
 {
    mips_get_cause( _ivcause );
    _ivcause &= SR_IMASK;	/* mask off everything other than the interrupt bits */
@@ -140,7 +140,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
       if ( cshifted & 0x01 )       /* SW[0] */
       {
 	 CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
-      } 
+      }
       if ( cshifted & 0x02 )       /* SW[1] */
       {
 	 CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame );
@@ -156,7 +156,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
       CLR_ISR_FLAG( 0x4 );
       if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
    }
-    
+
    if ( cshifted & 0x08 )       /* IP[1] ==> INT1 == TIMER2*/
    {
       SET_ISR_FLAG( 0x8 );
@@ -164,7 +164,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
       CLR_ISR_FLAG( 0x8 );
       if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
    }
-    
+
    if ( cshifted & 0x10 )       /* IP[2] ==> INT2 */
    {
       SET_ISR_FLAG( 0x10 );
@@ -172,7 +172,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
       CLR_ISR_FLAG( 0x10 );
       if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
    }
-    
+
    if ( cshifted & 0x20 )       /* IP[3] ==> INT3 == FPU interrupt */
    {
       SET_ISR_FLAG( 0x20 );
@@ -180,7 +180,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
       CLR_ISR_FLAG( 0x20 );
       if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
    }
-    
+
    if ( cshifted & 0x40 )       /* IP[4] ==> INT4, external interrupt */
    {
       SET_ISR_FLAG( 0x40 );
@@ -198,7 +198,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
       pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
 
 /*
-      for (bit=0, pf_mask = 1;    bit < 32;     bit++, pf_mask <<= 1 ) 
+      for (bit=0, pf_mask = 1;    bit < 32;     bit++, pf_mask <<= 1 )
       {
 	 if ( pf_icr & pf_mask )
 	 {
@@ -208,7 +208,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
 	    pf_reset |= pf_mask;
 	    if( (cshifted = READ_CAUSE()) & 0xff ) break;
 	 }
-      } 
+      }
 */
 
       /*
@@ -217,7 +217,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
        * way thru a full 32 bits.  pf_mask shifts left 8 bits at a time
        * to serve as a interrupt cause test mask.
        */
-      for( bit=0, pf_mask = 0xff;    (bit < 32 && pf_icr);     (bit+=8, pf_mask <<= 8) ) 
+      for( bit=0, pf_mask = 0xff;    (bit < 32 && pf_icr);     (bit+=8, pf_mask <<= 8) )
       {
 	 if ( pf_icr & pf_mask )
 	 {