diff options
author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-14 12:39:57 -0500 |
---|---|---|
committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-16 08:58:47 -0500 |
commit | c7e77ee488a547e5a89d9d9f54fa6e016f3a554b (patch) | |
tree | 2f2ec18c5bee957f5ca3ed1b6ef9e8ed7b47e061 /c/src/lib/libcpu/m68k | |
parent | bfin libcpu and libbsp: Fix warnings (diff) | |
download | rtems-c7e77ee488a547e5a89d9d9f54fa6e016f3a554b.tar.bz2 |
mcf5282: Move cache to libcpu and update av5282 and uC5282 BSPs
Diffstat (limited to 'c/src/lib/libcpu/m68k')
-rw-r--r-- | c/src/lib/libcpu/m68k/Makefile.am | 5 | ||||
-rw-r--r-- | c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c | 122 | ||||
-rw-r--r-- | c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h | 6 |
3 files changed, 133 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/m68k/Makefile.am b/c/src/lib/libcpu/m68k/Makefile.am index 2c46834347..19f500f1e1 100644 --- a/c/src/lib/libcpu/m68k/Makefile.am +++ b/c/src/lib/libcpu/m68k/Makefile.am @@ -176,6 +176,11 @@ if mcf5282 ## mcf5282/include include_mcf5282dir = $(includedir)/mcf5282 include_mcf5282_HEADERS = mcf5282/include/mcf5282.h + +noinst_PROGRAMS += mcf5282/cachepd.rel +mcf5282_cachepd_rel_SOURCES = mcf5282/cache/cachepd.c +mcf5282_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache +mcf5282_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if mcf548x diff --git a/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c new file mode 100644 index 0000000000..e59f213236 --- /dev/null +++ b/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c @@ -0,0 +1,122 @@ +/** + * @file + * + * Cache Management Support Routines for the MCF5282 + */ + +#include <rtems.h> +#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ +#include "cache_.h" + +/* + * CPU-space access + */ +#define m68k_set_acr0(_acr0) \ + __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) +#define m68k_set_acr1(_acr1) \ + __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) + +#define NOP __asm__ volatile ("nop"); + +/* + * DEFAULT WHEN mcf5xxx_initialize_cacr not called + * Read/write copy of common cache + * Split I/D cache + * Allow CPUSHL to invalidate a cache line + * Enable buffered writes + * No burst transfers on non-cacheable accesses + * Default cache mode is *disabled* (cache only ACRx areas) + */ +static uint32_t cacr_mode = MCF5XXX_CACR_CENB | + MCF5XXX_CACR_DBWE | + MCF5XXX_CACR_DCM; + +void mcf5xxx_initialize_cacr(uint32_t cacr) +{ + cacr_mode = cacr; + m68k_set_cacr( cacr_mode ); +} + +/* + * Cannot be frozen + */ +void _CPU_cache_freeze_data(void) {} +void _CPU_cache_unfreeze_data(void) {} +void _CPU_cache_freeze_instruction(void) {} +void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +void _CPU_cache_flush_1_data_line(const void *d_addr) {} +void _CPU_cache_flush_entire_data(void) {} + +void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI ); + NOP; + rtems_interrupt_enable(level); +} + +void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_invalidate_entire_instruction(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); + NOP; +} + +void _CPU_cache_invalidate_1_instruction_line(const void *addr) +{ + /* + * Top half of cache is I-space + */ + addr = (void *)((int)addr | 0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +void _CPU_cache_enable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); + rtems_interrupt_enable(level); +} + +void _CPU_cache_disable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_invalidate_entire_data(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); +} + +void _CPU_cache_invalidate_1_data_line(const void *addr) +{ + /* + * Bottom half of cache is D-space + */ + addr = (void *)((int)addr & ~0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} diff --git a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h index afe444cd86..3724f489de 100644 --- a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h +++ b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h @@ -73,6 +73,12 @@ typedef volatile uint32 vuint32 __attribute__((__may_alias__)); /* 32 bits */ #define MCF5XXX_SR_V (0x0002) #define MCF5XXX_SR_C (0x0001) +/* + * Used to set the initialize the cacr register to the BSP's desired + * starting value. + */ +void mcf5xxx_initialize_cacr(uint32_t); + #define MCF5XXX_CACR_CENB (0x80000000) #define MCF5XXX_CACR_CPDI (0x10000000) #define MCF5XXX_CACR_CPD (0x10000000) |