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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-09-19 15:51:33 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-09-19 15:51:33 +0000 |
commit | c01e72bdc519753b96da89248efde5126f4f3da2 (patch) | |
tree | 4c4616e634e69890ff619cb87d21e55bed391b8f /c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c | |
parent | 2008-09-19 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
download | rtems-c01e72bdc519753b96da89248efde5126f4f3da2.tar.bz2 |
2008-09-19 Joel Sherrill <joel.sherrill@oarcorp.com>
* Makefile.am: Split out various BSPs bspstart.c contents. Move cache
management code here.
* mcf5223x/cache/cachepd.c, mcf5235/cache/cachepd.c: New files.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c new file mode 100644 index 0000000000..361cfa1bfc --- /dev/null +++ b/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c @@ -0,0 +1,101 @@ +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <mcf5235/mcf5235.h> + +/* + * Default value for the cacr is set by the BSP + */ +extern uint32_t cacr_mode; + +/* + * Cannot be frozen + */ +void _CPU_cache_freeze_data(void) {} +void _CPU_cache_unfreeze_data(void) {} +void _CPU_cache_freeze_instruction(void) {} +void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +void _CPU_cache_flush_1_data_line(const void *d_addr) {} +void _CPU_cache_flush_entire_data(void) {} + +void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_invalidate_entire_instruction(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); +} + +void _CPU_cache_invalidate_1_instruction_line(const void *addr) +{ + /* + * Top half of cache is I-space + */ + addr = (void *)((int)addr | 0x400); + asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +void _CPU_cache_enable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_disable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +void _CPU_cache_invalidate_entire_data(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); +} + +void _CPU_cache_invalidate_1_data_line(const void *addr) +{ + /* + * Bottom half of cache is D-space + */ + addr = (void *)((int)addr & ~0x400); + asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} |