Reworked score/cpu/i960 so it can be safely compiled multilib. All

routines and structures that require CPU model specific information
are now in libcpu.  This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

1 files changed, 38 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c b/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c
new file mode 100644
index 0000000000..6e5f13952b
--- /dev/null
+++ b/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c
@@ -0,0 +1,38 @@
+/*
+ *  Install raw interrupt vector for i960ca
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <libcpu/i960CA.h>
+
+#define i960_vector_caching_enabled( _prcb ) \
+   ((_prcb)->control_tbl->icon & 0x2000)
+
+extern i960_PRCB *Prcb;
+
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  i960_PRCB   *prcb = Prcb;
+  proc_ptr    *cached_intr_tbl = NULL;
+
+  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
+   *  in the Interrupt Table are used to manage pending interrupts.
+   *  Thus vector 8, the first valid vector number, is actually in
+   *  slot 9 in the table.
+   */
+
+  *old_handler = prcb->intr_tbl[ vector + 1 ];
+
+  prcb->intr_tbl[ vector + 1 ] = new_handler;
+
+  if ( i960_vector_caching_enabled( prcb ) )
+    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
+      cached_intr_tbl[ vector >> 4 ] = new_handler;
+}
+