diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-15 20:18:41 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-15 20:18:41 +0000 |
| commit | 30abd24b7e7bc1f66b22527792931cf4468b06b8 (patch) | |
| tree | fba359b7e4b04fdd1f008f54fcca7b69d810bab6 /c/src/lib/libcpu/bfin/include | |
| parent | 2008-08-15 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
| download | rtems-30abd24b7e7bc1f66b22527792931cf4468b06b8.tar.bz2 | |
2008-08-15 Allan Hessenflow <allanh@kallisti.com>
* ChangeLog, Makefile.am, README, configure.ac, preinstall.am,
cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c,
clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h,
include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h,
include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h,
include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h,
include/sicRegs.h, include/spiRegs.h, include/sportRegs.h,
include/timerRegs.h, include/twiRegs.h, include/uartRegs.h,
include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h,
mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h,
serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h,
serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h,
timer/timer.c: New files.
Diffstat (limited to 'c/src/lib/libcpu/bfin/include')
19 files changed, 1886 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/bfin/include/bf533.h b/c/src/lib/libcpu/bfin/include/bf533.h new file mode 100644 index 0000000000..44a0b9b982 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/bf533.h @@ -0,0 +1,136 @@ +/* Blackfin BF533 Definitions + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _bf533_h_ +#define _bf533_h_ + +/* register (or register block) addresses */ + +#define SIC_BASE_ADDRESS 0xffc00100 +#define WDOG_BASE_ADDRESS 0xffc00200 +#define RTC_BASE_ADDRESS 0xffc00300 +#define UART0_BASE_ADDRESS 0xffc00400 +#define SPI_BASE_ADDRESS 0xffc00500 +#define TIMER_BASE_ADDRESS 0xffc00600 +#define TIMER_CHANNELS 3 +#define TIMER_PITCH 0x10 +#define TIMER0_BASE_ADDRESS 0xffc00600 +#define TIMER1_BASE_ADDRESS 0xffc00610 +#define TIMER2_BASE_ADDRESS 0xffc00620 +#define TIMER_ENABLE 0xffc00640 +#define TIMER_DISABLE 0xffc00644 +#define TIMER_STATUS 0xffc00648 +#define PORTFIO_BASE_ADDRESS 0xffc00700 +#define SPORT0_BASE_ADDRESS 0xffc00800 +#define SPORT1_BASE_ADDRESS 0xffc00900 +#define EBIU_BASE_ADDRESS 0xffc00a00 +#define DMA_TC_PER 0xffc00b0c +#define DMA_TC_CNT 0xffc00b10 +#define DMA_BASE_ADDRESS 0xffc00c00 +#define DMA_CHANNELS 8 +#define DMA_PITCH 0x40 +#define DMA0_BASE_ADDRESS 0xffc00c00 +#define DMA1_BASE_ADDRESS 0xffc00c40 +#define DMA2_BASE_ADDRESS 0xffc00c80 +#define DMA3_BASE_ADDRESS 0xffc00cc0 +#define DMA4_BASE_ADDRESS 0xffc00d00 +#define DMA5_BASE_ADDRESS 0xffc00d40 +#define DMA6_BASE_ADDRESS 0xffc00d80 +#define DMA7_BASE_ADDRESS 0xffc00dc0 +#define MDMA_BASE_ADDRESS 0xffc00e00 +#define MDMA_CHANNELS 2 +#define MDMA_D_S 0x40 +#define MDMA_PITCH 0x80 +#define MDMA0D_BASE_ADDRESS 0xffc00e00 +#define MDMA0S_BASE_ADDRESS 0xffc00e40 +#define MDMA1D_BASE_ADDRESS 0xffc00e80 +#define MDMA1S_BASE_ADDRESS 0xffc00ec0 +#define PPI_BASE_ADDRESS 0xffc01000 + + +/* register fields */ + +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 + +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 + +#define TIMER_ENABLE_TIMEN2 0x0004 +#define TIMER_ENABLE_TIMEN1 0x0002 +#define TIMER_ENABLE_TIMEN0 0x0001 + +#define TIMER_DISABLE_TIMDIS2 0x0004 +#define TIMER_DISABLE_TIMDIS1 0x0002 +#define TIMER_DISABLE_TIMDIS0 0x0001 + +#define TIMER_STATUS_TRUN2 0x00004000 +#define TIMER_STATUS_TRUN1 0x00002000 +#define TIMER_STATUS_TRUN0 0x00001000 +#define TIMER_STATUS_TOVF_ERR2 0x00000040 +#define TIMER_STATUS_TOVF_ERR1 0x00000020 +#define TIMER_STATUS_TOVF_ERR0 0x00000010 +#define TIMER_STATUS_TIMIL2 0x00000004 +#define TIMER_STATUS_TIMIL1 0x00000002 +#define TIMER_STATUS_TIMIL0 0x00000001 + +/* Core Event Controller vectors */ + +#define CEC_EMULATION_VECTOR 0 +#define CEC_RESET_VECTOR 1 +#define CEC_NMI_VECTOR 2 +#define CEC_EXCEPTIONS_VECTOR 3 +#define CEC_HARDWARE_ERROR_VECTOR 5 +#define CEC_CORE_TIMER_VECTOR 6 +#define CEC_INTERRUPT_BASE_VECTOR 7 +#define CEC_INTERRUPT_COUNT 9 + + +/* System Interrupt Controller vectors */ + +#define SIC_PLL_WAKEUP_VECTOR 0 +#define SIC_DMA_ERROR_VECTOR 1 +#define SIC_PPI_ERROR_VECTOR 2 +#define SIC_SPORT0_ERROR_VECTOR 3 +#define SIC_SPORT1_ERROR_VECTOR 4 +#define SIC_SPI_ERROR_VECTOR 5 +#define SIC_UART0_ERROR_VECTOR 6 +#define SIC_RTC_VECTOR 7 +#define SIC_DMA0_PPI_VECTOR 8 +#define SIC_DMA1_SPORT0_RX_VECTOR 9 +#define SIC_DMA2_SPORT0_TX_VECTOR 10 +#define SIC_DMA3_SPORT1_RX_VECTOR 11 +#define SIC_DMA4_SPORT1_TX_VECTOR 12 +#define SIC_DMA5_SPI_VECTOR 13 +#define SIC_DMA6_UART0_RX_VECTOR 14 +#define SIC_DMA7_UART0_TX_VECTOR 15 +#define SIC_TIMER0_VECTOR 16 +#define SIC_TIMER1_VECTOR 17 +#define SIC_TIMER2_VECTOR 18 +#define SIC_MDMA0_VECTOR 21 +#define SIC_MDMA1_VECTOR 22 +#define SIC_WATCHDOG_VECTOR 23 + +#endif /* _bf533_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/bf537.h b/c/src/lib/libcpu/bfin/include/bf537.h new file mode 100644 index 0000000000..82454410f6 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/bf537.h @@ -0,0 +1,226 @@ +/* Blackfin BF537 Definitions + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _bf537_h_ +#define _bf537_h_ + +/* register (or register block) addresses */ + +#define SIC_BASE_ADDRESS 0xffc00100 +#define WDOG_BASE_ADDRESS 0xffc00200 +#define RTC_BASE_ADDRESS 0xffc00300 +#define UART0_BASE_ADDRESS 0xffc00400 +#define SPI_BASE_ADDRESS 0xffc00500 +#define TIMER_BASE_ADDRESS 0xffc00600 +#define TIMER_CHANNELS 8 +#define TIMER_PITCH 0x10 +#define TIMER0_BASE_ADDRESS 0xffc00600 +#define TIMER1_BASE_ADDRESS 0xffc00610 +#define TIMER2_BASE_ADDRESS 0xffc00620 +#define TIMER3_BASE_ADDRESS 0xffc00630 +#define TIMER4_BASE_ADDRESS 0xffc00640 +#define TIMER5_BASE_ADDRESS 0xffc00650 +#define TIMER6_BASE_ADDRESS 0xffc00660 +#define TIMER7_BASE_ADDRESS 0xffc00670 +#define TIMER_ENABLE 0xffc00680 +#define TIMER_DISABLE 0xffc00684 +#define TIMER_STATUS 0xffc00688 +#define PORTFIO_BASE_ADDRESS 0xffc00700 +#define SPORT0_BASE_ADDRESS 0xffc00800 +#define SPORT1_BASE_ADDRESS 0xffc00900 +#define EBIU_BASE_ADDRESS 0xffc00a00 +#define DMA_TC_PER 0xffc00b0c +#define DMA_TC_CNT 0xffc00b10 +#define DMA_BASE_ADDRESS 0xffc00c00 +#define DMA_CHANNELS 12 +#define DMA_PITCH 0x40 +#define DMA0_BASE_ADDRESS 0xffc00c00 +#define DMA1_BASE_ADDRESS 0xffc00c40 +#define DMA2_BASE_ADDRESS 0xffc00c80 +#define DMA3_BASE_ADDRESS 0xffc00cc0 +#define DMA4_BASE_ADDRESS 0xffc00d00 +#define DMA5_BASE_ADDRESS 0xffc00d40 +#define DMA6_BASE_ADDRESS 0xffc00d80 +#define DMA7_BASE_ADDRESS 0xffc00dc0 +#define DMA8_BASE_ADDRESS 0xffc00e00 +#define DMA9_BASE_ADDRESS 0xffc00e40 +#define DMA10_BASE_ADDRESS 0xffc00e80 +#define DMA11_BASE_ADDRESS 0xffc00ec0 +#define MDMA_BASE_ADDRESS 0xffc00f00 +#define MDMA_CHANNELS 2 +#define MDMA_D_S 0x40 +#define MDMA_PITCH 0x80 +#define MDMA0D_BASE_ADDRESS 0xffc00f00 +#define MDMA0S_BASE_ADDRESS 0xffc00f40 +#define MDMA1D_BASE_ADDRESS 0xffc00f80 +#define MDMA1S_BASE_ADDRESS 0xffc00fc0 +#define PPI_BASE_ADDRESS 0xffc01000 +#define TWI_BASE_ADDRESS 0xffc01400 +#define PORTGIO_BASE_ADDRESS 0xffc01500 +#define PORTHIO_BASE_ADDRESS 0xffc01700 +#define UART1_BASE_ADDRESS 0xffc02000 +#define CAN_BASE_ADDRESS 0xffc02a00 +#define CAN_AM_BASE_ADDRESS 0xffc02b00 +#define CAN_MB_BASE_ADDRESS 0xffc02c00 +#define EMAC_BASE_ADDRESS 0xffc03000 +#define PORTF_FER 0xffc03200 +#define PORTG_FER 0xffc03204 +#define PORTH_FER 0xffc03208 +#define PORT_MUX 0xffc0320c +#define HMDMA0_BASE_ADDRESS 0xffc03300 +#define HMDMA1_BASE_ADDRESS 0xffc03340 + + +/* register fields */ + +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 +#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 +#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 +#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f +#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 + +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 +#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 +#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 +#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f +#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 + +#define TIMER_ENABLE_TIMEN7 0x0080 +#define TIMER_ENABLE_TIMEN6 0x0040 +#define TIMER_ENABLE_TIMEN5 0x0020 +#define TIMER_ENABLE_TIMEN4 0x0010 +#define TIMER_ENABLE_TIMEN3 0x0008 +#define TIMER_ENABLE_TIMEN2 0x0004 +#define TIMER_ENABLE_TIMEN1 0x0002 +#define TIMER_ENABLE_TIMEN0 0x0001 + +#define TIMER_DISABLE_TIMDIS7 0x0080 +#define TIMER_DISABLE_TIMDIS6 0x0040 +#define TIMER_DISABLE_TIMDIS5 0x0020 +#define TIMER_DISABLE_TIMDIS4 0x0010 +#define TIMER_DISABLE_TIMDIS3 0x0008 +#define TIMER_DISABLE_TIMDIS2 0x0004 +#define TIMER_DISABLE_TIMDIS1 0x0002 +#define TIMER_DISABLE_TIMDIS0 0x0001 + +#define TIMER_STATUS_TRUN7 0x80000000 +#define TIMER_STATUS_TRUN6 0x40000000 +#define TIMER_STATUS_TRUN5 0x20000000 +#define TIMER_STATUS_TRUN4 0x10000000 +#define TIMER_STATUS_TOVF_ERR7 0x00800000 +#define TIMER_STATUS_TOVF_ERR6 0x00400000 +#define TIMER_STATUS_TOVF_ERR5 0x00200000 +#define TIMER_STATUS_TOVF_ERR4 0x00100000 +#define TIMER_STATUS_TIMIL7 0x00080000 +#define TIMER_STATUS_TIMIL6 0x00040000 +#define TIMER_STATUS_TIMIL5 0x00020000 +#define TIMER_STATUS_TIMIL4 0x00010000 +#define TIMER_STATUS_TRUN3 0x00008000 +#define TIMER_STATUS_TRUN2 0x00004000 +#define TIMER_STATUS_TRUN1 0x00002000 +#define TIMER_STATUS_TRUN0 0x00001000 +#define TIMER_STATUS_TOVF_ERR3 0x00000080 +#define TIMER_STATUS_TOVF_ERR2 0x00000040 +#define TIMER_STATUS_TOVF_ERR1 0x00000020 +#define TIMER_STATUS_TOVF_ERR0 0x00000010 +#define TIMER_STATUS_TIMIL3 0x00000008 +#define TIMER_STATUS_TIMIL2 0x00000004 +#define TIMER_STATUS_TIMIL1 0x00000002 +#define TIMER_STATUS_TIMIL0 0x00000001 + +#define PORT_MUX_PGTE 0x0800 +#define PORT_MUX_PGRE 0x0400 +#define PORT_MUX_PGSE 0x0200 +#define PORT_MUX_PFFE 0x0100 +#define PORT_MUX_PFS4E 0x0080 +#define PORT_MUX_PFS5E 0x0040 +#define PORT_MUX_PFS6E 0x0020 +#define PORT_MUX_PFTE 0x0010 +#define PORT_MUX_PFDE 0x0008 +#define PORT_MUX_PJCE_MASK 0x0006 +#define PORT_MUX_PJCE_DR0SEC_DTOSEC 0x0000 +#define PORT_MUX_PJCE_CANRX_CANTX 0x0002 +#define PORT_MUX_PJCE_SPISSEL7 0x0004 +#define PORT_MUX_PJSE 0x0001 + + +/* Core Event Controller vectors */ + +#define CEC_EMULATION_VECTOR 0 +#define CEC_RESET_VECTOR 1 +#define CEC_NMI_VECTOR 2 +#define CEC_EXCEPTIONS_VECTOR 3 +#define CEC_HARDWARE_ERROR_VECTOR 5 +#define CEC_CORE_TIMER_VECTOR 6 +#define CEC_INTERRUPT_BASE_VECTOR 7 +#define CEC_INTERRUPT_COUNT 9 + + +/* System Interrupt Controller vectors */ + +#define SIC_PLL_WAKEUP_VECTOR 0 +#define SIC_DMA_ERROR_VECTOR 1 +#define SIC_DMAR0_BLOCK_DONE_VECTOR 1 +#define SIC_DMAR1_BLOCK_DONE_VECTOR 1 +#define SIC_DMAR0_OVERFLOW_VECTOR 1 +#define SIC_DMAR1_OVERFLOW_VECTOR 1 +#define SIC_CAN_ERROR_VECTOR 2 +#define SIC_MAC_ERROR_VECTOR 2 +#define SIC_SPORT0_ERROR_VECTOR 2 +#define SIC_SPORT1_ERROR_VECTOR 2 +#define SIC_PPI_ERROR_VECTOR 2 +#define SIC_SPI_ERROR_VECTOR 2 +#define SIC_UART0_ERROR_VECTOR 2 +#define SIC_UART1_ERROR_VECTOR 2 +#define SIC_RTC_VECTOR 3 +#define SIC_DMA0_PPI_VECTOR 4 +#define SIC_DMA3_SPORT0_RX_VECTOR 5 +#define SIC_DMA4_SPORT0_TX_VECTOR 6 +#define SIC_DMA5_SPORT1_RX_VECTOR 7 +#define SIC_DMA5_SPORT1_TX_VECTOR 8 +#define SIC_TWI_VECTOR 9 +#define SIC_DMA7_SPI_VECTOR 10 +#define SIC_DMA8_UART0_RX_VECTOR 11 +#define SIC_DMA9_UART0_TX_VECTOR 12 +#define SIC_DMA10_UART1_RX_VECTOR 13 +#define SIC_DMA11_UART1_TX_VECTOR 14 +#define SIC_CAN_RX_VECTOR 15 +#define SIC_CAN_TX_VECTOR 16 +#define SIC_DMA1_MAC_RX_VECTOR 17 +#define SIC_PORTH_IRQ_A_VECTOR 17 +#define SIC_DMA2_MAC_TX_VECTOR 18 +#define SIC_PORTH_IRQ_B_VECTOR 18 +#define SIC_TIMER0_VECTOR 19 +#define SIC_TIMER1_VECTOR 20 +#define SIC_TIMER2_VECTOR 21 +#define SIC_TIMER3_VECTOR 22 +#define SIC_TIMER4_VECTOR 23 +#define SIC_TIMER5_VECTOR 24 +#define SIC_TIMER6_VECTOR 25 +#define SIC_TIMER7_VECTOR 26 +#define SIC_PORTF_IRQ_A_VECTOR 27 +#define SIC_PORTG_IRQ_A_VECTOR 27 +#define SIC_PORTG_IRQ_B_VECTOR 28 +#define SIC_MDMA0_VECTOR 29 +#define SIC_MDMA1_VECTOR 30 +#define SIC_WATCHDOG_VECTOR 31 +#define SIC_PORTF_IRQ_B_VECTOR 31 + + +#endif /* _bf537_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/cecRegs.h b/c/src/lib/libcpu/bfin/include/cecRegs.h new file mode 100644 index 0000000000..58916735fe --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/cecRegs.h @@ -0,0 +1,49 @@ +/* Blackfin Core Event Controller Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _cecRegs_h_ +#define _cecRegs_h_ + +/* register addresses */ +#define CEC_EVT_BASE 0xffe02000 +#define CEC_EVT_COUNT 16 +#define CEC_EVT_PITCH 0x04 +#define CEC_EVT0 0xffe02000 +#define CEC_EVT1 0xffe02004 +#define CEC_EVT2 0xffe02008 +#define CEC_EVT3 0xffe0200c +#define CEC_EVT4 0xffe02010 +#define CEC_EVT5 0xffe02014 +#define CEC_EVT6 0xffe02018 +#define CEC_EVT7 0xffe0201c +#define CEC_EVT8 0xffe02020 +#define CEC_EVT9 0xffe02024 +#define CEC_EVT10 0xffe02028 +#define CEC_EVT11 0xffe0202c +#define CEC_EVT12 0xffe02030 +#define CEC_EVT13 0xffe02034 +#define CEC_EVT14 0xffe02038 +#define CEC_EVT15 0xffe0203c +#define CEC_IMASK 0xffe02104 +#define CEC_IPEND 0xffe02108 +#define CEC_ILAT 0xffe0210c +#define CEC_IPRIO 0xffe02110 + + +/* register fields */ + +#define CEC_IPRIO_IPRIO_MARK_MASK 0x0000000f +#define CEC_IPRIO_IPRIO_MARK_SHIFT 0 + + +#endif /* _cecRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/coreTimerRegs.h b/c/src/lib/libcpu/bfin/include/coreTimerRegs.h new file mode 100644 index 0000000000..393720f4dd --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/coreTimerRegs.h @@ -0,0 +1,32 @@ +/* Blackfin Core Timer Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _coreTimerRegs_h_ +#define _coreTimerRegs_h_ + +/* register addresses */ + +#define TCNTL 0xffe03000 +#define TPERIOD 0xffe03004 +#define TSCALE 0xffe03008 +#define TCOUNT 0xffe0300c + + +/* register fields */ + +#define TCNTL_TINT 0x00000008 +#define TCNTL_TAUTORLD 0x00000004 +#define TCNTL_TMREN 0x00000002 +#define TCNTL_TMPWR 0x00000001 + +#endif /* _coreTimerRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/dmaRegs.h b/c/src/lib/libcpu/bfin/include/dmaRegs.h new file mode 100644 index 0000000000..0fc62019d8 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/dmaRegs.h @@ -0,0 +1,100 @@ +/* Blackfin DMA Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _dmaRegs_h_ +#define _dmaRegs_h_ + + +/* register addresses */ + +#define DMA_NEXT_DESC_PTR_OFFSET 0x0000 +#define DMA_START_ADDR_OFFSET 0x0004 +#define DMA_CONFIG_OFFSET 0x0008 +#define DMA_X_COUNT_OFFSET 0x0010 +#define DMA_X_MODIFY_OFFSET 0x0014 +#define DMA_Y_COUNT_OFFSET 0x0018 +#define DMA_Y_MODIFY_OFFSET 0x001c +#define DMA_CURR_DESC_PTR_OFFSET 0x0020 +#define DMA_CURR_ADDR_OFFSET 0x0024 +#define DMA_IRQ_STATUS_OFFSET 0x0028 +#define DMA_PERIPHERAL_MAP_OFFSET 0x002c +#define DMA_CURR_X_COUNT_OFFSET 0x0030 +#define DMA_CURR_Y_COUNT_OFFSET 0x0038 + +#define HMDMA_CONTROL_OFFSET 0x0000 +#define HMDMA_ECINIT_OFFSET 0x0004 +#define HMDMA_BCINIT_OFFSET 0x0008 +#define HMDMA_ECURGENT_OFFSET 0x000c +#define HMDMA_ECOVERFLOW_OFFSET 0x0010 +#define HMDMA_ECOUNT_OFFSET 0x0014 +#define HMDMA_BCOUNT_OFFSET 0x0018 + + +/* register fields */ + +#define DMA_CONFIG_FLOW_MASK 0x7000 +#define DMA_CONFIG_FLOW_STOP 0x0000 +#define DMA_CONFIG_FLOW_AUTOBUFFER 0x1000 +#define DMA_CONFIG_FLOW_DESC_ARRAY 0x4000 +#define DMA_CONFIG_FLOW_DESC_SMALL 0x6000 +#define DMA_CONFIG_FLOW_DESC_LARGE 0x7000 +#define DMA_CONFIG_NDSIZE_MASK 0x0f00 +#define DMA_CONFIG_NDSIZE_SHIFT 8 +#define DMA_CONFIG_DI_EN 0x0080 +#define DMA_CONFIG_DI_SEL 0x0040 +#define DMA_CONFIG_SYNC 0x0020 +#define DMA_CONFIG_DMA2D 0x0010 +#define DMA_CONFIG_WDSIZE_MASK 0x000c +#define DMA_CONFIG_WDSIZE_8 0x0000 +#define DMA_CONFIG_WDSIZE_16 0x0004 +#define DMA_CONFIG_WDSIZE_32 0x0008 +#define DMA_CONFIG_WNR 0x0002 +#define DMA_CONFIG_DMAEN 0x0001 + +#define DMA_IRQ_STATUS_DMA_RUN 0x0008 +#define DMA_IRQ_STATUS_DFETCH 0x0004 +#define DMA_IRQ_STATUS_DMA_ERR 0x0002 +#define DMA_IRQ_STATUS_DMA_DONE 0x0001 + +#define DMA_PERIPHERAL_MAP_PMAP_MASK 0xf000 +#define DMA_PERIPHERAL_MAP_PMAP_PPI 0x0000 +#define DMA_PERIPHERAL_MAP_PMAP_ETHRX 0x1000 +#define DMA_PERIPHERAL_MAP_PMAP_ETHTX 0x2000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT0RX 0x3000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT0TX 0x4000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT1RX 0x5000 +#define DMA_PERIPHERAL_MAP_PMAP_SPORT1TX 0x6000 +#define DMA_PERIPHERAL_MAP_PMAP_SPI 0x7000 +#define DMA_PERIPHERAL_MAP_PMAP_UART0RX 0x8000 +#define DMA_PERIPHERAL_MAP_PMAP_UART0TX 0x9000 +#define DMA_PERIPHERAL_MAP_PMAP_UART1RX 0xa000 +#define DMA_PERIPHERAL_MAP_PMAP_UART1TX 0xb000 +#define DMA_PERIPHERAL_MAP_CTYPE 0x0040 + +#define HMDMA_CONTROL_BDI 0x8000 +#define HMDMA_CONTROL_OI 0x4000 +#define HMDMA_CONTROL_PS 0x2000 +#define HMDMA_CONTROL_RBC 0x1000 +#define HMDMA_CONTROL_DRQ_MASK 0x0300 +#define HMDMA_CONTROL_DRQ_NONE 0x0000 +#define HMDMA_CONTROL_DRQ_SINGLE 0x0100 +#define HMDMA_CONTROL_DRQ_MULTIPLE 0x0200 +#define HMDMA_CONTROL_DRQ_URGENT_MULTIPLE 0x0300 +#define HMDMA_CONTROL_MBDI 0x0040 +#define HMDMA_CONTROL_BDIE 0x0020 +#define HMDMA_CONTROL_OIE 0x0010 +#define HMDMA_CONTROL_UTE 0x0008 +#define HMDMA_CONTROL_REP 0x0002 +#define HMDMA_CONTROL_HMDMAEN 0x0001 + +#endif /* _dmaRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/ebiuRegs.h b/c/src/lib/libcpu/bfin/include/ebiuRegs.h new file mode 100644 index 0000000000..5b07822fbd --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/ebiuRegs.h @@ -0,0 +1,136 @@ +/* Blackfin External Peripheral Interface Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _ebiuRegs_h_ +#define _ebiuRegs_h_ + +/* register addresses */ + +#define EBIU_AMGCTL (EBIU_BASE_ADDRESS + 0x0000) +#define EBIU_AMBCTL0 (EBIU_BASE_ADDRESS + 0x0004) +#define EBIU_AMBCTL1 (EBIU_BASE_ADDRESS + 0x0008) +#define EBIU_SDGCTL (EBIU_BASE_ADDRESS + 0x0010) +#define EBIU_SDBCTL (EBIU_BASE_ADDRESS + 0x0014) +#define EBIU_SDRRC (EBIU_BASE_ADDRESS + 0x0018) +#define EBIU_SDSTAT (EBIU_BASE_ADDRESS + 0x001c) + +/* register fields */ + +#define EBIU_AMGCTL_CDPRIO 0x0100 +#define EBIU_AMGCTL_AMBEN_MASK 0x000e +#define EBIU_AMGCTL_AMBEN_SHIFT 1 +#define EBIU_AMGCTL_AMCKEN 0x0001 + +#define EBIU_AMBCTL0_B1WAT_MASK 0xf0000000 +#define EBIU_AMBCTL0_B1WAT_SHIFT 28 +#define EBIU_AMBCTL0_B1RAT_MASK 0x0f000000 +#define EBIU_AMBCTL0_B1RAT_SHIFT 24 +#define EBIU_AMBCTL0_B1HT_MASK 0x00c00000 +#define EBIU_AMBCTL0_B1HT_SHIFT 22 +#define EBIU_AMBCTL0_B1ST_MASK 0x00300000 +#define EBIU_AMBCTL0_B1ST_SHIFT 20 +#define EBIU_AMBCTL0_B1TT_MASK 0x000c0000 +#define EBIU_AMBCTL0_B1TT_SHIFT 18 +#define EBIU_AMBCTL0_B1RDYPOL 0x00020000 +#define EBIU_AMBCTL0_B1RDYEN 0x00010000 +#define EBIU_AMBCTL0_B0WAT_MASK 0x0000f000 +#define EBIU_AMBCTL0_B0WAT_SHIFT 12 +#define EBIU_AMBCTL0_B0RAT_MASK 0x00000f00 +#define EBIU_AMBCTL0_B0RAT_SHIFT 8 +#define EBIU_AMBCTL0_B0HT_MASK 0x000000c0 +#define EBIU_AMBCTL0_B0HT_SHIFT 6 +#define EBIU_AMBCTL0_B0ST_MASK 0x00000030 +#define EBIU_AMBCTL0_B0ST_SHIFT 4 +#define EBIU_AMBCTL0_B0TT_MASK 0x0000000c +#define EBIU_AMBCTL0_B0TT_SHIFT 2 +#define EBIU_AMBCTL0_B0RDYPOL 0x00000002 +#define EBIU_AMBCTL0_B0RDYEN 0x00000001 + +#define EBIU_AMBCTL1_B3WAT_MASK 0xf0000000 +#define EBIU_AMBCTL1_B3WAT_SHIFT 28 +#define EBIU_AMBCTL1_B3RAT_MASK 0x0f000000 +#define EBIU_AMBCTL1_B3RAT_SHIFT 24 +#define EBIU_AMBCTL1_B3HT_MASK 0x00c00000 +#define EBIU_AMBCTL1_B3HT_SHIFT 22 +#define EBIU_AMBCTL1_B3ST_MASK 0x00300000 +#define EBIU_AMBCTL1_B3ST_SHIFT 20 +#define EBIU_AMBCTL1_B3TT_MASK 0x000c0000 +#define EBIU_AMBCTL1_B3TT_SHIFT 18 +#define EBIU_AMBCTL1_B3RDYPOL 0x00020000 +#define EBIU_AMBCTL1_B3RDYEN 0x00010000 +#define EBIU_AMBCTL1_B2WAT_MASK 0x0000f000 +#define EBIU_AMBCTL1_B2WAT_SHIFT 12 +#define EBIU_AMBCTL1_B2RAT_MASK 0x00000f00 +#define EBIU_AMBCTL1_B2RAT_SHIFT 8 +#define EBIU_AMBCTL1_B2HT_MASK 0x000000c0 +#define EBIU_AMBCTL1_B2HT_SHIFT 6 +#define EBIU_AMBCTL1_B2ST_MASK 0x00000030 +#define EBIU_AMBCTL1_B2ST_SHIFT 4 +#define EBIU_AMBCTL1_B2TT_MASK 0x0000000c +#define EBIU_AMBCTL1_B2TT_SHIFT 2 +#define EBIU_AMBCTL1_B2RDYPOL 0x00000002 +#define EBIU_AMBCTL1_B2RDYEN 0x00000001 + +#define EBIU_SDGCTL_CDDBG 0x40000000 +#define EBIU_SDGCTL_TCSR 0x20000000 +#define EBIU_SDGCTL_EMREN 0x10000000 +#define EBIU_SDGCTL_FBBRW 0x04000000 +#define EBIU_SDGCTL_EBUFE 0x02000000 +#define EBIU_SDGCTL_SRFS 0x01000000 +#define EBIU_SDGCTL_PSSE 0x00800000 +#define EBIU_SDGCTL_PSM 0x00400000 +#define EBIU_SDGCTL_PUPSD 0x00200000 +#define EBIU_SDGCTL_TWR_MASK 0x00180000 +#define EBIU_SDGCTL_TWR_SHIFT 19 +#define EBIU_SDGCTL_TRCD_MASK 0x00038000 +#define EBIU_SDGCTL_TRCD_SHIFT 15 +#define EBIU_SDGCTL_TRP_MASK 0x00003800 +#define EBIU_SDGCTL_TRP_SHIFT 11 +#define EBIU_SDGCTL_TRAS_MASK 0x000003c0 +#define EBIU_SDGCTL_TRAS_SHIFT 6 +#define EBIU_SDGCTL_PASR_MASK 0x00000030 +#define EBIU_SDGCTL_PASR_ALL 0x00000000 +#define EBIU_SDGCTL_PASR_0_1 0x00000010 +#define EBIU_SDGCTL_PASR_0 0x00000020 +#define EBIU_SDGCTL_CL_MASK 0x0000000c +#define EBIU_SDGCTL_CL_SHIFT 2 +#define EBIU_SDGCTL_SCTLE 0x00000001 + +#define EBIU_SDBCTL_EBCAW_MASK 0x0030 +#define EBIU_SDBCTL_SHIFT 4 +#define EBIU_SDBCTL_EBCAW_8 0x0000 +#define EBIU_SDBCTL_EBCAW_9 0x0010 +#define EBIU_SDBCTL_EBCAW_10 0x0020 +#define EBIU_SDBCTL_EBCAW_11 0x0030 +#define EBIU_SDBCTL_EBSZ_MASK 0x000e +#define EBIU_SDBCTL_EBSZ_SHIFT 1 +#define EBIU_SDBCTL_EBSZ_16M 0x0000 +#define EBIU_SDBCTL_EBSZ_32M 0x0002 +#define EBIU_SDBCTL_EBSZ_64M 0x0004 +#define EBIU_SDBCTL_EBSZ_128M 0x0006 +#define EBIU_SDBCTL_EBSZ_256M 0x0008 +#define EBIU_SDBCTL_EBSZ_512M 0x000a +#define EBIU_SDBCTL_EBE 0x0001 + +#define EBIU_SDRRC_RDIV_MASK 0x0fff +#define EBIU_SDRRC_RDIV_SHIFT 0 + +#define EBIU_SDSTAT_BGSTAT 0x0020 +#define EBIU_SDSTAT_SDEASE 0x0010 +#define EBIU_SDSTAT_SDRS 0x0008 +#define EBIU_SDSTAT_SDPUA 0x0004 +#define EBIU_SDSTAT_SDSRA 0x0002 +#define EBIU_SDSTAT_SDCI 0x0001 + + +#endif /* _ebiuRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/ethernetRegs.h b/c/src/lib/libcpu/bfin/include/ethernetRegs.h new file mode 100644 index 0000000000..dc4b3fbc8f --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/ethernetRegs.h @@ -0,0 +1,422 @@ +/* Blackfin Ethernet Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _ethernetRegs_h_ +#define _ethernetRegs_h_ + +/* register addresses */ + +#define EMAC_OPMODE_OFFSET 0x0000 +#define EMAC_ADDRLO_OFFSET 0x0004 +#define EMAC_ADDRHI_OFFSET 0x0008 +#define EMAC_HASHLO_OFFSET 0x000c +#define EMAC_HASHHI_OFFSET 0x0010 +#define EMAC_STAADD_OFFSET 0x0014 +#define EMAC_STADAT_OFFSET 0x0018 +#define EMAC_FLC_OFFSET 0x001c +#define EMAC_VLAN1_OFFSET 0x0020 +#define EMAC_VLAN2_OFFSET 0x0024 +#define EMAC_WKUP_CTL_OFFSET 0x002c +#define EMAC_WKUP_FFMSK0_OFFSET 0x0030 +#define EMAC_WKUP_FFMSK1_OFFSET 0x0034 +#define EMAC_WKUP_FFMSK2_OFFSET 0x0038 +#define EMAC_WKUP_FFMSK3_OFFSET 0x003c +#define EMAC_WKUP_FFCMD_OFFSET 0x0040 +#define EMAC_WKUP_FFOFF_OFFSET 0x0044 +#define EMAC_WKUP_FFCRC01_OFFSET 0x0048 +#define EMAC_WKUP_FFCRC23_OFFSET 0x004c +#define EMAC_SYSCTL_OFFSET 0x0060 +#define EMAC_SYSTAT_OFFSET 0x0064 +#define EMAC_RX_STAT_OFFSET 0x0068 +#define EMAC_RX_STKY_OFFSET 0x006c +#define EMAC_RX_IRQE_OFFSET 0x0070 +#define EMAC_TX_STAT_OFFSET 0x0074 +#define EMAC_TX_STKY_OFFSET 0x0078 +#define EMAC_TX_IRQE_OFFSET 0x007c +#define EMAC_MMC_CTL_OFFSET 0x0080 +#define EMAC_MMC_RIRQS_OFFSET 0x0084 +#define EMAC_MMC_RIRQE_OFFSET 0x0088 +#define EMAC_MMC_TIRQS_OFFSET 0x008c +#define EMAC_MMC_TIRQE_OFFSET 0x0090 + +#define EMAC_RXC_OK_OFFSET 0x0100 +#define EMAC_RXC_FCS_OFFSET 0x0104 +#define EMAC_RXC_ALIGN_OFFSET 0x0108 +#define EMAC_RXC_OCTET_OFFSET 0x010c +#define EMAC_RXC_DMAOVF_OFFSET 0x0110 +#define EMAC_RXC_UNICST_OFFSET 0x0114 +#define EMAC_RXC_MULTI_OFFSET 0x0118 +#define EMAC_RXC_BROAD_OFFSET 0x011c +#define EMAC_RXC_LNERRI_OFFSET 0x0120 +#define EMAC_RXC_LNERRO_OFFSET 0x0124 +#define EMAC_RXC_LONG_OFFSET 0x0128 +#define EMAC_RXC_MACCTL_OFFSET 0x012c +#define EMAC_RXC_OPCODE_OFFSET 0x0130 +#define EMAC_RXC_PAUSE_OFFSET 0x0134 +#define EMAC_RXC_ALLFRM_OFFSET 0x0138 +#define EMAC_RXC_ALLOCT_OFFSET 0x013c +#define EMAC_RXC_TYPED_OFFSET 0x0140 +#define EMAC_RXC_SHORT_OFFSET 0x0144 +#define EMAC_RXC_EQ64_OFFSET 0x0148 +#define EMAC_RXC_LT128_OFFSET 0x014c +#define EMAC_RXC_LT256_OFFSET 0x0150 +#define EMAC_RXC_LT512_OFFSET 0x0154 +#define EMAC_RXC_LT1024_OFFSET 0x0158 +#define EMAC_RXC_GE1024_OFFSET 0x015c + +#define EMAC_TXC_OK_OFFSET 0x0180 +#define EMAC_TXC_1COL_OFFSET 0x0184 +#define EMAC_TXC_GT1COL_OFFSET 0x0188 +#define EMAC_TXC_OCTET_OFFSET 0x018c +#define EMAC_TXC_DEFER_OFFSET 0x0190 +#define EMAC_TXC_LATECL_OFFSET 0x0194 +#define EMAC_TXC_XS_COL_OFFSET 0x0198 +#define EMAC_TXC_DMAUND_OFFSET 0x019c +#define EMAC_TXC_CRSERR_OFFSET 0x01a0 +#define EMAC_TXC_UNICST_OFFSET 0x01a4 +#define EMAC_TXC_MULTI_OFFSET 0x01a8 +#define EMAC_TXC_BROAD_OFFSET 0x01ac +#define EMAC_TXC_ES_DFR_OFFSET 0x01b0 +#define EMAC_TXC_MACCTL_OFFSET 0x01b4 +#define EMAC_TXC_ALLFRM_OFFSET 0x01b8 +#define EMAC_TXC_ALLOCT_OFFSET 0x01bc +#define EMAC_TXC_EQ64_OFFSET 0x01c0 +#define EMAC_TXC_LT128_OFFSET 0x01c4 +#define EMAC_TXC_LT256_OFFSET 0x01c8 +#define EMAC_TXC_LT512_OFFSET 0x01cc +#define EMAC_TXC_LT1024_OFFSET 0x01d0 +#define EMAC_TXC_GE1024_OFFSET 0x01d4 +#define EMAC_TXC_ABORT_OFFSET 0x01d8 + + +/* register fields */ + +#define EMAC_OPMODE_DRO 0x10000000 +#define EMAC_OPMODE_LB 0x08000000 +#define EMAC_OPMODE_FDMODE 0x04000000 +#define EMAC_OPMODE_RMII_10 0x02000000 +#define EMAC_OPMODE_RMII 0x01000000 +#define EMAC_OPMODE_LCTRE 0x00800000 +#define EMAC_OPMODE_DRTY 0x00400000 +#define EMAC_OPMODE_BOLMT_MASK 0x00300000 +#define EMAC_OPMODE_BOLMT_1023 0x00000000 +#define EMAC_OPMODE_BOLMT_255 0x00100000 +#define EMAC_OPMODE_BOLMT_15 0x00200000 +#define EMAC_OPMODE_BOLMT_1 0x00300000 +#define EMAC_OPMODE_DC 0x00080000 +#define EMAC_OPMODE_DTXCRC 0x00040000 +#define EMAC_OPMODE_DTXPAD 0x00020000 +#define EMAC_OPMODE_TE 0x00010000 +#define EMAC_OPMODE_RAF 0x00001000 +#define EMAC_OPMODE_PSF 0x00000800 +#define EMAC_OPMODE_PBF 0x00000400 +#define EMAC_OPMODE_DBF 0x00000200 +#define EMAC_OPMODE_IFE 0x00000100 +#define EMAC_OPMODE_PR 0x00000080 +#define EMAC_OPMODE_PAM 0x00000040 +#define EMAC_OPMODE_HM 0x00000020 +#define EMAC_OPMODE_HU 0x00000010 +#define EMAC_OPMODE_ASTP 0x00000002 +#define EMAC_OPMODE_RE 0x00000001 + +#define EMAC_STAADD_PHYAD_MASK 0x0000f800 +#define EMAC_STAADD_PHYAD_SHIFT 11 +#define EMAC_STAADD_REGAD_MASK 0x000007c0 +#define EMAC_STAADD_REGAD_SHIFT 6 +#define EMAC_STAADD_STAIE 0x00000008 +#define EMAC_STAADD_STADISPRE 0x00000004 +#define EMAC_STAADD_STAOP 0x00000002 +#define EMAC_STAADD_STABUSY 0x00000001 + +#define EMAC_FLC_FLCPAUSE_MASK 0xffff0000 +#define EMAC_FLC_FLCPAUSE_SHIFT 16 +#define EMAC_FLC_BKPRSEN 0x00000008 +#define EMAC_FLC_PCF 0x00000004 +#define EMAC_FLC_FLCE 0x00000002 +#define EMAC_FLC_FLCBUSY 0x00000001 + +#define EMAC_WKUP_CTL_RWKS_MASK 0x00000f00 +#define EMAC_WKUP_CTL_RWKS_SHIFT 8 +#define EMAC_WKUP_CTL_MPKS 0x00000020 +#define EMAC_WKUP_CTL_GUWKE 0x00000008 +#define EMAC_WKUP_CTL_RWKE 0x00000004 +#define EMAC_WKUP_CTL_MPKE 0x00000002 +#define EMAC_WKUP_CTL_CAPWKFRM 0x00000001 + +#define EMAC_WKUP_FFCMD_3_TYPE 0x08000000 +#define EMAC_WKUP_FFCMD_3_EN 0x01000000 +#define EMAC_WKUP_FFCMD_2_TYPE 0x00080000 +#define EMAC_WKUP_FFCMD_2_EN 0x00010000 +#define EMAC_WKUP_FFCMD_1_TYPE 0x00000800 +#define EMAC_WKUP_FFCMD_1_EN 0x00000100 +#define EMAC_WKUP_FFCMD_0_TYPE 0x00000008 +#define EMAC_WKUP_FFCMD_0_EN 0x00000001 + +#define EMAC_WKUP_FFOFF_3_MASK 0xff000000 +#define EMAC_WKUP_FFOFF_3_SHIFT 24 +#define EMAC_WKUP_FFOFF_2_MASK 0x00ff0000 +#define EMAC_WKUP_FFOFF_2_SHIFT 16 +#define EMAC_WKUP_FFOFF_1_MASK 0x0000ff00 +#define EMAC_WKUP_FFOFF_1_SHIFT 8 +#define EMAC_WKUP_FFOFF_0_MASK 0x000000ff +#define EMAC_WKUP_FFOFF_0_SHIFT 0 + +#define EMAC_WKUP_FFCRC01_1_MASK 0xffff0000 +#define EMAC_WKUP_FFCRC01_1_SHIFT 16 +#define EMAC_WKUP_FFCRC01_0_MASK 0x0000ffff +#define EMAC_WKUP_FFCRC01_0_SHIFT 0 + +#define EMAC_WKUP_FFCRC23_3_MASK 0xffff0000 +#define EMAC_WKUP_FFCRC23_3_SHIFT 16 +#define EMAC_WKUP_FFCRC23_2_MASK 0x0000ffff +#define EMAC_WKUP_FFCRC23_2_SHIFT 0 + +#define EMAC_SYSCTL_MDCDIV_MASK 0x00003f00 +#define EMAC_SYSCTL_MDCDIV_SHIFT 8 +#define EMAC_SYSCTL_TXDWA 0x00000010 +#define EMAC_SYSCTL_RXCKS 0x00000004 +#define EMAC_SYSCTL_RXDWA 0x00000002 +#define EMAC_SYSCTL_PHYIE 0x00000001 + +#define EMAC_SYSTAT_STMDONE 0x00000080 +#define EMAC_SYSTAT_TXDMAERR 0x00000040 +#define EMAC_SYSTAT_RXDMAERR 0x00000020 +#define EMAC_SYSTAT_WAKEDET 0x00000010 +#define EMAC_SYSTAT_TXFSINT 0x00000008 +#define EMAC_SYSTAT_RXFSINT 0x00000004 +#define EMAC_SYSTAT_MMCINT 0x00000002 +#define EMAC_SYSTAT_PHYINT 0x00000001 + +#define EMAC_RX_STAT_RX_ACCEPT 0x80000000 +#define EMAC_RX_STAT_RX_VLAN2 0x40000000 +#define EMAC_RX_STAT_RX_VLAN1 0x20000000 +#define EMAC_RX_STAT_RX_TYPE 0x10000000 +#define EMAC_RX_STAT_RX_UCTL 0x08000000 +#define EMAC_RX_STAT_RX_CTL 0x04000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_MASK 0x03000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL 0x03000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST 0x02000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP 0x01000000 +#define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST 0x00000000 +#define EMAC_RX_STAT_RX_RANGE 0x00800000 +#define EMAC_RX_STAT_RX_LATE 0x00400000 +#define EMAC_RX_STAT_RX_PHY 0x00200000 +#define EMAC_RX_STAT_RX_DMAO 0x00100000 +#define EMAC_RX_STAT_RX_ADDR 0x00080000 +#define EMAC_RX_STAT_RX_FRAG 0x00040000 +#define EMAC_RX_STAT_RX_LEN 0x00020000 +#define EMAC_RX_STAT_RX_CRC 0x00010000 +#define EMAC_RX_STAT_RX_ALIGN 0x00008000 +#define EMAC_RX_STAT_RX_LONG 0x00004000 +#define EMAC_RX_STAT_RX_OK 0x00002000 +#define EMAC_RX_STAT_RX_COMP 0x00001000 +#define EMAC_RX_STAT_RX_FRLEN_MASK 0x000007ff +#define EMAC_RX_STAT_RX_FRLEN_SHIFT 0 + +#define EMAC_RX_STKY_RX_ACCEPT 0x80000000 +#define EMAC_RX_STKY_RX_VLAN2 0x40000000 +#define EMAC_RX_STKY_RX_VLAN1 0x20000000 +#define EMAC_RX_STKY_RX_TYPE 0x10000000 +#define EMAC_RX_STKY_RX_UCTL 0x08000000 +#define EMAC_RX_STKY_RX_CTL 0x04000000 +#define EMAC_RX_STKY_RX_BROAD 0x02000000 +#define EMAC_RX_STKY_RX_MULTI 0x01000000 +#define EMAC_RX_STKY_RX_RANGE 0x00800000 +#define EMAC_RX_STKY_RX_LATE 0x00400000 +#define EMAC_RX_STKY_RX_PHY 0x00200000 +#define EMAC_RX_STKY_RX_DMAO 0x00100000 +#define EMAC_RX_STKY_RX_ADDR 0x00080000 +#define EMAC_RX_STKY_RX_FRAG 0x00040000 +#define EMAC_RX_STKY_RX_LEN 0x00020000 +#define EMAC_RX_STKY_RX_CRC 0x00010000 +#define EMAC_RX_STKY_RX_ALIGN 0x00008000 +#define EMAC_RX_STKY_RX_LONG 0x00004000 +#define EMAC_RX_STKY_RX_OK 0x00002000 +#define EMAC_RX_STKY_RX_COMP 0x00001000 + +#define EMAC_RX_IRQE_RX_ACCEPT 0x80000000 +#define EMAC_RX_IRQE_RX_VLAN2 0x40000000 +#define EMAC_RX_IRQE_RX_VLAN1 0x20000000 +#define EMAC_RX_IRQE_RX_TYPE 0x10000000 +#define EMAC_RX_IRQE_RX_UCTL 0x08000000 +#define EMAC_RX_IRQE_RX_CTL 0x04000000 +#define EMAC_RX_IRQE_RX_BROAD 0x02000000 +#define EMAC_RX_IRQE_RX_MULTI 0x01000000 +#define EMAC_RX_IRQE_RX_RANGE 0x00800000 +#define EMAC_RX_IRQE_RX_LATE 0x00400000 +#define EMAC_RX_IRQE_RX_PHY 0x00200000 +#define EMAC_RX_IRQE_RX_DMAO 0x00100000 +#define EMAC_RX_IRQE_RX_ADDR 0x00080000 +#define EMAC_RX_IRQE_RX_FRAG 0x00040000 +#define EMAC_RX_IRQE_RX_LEN 0x00020000 +#define EMAC_RX_IRQE_RX_CRC 0x00010000 +#define EMAC_RX_IRQE_RX_ALIGN 0x00008000 +#define EMAC_RX_IRQE_RX_LONG 0x00004000 +#define EMAC_RX_IRQE_RX_OK 0x00002000 +#define EMAC_RX_IRQE_RX_COMP 0x00001000 + +#define EMAC_TX_STAT_TX_FRLEN_MASK 0x07ff0000 +#define EMAC_TX_STAT_TX_FRLEN_SHIFT 16 +#define EMAC_TX_STAT_TX_RETRY 0x00008000 +#define EMAC_TX_STAT_TX_LOSS 0x00004000 +#define EMAC_TX_STAT_TX_CRS 0x00002000 +#define EMAC_TX_STAT_TX_DEFER 0x00001000 +#define EMAC_TX_STAT_TX_CCNT_MASK 0x00000f00 +#define EMAC_TX_STAT_TX_CCNT_SHIFT 8 +#define EMAC_TX_STAT_TX_MULTI_BROAD_MASK 0x000000c0 +#define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL 0x000000c0 +#define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP 0x00000080 +#define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST 0x00000040 +#define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST 0x00000000 +#define EMAC_TX_STAT_TX_EDEFER 0x00000020 +#define EMAC_TX_STAT_TX_DMAU 0x00000010 +#define EMAC_TX_STAT_TX_LATE 0x00000008 +#define EMAC_TX_STAT_TX_ECOLL 0x00000004 +#define EMAC_TX_STAT_TX_OK 0x00000002 +#define EMAC_TX_STAT_TX_COMP 0x00000001 + +#define EMAC_TX_STKY_TX_RETRY 0x00008000 +#define EMAC_TX_STKY_TX_LOSS 0x00004000 +#define EMAC_TX_STKY_TX_CRS 0x00002000 +#define EMAC_TX_STKY_TX_DEFER 0x00001000 +#define EMAC_TX_STKY_TX_CCNT_MASK 0x00000f00 +#define EMAC_TX_STKY_TX_CCNT_SHIFT 8 +#define EMAC_TX_STKY_TX_MULTI 0x00000080 +#define EMAC_TX_STKY_TX_BROAD 0x00000040 +#define EMAC_TX_STKY_TX_EDEFER 0x00000020 +#define EMAC_TX_STKY_TX_DMAU 0x00000010 +#define EMAC_TX_STKY_TX_LATE 0x00000008 +#define EMAC_TX_STAT_TX_ECOLL 0x00000004 +#define EMAC_TX_STAT_TX_OK 0x00000002 +#define EMAC_TX_STAT_TX_COMP 0x00000001 + +#define EMAC_TX_IRQE_TX_RETRY 0x00008000 +#define EMAC_TX_IRQE_TX_LOSS 0x00004000 +#define EMAC_TX_IRQE_TX_CRS 0x00002000 +#define EMAC_TX_IRQE_TX_DEFER 0x00001000 +#define EMAC_TX_IRQE_TX_CCNT_MASK 0x00000f00 +#define EMAC_TX_IRQE_TX_CCNT_SHIFT 8 +#define EMAC_TX_IRQE_TX_MULTI 0x00000080 +#define EMAC_TX_IRQE_TX_BROAD 0x00000040 +#define EMAC_TX_IRQE_TX_EDEFER 0x00000020 +#define EMAC_TX_IRQE_TX_DMAU 0x00000010 +#define EMAC_TX_IRQE_TX_LATE 0x00000008 +#define EMAC_TX_IRQE_TX_ECOLL 0x00000004 +#define EMAC_TX_IRQE_TX_OK 0x00000002 +#define EMAC_TX_IRQE_TX_COMP 0x00000001 + +#define EMAC_MMC_RIRQS_RX_GE1024_CNT 0x00800000 +#define EMAC_MMC_RIRQS_RX_LT1024_CNT 0x00400000 +#define EMAC_MMC_RIRQS_RX_LT512_CNT 0x00200000 +#define EMAC_MMC_RIRQS_RX_LT256_CNT 0x00100000 +#define EMAC_MMC_RIRQS_RX_LT128_CNT 0x00080000 +#define EMAC_MMC_RIRQS_RX_EQ64_CNT 0x00040000 +#define EMAC_MMC_RIRQS_RX_SHORT_CNT 0x00020000 +#define EMAC_MMC_RIRQS_RX_TYPED_CNT 0x00010000 +#define EMAC_MMC_RIRQS_RX_ALLO_CNT 0x00008000 +#define EMAC_MMC_RIRQS_RX_ALLF_CNT 0x00004000 +#define EMAC_MMC_RIRQS_RX_PAUSE_CNT 0x00002000 +#define EMAC_MMC_RIRQS_RX_OPCODE_CNT 0x00001000 +#define EMAC_MMC_RIRQS_RX_MACCTL_CNT 0x00000800 +#define EMAC_MMC_RIRQS_RX_LONG_CNT 0x00000400 +#define EMAC_MMC_RIRQS_RX_ORL_CNT 0x00000200 +#define EMAC_MMC_RIRQS_RX_IRL_CNT 0x00000100 +#define EMAC_MMC_RIRQS_RX_BROAD_CNT 0x00000080 +#define EMAC_MMC_RIRQS_RX_MULTI_CNT 0x00000040 +#define EMAC_MMC_RIRQS_RX_UNI_CNT 0x00000020 +#define EMAC_MMC_RIRQS_RX_LOST_CNT 0x00000010 +#define EMAC_MMC_RIRQS_RX_OCTET_CNT 0x00000008 +#define EMAC_MMC_RIRQS_RX_ALIGN_CNT 0x00000004 +#define EMAC_MMC_RIRQS_RX_FCS_CNT 0x00000002 +#define EMAC_MMC_RIRQS_RX_OK_CNT 0x00000001 + +#define EMAC_MMC_RIRQE_RX_GE1024_CNT 0x00800000 +#define EMAC_MMC_RIRQE_RX_LT1024_CNT 0x00400000 +#define EMAC_MMC_RIRQE_RX_LT512_CNT 0x00200000 +#define EMAC_MMC_RIRQE_RX_LT256_CNT 0x00100000 +#define EMAC_MMC_RIRQE_RX_LT128_CNT 0x00080000 +#define EMAC_MMC_RIRQE_RX_EQ64_CNT 0x00040000 +#define EMAC_MMC_RIRQE_RX_SHORT_CNT 0x00020000 +#define EMAC_MMC_RIRQE_RX_TYPED_CNT 0x00010000 +#define EMAC_MMC_RIRQE_RX_ALLO_CNT 0x00008000 +#define EMAC_MMC_RIRQE_RX_ALLF_CNT 0x00004000 +#define EMAC_MMC_RIRQE_RX_PAUSE_CNT 0x00002000 +#define EMAC_MMC_RIRQE_RX_OPCODE_CNT 0x00001000 +#define EMAC_MMC_RIRQE_RX_MACCTL_CNT 0x00000800 +#define EMAC_MMC_RIRQE_RX_LONG_CNT 0x00000400 +#define EMAC_MMC_RIRQE_RX_ORL_CNT 0x00000200 +#define EMAC_MMC_RIRQE_RX_IRL_CNT 0x00000100 +#define EMAC_MMC_RIRQE_RX_BROAD_CNT 0x00000080 +#define EMAC_MMC_RIRQE_RX_MULTI_CNT 0x00000040 +#define EMAC_MMC_RIRQE_RX_UNI_CNT 0x00000020 +#define EMAC_MMC_RIRQE_RX_LOST_CNT 0x00000010 +#define EMAC_MMC_RIRQE_RX_OCTET_CNT 0x00000008 +#define EMAC_MMC_RIRQE_RX_ALIGN_CNT 0x00000004 +#define EMAC_MMC_RIRQE_RX_FCS_CNT 0x00000002 +#define EMAC_MMC_RIRQE_RX_OK_CNT 0x00000001 + +#define EMAC_MMC_TIRQS_TX_ABORT_CNT 0x00400000 +#define EMAC_MMC_TIRQS_TX_GE1024_CNT 0x00200000 +#define EMAC_MMC_TIRQS_TX_LT1024_CNT 0x00100000 +#define EMAC_MMC_TIRQS_TX_LT512_CNT 0x00080000 +#define EMAC_MMC_TIRQS_TX_LT256_CNT 0x00040000 +#define EMAC_MMC_TIRQS_TX_LT128_CNT 0x00020000 +#define EMAC_MMC_TIRQS_TX_EQ64_CNT 0x00010000 +#define EMAC_MMC_TIRQS_TX_ALLO_CNT 0x00008000 +#define EMAC_MMC_TIRQS_TX_ALLF_CNT 0x00004000 +#define EMAC_MMC_TIRQS_TX_MACCTL_CNT 0x00002000 +#define EMAC_MMC_TIRQS_TX_EXDEF_CNT 0x00001000 +#define EMAC_MMC_TIRQS_TX_BROAD_CNT 0x00000800 +#define EMAC_MMC_TIRQS_TX_MULTI_CNT 0x00000400 +#define EMAC_MMC_TIRQS_TX_UNI_CNT 0x00000200 +#define EMAC_MMC_TIRQS_TX_CRS_CNT 0x00000100 +#define EMAC_MMC_TIRQS_TX_LOST_CNT 0x00000080 +#define EMAC_MMC_TIRQS_TX_ABORTC_CNT 0x00000040 +#define EMAC_MMC_TIRQS_TX_LATE_CNT 0x00000020 +#define EMAC_MMC_TIRQS_TX_DEFER_CNT 0x00000010 +#define EMAC_MMC_TIRQS_TX_OCTET_CNT 0x00000008 +#define EMAC_MMC_TIRQS_TX_MCOLL_CNT 0x00000004 +#define EMAC_MMC_TIRQS_TX_SCOLL_CNT 0x00000002 +#define EMAC_MMC_TIRQS_TX_OK_CNT 0x00000001 + +#define EMAC_MMC_TIRQE_TX_ABORT_CNT 0x00400000 +#define EMAC_MMC_TIRQE_TX_GE1024_CNT 0x00200000 +#define EMAC_MMC_TIRQE_TX_LT1024_CNT 0x00100000 +#define EMAC_MMC_TIRQE_TX_LT512_CNT 0x00080000 +#define EMAC_MMC_TIRQE_TX_LT256_CNT 0x00040000 +#define EMAC_MMC_TIRQE_TX_LT128_CNT 0x00020000 +#define EMAC_MMC_TIRQE_TX_EQ64_CNT 0x00010000 +#define EMAC_MMC_TIRQE_TX_ALLO_CNT 0x00008000 +#define EMAC_MMC_TIRQE_TX_ALLF_CNT 0x00004000 +#define EMAC_MMC_TIRQE_TX_MACCTL_CNT 0x00002000 +#define EMAC_MMC_TIRQE_TX_EXDEF_CNT 0x00001000 +#define EMAC_MMC_TIRQE_TX_BROAD_CNT 0x00000800 +#define EMAC_MMC_TIRQE_TX_MULTI_CNT 0x00000400 +#define EMAC_MMC_TIRQE_TX_UNI_CNT 0x00000200 +#define EMAC_MMC_TIRQE_TX_CRS_CNT 0x00000100 +#define EMAC_MMC_TIRQE_TX_LOST_CNT 0x00000080 +#define EMAC_MMC_TIRQE_TX_ABORTC_CNT 0x00000040 +#define EMAC_MMC_TIRQE_TX_LATE_CNT 0x00000020 +#define EMAC_MMC_TIRQE_TX_DEFER_CNT 0x00000010 +#define EMAC_MMC_TIRQE_TX_OCTET_CNT 0x00000008 +#define EMAC_MMC_TIRQE_TX_MCOLL_CNT 0x00000004 +#define EMAC_MMC_TIRQE_TX_SCOLL_CNT 0x00000002 +#define EMAC_MMC_TIRQE_TX_OK_CNT 0x00000001 + +#define EMAC_MMC_CTL_MMCE 0x00000008 +#define EMAC_MMC_CTL_CCOR 0x00000004 +#define EMAC_MMC_CTL_CROLL 0x00000002 +#define EMAC_MMC_CTL_RSTC 0x00000001 + + +#endif /* _ethernetRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/gpioRegs.h b/c/src/lib/libcpu/bfin/include/gpioRegs.h new file mode 100644 index 0000000000..19db75ea7a --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/gpioRegs.h @@ -0,0 +1,39 @@ +/* Blackfin GPIO Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _gpioRegs_h_ +#define _gpioRegs_h_ + + +/* register addresses */ + +#define PORTIO_OFFSET 0x0000 +#define PORTIO_CLEAR_OFFSET 0x0004 +#define PORTIO_SET_OFFSET 0x0008 +#define PORTIO_TOGGLE_OFFSET 0x000c +#define PORTIO_MASKA_OFFSET 0x0010 +#define PORTIO_MASKA_CLEAR_OFFSET 0x0014 +#define PORTIO_MASKA_SET_OFFSET 0x0018 +#define PORTIO_MASKA_TOGGLE_OFFSET 0x001c +#define PORTIO_MASKB_OFFSET 0x0020 +#define PORTIO_MASKB_CLEAR_OFFSET 0x0024 +#define PORTIO_MASKB_SET_OFFSET 0x0028 +#define PORTIO_MASKB_TOGGLE_OFFSET 0x002c +#define PORTIO_DIR_OFFSET 0x0030 +#define PORTIO_POLAR_OFFSET 0x0034 +#define PORTIO_EDGE_OFFSET 0x0038 +#define PORTIO_BOTH_OFFSET 0x003c +#define PORTIO_INEN_OFFSET 0x0040 + + +#endif /* _gpioRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/memoryRegs.h b/c/src/lib/libcpu/bfin/include/memoryRegs.h new file mode 100644 index 0000000000..616d0381fc --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/memoryRegs.h @@ -0,0 +1,61 @@ +/* Blackfin Memory Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _memoryRegs_h_ +#define _memoryRegs_h_ + +/* register addresses */ +#define DMEM_CONTROL 0xffe00004 +#define DTEST_COMMAND 0xffe00300 +#define DTEST_DATA0 0xffe00400 +#define DTEST_DATA1 0xffe00404 + +#define IMEM_CONTROL 0xffe01004 + + +/* register fields */ +#define DMEM_CONTROL_PORT_PREF1 0x00002000 +#define DMEM_CONTROL_PORT_PREF0 0x00001000 +#define DMEM_CONTROL_DCBS 0x00000010 +#define DMEM_CONTROL_DMC_MASK 0x0000000c +#define DMEM_CONTROL_DMC_SHIFT 2 +#define DMEM_CONTROL_ENDCPLB 0x00000002 + +#define DTEST_COMMAND_ACCESS_WAY1 0x02000000 +#define DTEST_COMMAND_ACCESS_INSTRUCTION 0x01000000 +#define DTEST_COMMAND_ACCESS_BANKB 0x00800000 +#define DTEST_COMMAND_SRAM_ADDR_13_12_MASK 0x00030000 +#define DTEST_COMMAND_SRAM_ADDR_13_12_SHIFT 16 +#define DTEST_COMMAND_DATA_CACHE_SELECT 0x00004000 +#define DTEST_COMMAND_SET_INDEX_MASK 0x000007e0 +#define DTEST_COMMAND_SET_INDEX_SHIFT 5 +#define DTEST_COMMAND_DOUBLE_WORD_INDEX_MASK 0x00000018 +#define DTEST_COMMAND_DOUBLE_WORD_INDEX_SHIFT 3 +#define DTEST_COMMAND_ACCESS_DATA_ARRAY 0x00000004 +#define DTEST_COMMAND_WRITE_ACCESS 0x00000002 + +#define DTEST_DATA0_TAG_19_2_MASK 0xffffc000 +#define DTEST_DATA0_TAG_19_2_SHIFT 14 +#define DTEST_DATA0_TAG 0x00000800 +#define DTEST_DATA0_LRU 0x00000004 +#define DTEST_DATA0_DIRTY 0x00000002 +#define DTEST_DATA0_VALID 0x00000001 + +#define IMEM_CONTROL_LRUPRIORST 0x00002000 +#define IMEM_CONTROL_ILOC_MASK 0x00000078 +#define IMEM_CONTROL_ILOC_SHIFT 3 +#define IMEM_CONTROL_IMC 0x00000004 +#define IMEM_CONTROL_ENICPLB 0x00000002 + + +#endif /* _memoryRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/mmuRegs.h b/c/src/lib/libcpu/bfin/include/mmuRegs.h new file mode 100644 index 0000000000..bee11ce0e9 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/mmuRegs.h @@ -0,0 +1,57 @@ +/* Blackfin MMU Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _mmuRegs_h_ +#define _mmuRegs_h_ + +/* register addresses */ +#define DCPLB_ADDR0 0xffe00100 +#define DCPLB_DATA0 0xffe00200 +#define DCPLB_COUNT 16 +#define DCPLB_ADDR_PITCH 4 +#define DCPLB_DATA_PITCH 4 +#define ICPLB_ADDR0 0xffe01100 +#define ICPLB_DATA0 0xffe01200 +#define ICPLB_COUNT 16 +#define ICPLB_ADDR_PITCH 4 +#define ICPLB_DATA_PITCH 4 + + +/* register fields */ +#define DCPLB_DATA_PAGE_SIZE_MASK 0x00030000 +#define DCPLB_DATA_PAGE_SIZE_1KB 0x00000000 +#define DCPLB_DATA_PAGE_SIZE_4KB 0x00010000 +#define DCPLB_DATA_PAGE_SIZE_1MB 0x00020000 +#define DCPLB_DATA_PAGE_SIZE_4MB 0x00030000 +#define DCPLB_DATA_CPLB_L1_AOW 0x00008000 +#define DCPLB_DATA_CPLB_WT 0x00004000 +#define DCPLB_DATA_CPLB_L1_CHBL 0x00001000 +#define DCPLB_DATA_CPLB_DIRTY 0x00000080 +#define DCPLB_DATA_CPLB_SUPV_WR 0x00000010 +#define DCPLB_DATA_CPLB_USER_WR 0x00000008 +#define DCPLB_DATA_CPLB_USER_RD 0x00000004 +#define DCPLB_DATA_CPLB_LOCK 0x00000002 +#define DCPLB_DATA_CPLB_VALID 0x00000001 + +#define ICPLB_DATA_PAGE_SIZE_MASK 0x00030000 +#define ICPLB_DATA_PAGE_SIZE_1KB 0x00000000 +#define ICPLB_DATA_PAGE_SIZE_4KB 0x00010000 +#define ICPLB_DATA_PAGE_SIZE_1MB 0x00020000 +#define ICPLB_DATA_PAGE_SIZE_4MB 0x00030000 +#define ICPLB_DATA_CPLB_L1_CHBL 0x00001000 +#define ICPLB_DATA_CPLB_LRUPRIO 0x00000100 +#define ICPLB_DATA_CPLB_USER_RD 0x00000004 +#define ICPLB_DATA_CPLB_CPLB_LOCK 0x00000002 +#define ICPLB_DATA_CPLB_CPLB_VALID 0x00000001 + +#endif /* _mmuRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/ppiRegs.h b/c/src/lib/libcpu/bfin/include/ppiRegs.h new file mode 100644 index 0000000000..0b7fdd28a4 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/ppiRegs.h @@ -0,0 +1,61 @@ +/* Blackfin Parallel Peripheral Interface Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _ppiRegs_h_ +#define _ppiRegs_h_ + + +/* register addresses */ + +#define PPI_CONTROL_OFFSET 0x0000 +#define PPI_STATUS_OFFSET 0x0004 +#define PPI_COUNT_OFFSET 0x0008 +#define PPI_DELAY_OFFSET 0x000c +#define PPI_FRAME_OFFSET 0x0010 + + +/* register fields */ + +#define PPI_CONTROL_POLS 0x8000 +#define PPI_CONTROL_POLC 0x4000 +#define PPI_CONTROL_DLEN_MASK 0x3800 +#define PPI_CONTROL_DLEN_8 0x0000 +#define PPI_CONTROL_DLEN_10 0x0800 +#define PPI_CONTROL_DLEN_11 0x1000 +#define PPI_CONTROL_DLEN_12 0x1800 +#define PPI_CONTROL_DLEN_13 0x2000 +#define PPI_CONTROL_DLEN_14 0x2800 +#define PPI_CONTROL_DLEN_15 0x3000 +#define PPI_CONTROL_DLEN_16 0x3800 +#define PPI_CONTROL_SKIP_EO 0x0400 +#define PPI_CONTROL_SKIP_EN 0x0200 +#define PPI_CONTROL_PACK_EN 0x0080 +#define PPI_CONTROL_FLD_SEL 0x0040 +#define PPI_CONTROL_PORT_CFG_MASK 0x0030 +#define PPI_CONTROL_PORT_CFG_SHIFT 4 +#define PPI_CONTROL_XFR_TYPE_MASK 0x000c +#define PPI_CONTROL_XFR_TYPE_SHIFT 2 +#define PPI_CONTROL_PORT_DIR 0x0002 +#define PPI_CONTROL_PORT_EN 0x0001 + +#define PPI_STATUS_ERR_NCOR 0x8000 +#define PPI_STATUS_ERR_DET 0x4000 +#define PPI_STATUS_UNDR 0x2000 +#define PPI_STATUS_OVR 0x1000 +#define PPI_STATUS_FT_ERR 0x0800 +#define PPI_STATUS_FLD 0x0400 +#define PPI_STATUS_LT_ERR_UNDR 0x0200 +#define PPI_STATUS_LT_ERR_OVR 0x0100 + + +#endif /* _ppiRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/rtcRegs.h b/c/src/lib/libcpu/bfin/include/rtcRegs.h new file mode 100644 index 0000000000..f71372a9f4 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/rtcRegs.h @@ -0,0 +1,68 @@ +/* Blackfin RTC Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _rtcRegs_h_ +#define _rtcRegs_h_ + +/* register addresses */ + +#define RTC_STAT (RTC_BASE_ADDRESS + 0x0000) +#define RTC_ICTL (RTC_BASE_ADDRESS + 0x0004) +#define RTC_ISTAT (RTC_BASE_ADDRESS + 0x0008) +#define RTC_SWCNT (RTC_BASE_ADDRESS + 0x000c) +#define RTC_ALARM (RTC_BASE_ADDRESS + 0x0010) +#define RTC_PREN (RTC_BASE_ADDRESS + 0x0014) + + +/* register fields */ + +#define RTC_STAT_DAYS_MASK 0xfffe0000 +#define RTC_STAT_DAYS_SHIFT 17 +#define RTC_STAT_HOURS_MASK 0x0001f000 +#define RTC_STAT_HOURS_SHIFT 12 +#define RTC_STAT_MINUTES_MASK 0x00000fc0 +#define RTC_STAT_MINUTES_SHIFT 6 +#define RTC_STAT_SECONDS_MASK 0x0000003f +#define RTC_STAT_SECONDS_SHIFT 0 + +#define RTC_ICTL_WCIE 0x8000 +#define RTC_ICTL_DAIE 0x0040 +#define RTC_ICTL_24HIE 0x0020 +#define RTC_ICTL_HIE 0x0010 +#define RTC_ICTL_MIE 0x0008 +#define RTC_ICTL_SIE 0x0004 +#define RTC_ICTL_AIE 0x0002 +#define RTC_ICTL_SWIE 0x0001 + +#define RTC_ISTAT_WC 0x8000 +#define RTC_ISTAT_WP 0x4000 +#define RTC_ISTAT_DAEF 0x0040 +#define RTC_ISTAT_24HE 0x0020 +#define RTC_ISTAT_HEF 0x0010 +#define RTC_ISTAT_MEF 0x0008 +#define RTC_ISTAT_SEF 0x0004 +#define RTC_ISTAT_AEF 0x0002 +#define RTC_ISTAT_SWEF 0x0001 + +#define RTC_ALARM_DAYS_MASK 0xfff70000 +#define RTC_ALARM_DAYS_SHIFT 17 +#define RTC_ALARM_HOURS_MASK 0x0001f000 +#define RTC_ALARM_HOURS_SHIFT 12 +#define RTC_ALARM_MINUTES_MASK 0x00000fc0 +#define RTC_ALARM_MINUTES_SHIFT 10 +#define RTC_ALARM_SECONDS_MASK 0x0000003f +#define RTC_ALARM_SECONDS_SHIFT 0 + +#define RTC_PREN_PREN 0x0001 + +#endif /* _rtcRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/sicRegs.h b/c/src/lib/libcpu/bfin/include/sicRegs.h new file mode 100644 index 0000000000..a3c6c391e1 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/sicRegs.h @@ -0,0 +1,35 @@ +/* Blackfin System Interrupt Controller Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _sicRegs_h_ +#define _sicRegs_h_ + +/* register addresses */ + +#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) +#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) +#define SIC_IAR_COUNT 4 +#define SIC_IAR_PITCH 0x04 +#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) +#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) +#define SIC_IAR2 (SIC_BASE_ADDRESS + 0x0018) +#define SIC_IAR3 (SIC_BASE_ADDRESS + 0x001c) +#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020) +#define SIC_IWR (SIC_BASE_ADDRESS + 0x0024) + + +/* register fields */ + + + +#endif /* _sicRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/spiRegs.h b/c/src/lib/libcpu/bfin/include/spiRegs.h new file mode 100644 index 0000000000..183ee557c7 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/spiRegs.h @@ -0,0 +1,72 @@ +/* Blackfin SPI Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _spiRegs_h_ +#define _spiRegs_h_ + + +/* register addresses */ + +#define SPI_CTL_OFFSET 0x0000 +#define SPI_FLG_OFFSET 0x0004 +#define SPI_STAT_OFFSET 0x0008 +#define SPI_TDBR_OFFSET 0x000c +#define SPI_RDBR_OFFSET 0x0010 +#define SPI_BAUD_OFFSET 0x0014 +#define SPI_SHADOW 0x0018 + + +/* register fields */ + +#define SPI_CTL_SPE 0x4000 +#define SPI_CTL_WOM 0x2000 +#define SPI_CTL_MSTR 0x1000 +#define SPI_CTL_CPOL 0x0800 +#define SPI_CTL_CPHA 0x0400 +#define SPI_CTL_LSBF 0x0200 +#define SPI_CTL_SIZE 0x0100 +#define SPI_CTL_EMISO 0x0020 +#define SPI_CTL_PSSE 0x0010 +#define SPI_CTL_GM 0x0008 +#define SPI_CTL_SZ 0x0004 +#define SPI_CTL_TIMOD_MASK 0x0003 +#define SPI_CTL_TIMOD_RDBR 0x0000 +#define SPI_CTL_TIMOD_TDBR 0x0001 +#define SPI_CTL_TIMOD_DMA_RDBR 0x0002 +#define SPI_CTL_TIMOD_DMA_TDBR 0x0003 + +#define SPI_FLG_FLG7 0x8000 +#define SPI_FLG_FLG6 0x4000 +#define SPI_FLG_FLG5 0x2000 +#define SPI_FLG_FLG4 0x1000 +#define SPI_FLG_FLG3 0x0800 +#define SPI_FLG_FLG2 0x0400 +#define SPI_FLG_FLG1 0x0200 +#define SPI_FLG_FLS7 0x0080 +#define SPI_FLG_FLS6 0x0040 +#define SPI_FLG_FLS5 0x0020 +#define SPI_FLG_FLS4 0x0010 +#define SPI_FLG_FLS3 0x0008 +#define SPI_FLG_FLS2 0x0004 +#define SPI_FLG_FLS1 0x0002 + +#define SPI_STAT_TXCOL 0x0040 +#define SPI_STAT_RXS 0x0020 +#define SPI_STAT_RBSY 0x0010 +#define SPI_STAT_TXS 0x0008 +#define SPI_STAT_TXE 0x0004 +#define SPI_STAT_MODF 0x0002 +#define SPI_STAT_SPIF 0x0001 + + +#endif /* _spiRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/sportRegs.h b/c/src/lib/libcpu/bfin/include/sportRegs.h new file mode 100644 index 0000000000..fd7770ad46 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/sportRegs.h @@ -0,0 +1,114 @@ +/* Blackfin SPORT Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _sportRegs_h_ +#define _sportRegs_h_ + + +/* register addresses */ + +#define SPORT_TCR1_OFFSET 0x0000 +#define SPORT_TCR2_OFFSET 0x0004 +#define SPORT_TCLKDIV_OFFSET 0x0008 +#define SPORT_TFSDIV_OFFSET 0x000c +#define SPORT_TX_OFFSET 0x0010 +#define SPORT_RX_OFFSET 0x0018 +#define SPORT_RCR1_OFFSET 0x0020 +#define SPORT_RCR2_OFFSET 0x0024 +#define SPORT_RCLKDIV_OFFSET 0x0028 +#define SPORT_RFSDIV_OFFSET 0x002c +#define SPORT_STAT_OFFSET 0x0030 +#define SPORT_CHNL_OFFSET 0x0034 +#define SPORT_MCMC1_OFFSET 0x0038 +#define SPORT_MCMC2_OFFSET 0x003c +#define SPORT_MTCS0_OFFSET 0x0040 +#define SPORT_MTCS1_OFFSET 0x0044 +#define SPORT_MTCS2_OFFSET 0x0048 +#define SPORT_MTCS3_OFFSET 0x004c +#define SPORT_MRCS0_OFFSET 0x0050 +#define SPORT_MRCS1_OFFSET 0x0054 +#define SPORT_MRCS2_OFFSET 0x0058 +#define SPORT_MRCS3_OFFSET 0x005c + + +/* register fields */ + +#define SPORT_TCR1_TCKFE 0x4000 +#define SPORT_TCR1_LATFS 0x2000 +#define SPORT_TCR1_LTFS 0x1000 +#define SPORT_TCR1_DITFS 0x0800 +#define SPORT_TCR1_TFSR 0x0400 +#define SPORT_TCR1_ITFS 0x0200 +#define SPORT_TCR1_TLSBIT 0x0010 +#define SPORT_TCR1_TDTYPE_MASK 0x000c +#define SPORT_TCR1_TDTYPE_NORMAL 0x0000 +#define SPORT_TCR1_TDTYPE_ULAW 0x0008 +#define SPORT_TCR1_TDTYPE_ALAW 0x000c +#define SPORT_TCR1_ITCLK 0x0002 +#define SPORT_TCR1_TSPEN 0x0001 + +#define SPORT_TCR2_TRFST 0x0400 +#define SPORT_TCR2_TSFSE 0x0200 +#define SPORT_TCR2_TXSE 0x0100 +#define SPORT_TCR2_SLEN_MASK 0x001f +#define SPORT_TCR2_SLEN_SHIFT 0 + +#define SPORT_RCR1_RCKFE 0x4000 +#define SPORT_RCR1_LARFS 0x2000 +#define SPORT_RCR1_LRFS 0x1000 +#define SPORT_RCR1_RFSR 0x0400 +#define SPORT_RCR1_IRFS 0x0200 +#define SPORT_RCR1_RLSBIT 0x0010 +#define SPORT_RCR1_RDTYPE_MASK 0x000c +#define SPORT_RCR1_RDTYPE_ZEROFILL 0x0000 +#define SPORT_RCR1_RDTYPE_SIGNEXTEND 0x0004 +#define SPORT_RCR1_RDTYPE_ULAW 0x0008 +#define SPORT_RCR1_RDTYPE_ALAW 0x000c +#define SPORT_RCR1_IRCLK 0x0002 +#define SPORT_RCR1_RSPEN 0x0001 + +#define SPORT_RCR2_RRFST 0x0400 +#define SPORT_RCR2_RSFSE 0x0200 +#define SPORT_RCR2_RXSE 0x0100 +#define SPORT_RCR2_SLEN_MASK 0x001f +#define SPORT_RCR2_SLEN_SHIFT 0 + +#define SPORT_STAT_TXHRE 0x0040 +#define SPORT_STAT_TOVF 0x0020 +#define SPORT_STAT_TUVF 0x0010 +#define SPORT_STAT_TXF 0x0008 +#define SPORT_STAT_ROVF 0x0004 +#define SPORT_STAT_RUVF 0x0002 +#define SPORT_STAT_RXNE 0x0001 + +#define SPORT_CHNL_CHNL_MASK 0x03ff +#define SPORT_CHNL_CHNL_SHIFT 0 + +#define SPORT_MCMC1_WSIZE_MASK 0xf000 +#define SPORT_MCMC1_WSIZE_SHIFT 12 +#define SPORT_MCMC1_WOFF_MASK 0x03ff +#define SPORT_MCMC1_WOFF_SHIFT 0 + +#define SPORT_MCMC2_MFD_MASK 0xf000 +#define SPORT_MCMC2_MFD_SHIFT 12 +#define SPORT_MCMC2_FSDR 0x0080 +#define SPORT_MCMC2_MCMEN 0x0010 +#define SPORT_MCMC2_MCDRXPE 0x0008 +#define SPORT_MCMC2_MCDTXPE 0x0004 +#define SPORT_MCMC2_MCCRM_MASK 0x0003 +#define SPORT_MCMC2_MCCRM_BYPASS 0x0000 +#define SPORT_MCMC2_MCCRM_2_4 0x0002 +#define SPORT_MCMC2_MCCRM_8_16 0x0003 + + +#endif /* _sportRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/timerRegs.h b/c/src/lib/libcpu/bfin/include/timerRegs.h new file mode 100644 index 0000000000..db7e13fbcb --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/timerRegs.h @@ -0,0 +1,48 @@ +/* Blackfin General Purpose Timer Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _timerRegs_h_ +#define _timerRegs_h_ + + +/* register addresses */ + +#define TIMER_CONFIG_OFFSET 0x00 +#define TIMER_WIDTH_OFFSET 0x04 +#define TIMER_PERIOD_OFFSET 0x08 +#define TIMER_COUNTER_OFFSET 0x0c + + +/* register fields */ + +#define TIMER_CONFIG_ERR_TYP_MASK 0xc000 +#define TIMER_CONFIG_ERR_TYP_NONE 0x0000 +#define TIMER_CONFIG_ERR_TYP_OVERFLOW 0x4000 +#define TIMER_CONFIG_ERR_TYP_PERIOD 0x8000 +#define TIMER_CONFIG_ERR_TYP_WIDTH 0xc000 +#define TIMER_CONFIG_EMU_RUN 0x0200 +#define TIMER_CONFIG_TOGGLE_HI 0x0100 +#define TIMER_CONFIG_CLK_SEL 0x0080 +#define TIMER_CONFIG_OUT_DIS 0x0040 +#define TIMER_CONFIG_TIN_SEL 0x0020 +#define TIMER_CONFIG_IRQ_ENA 0x0010 +#define TIMER_CONFIG_PERIOD_CNT 0x0008 +#define TIMER_CONFIG_PULSE_HI 0x0004 +#define TIMER_CONFIG_TMODE_MASK 0x0003 +#define TIMER_CONFIG_TMODE_RESET 0x0000 +#define TIMER_CONFIG_TMODE_PWM_OUT 0x0001 +#define TIMER_CONFIG_TMODE_WDTH_CAP 0x0002 +#define TIMER_CONFIG_TMODE_EXT_CLK 0x0003 + + +#endif /* _timerRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/twiRegs.h b/c/src/lib/libcpu/bfin/include/twiRegs.h new file mode 100644 index 0000000000..a5df911908 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/twiRegs.h @@ -0,0 +1,121 @@ +/* Blackfin Two Wire Interface Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _twiRegs_h_ +#define _twiRegs_h_ + + +/* register addresses */ + +#define TWI_CLKDIV_OFFSET 0x0000 +#define TWI_CONTROL_OFFSET 0x0004 +#define TWI_SLAVE_CTL_OFFSET 0x0008 +#define TWI_SLAVE_STAT_OFFSET 0x000c +#define TWI_SLAVE_ADDR_OFFSET 0x0010 +#define TWI_MASTER_CTL_OFFSET 0x0014 +#define TWI_MASTER_STAT_OFFSET 0x0018 +#define TWI_MASTER_ADDR_OFFSET 0x001c +#define TWI_INT_STAT_OFFSET 0x0020 +#define TWI_INT_MASK_OFFSET 0x0024 +#define TWI_FIFO_CTL_OFFSET 0x0028 +#define TWI_FIFO_STAT_OFFSET 0x002c +#define TWI_XMT_DATA8_OFFSET 0x0080 +#define TWI_XMT_DATA16_OFFSET 0x0084 +#define TWI_RCV_DATA8_OFFSET 0x0088 +#define TWI_RCV_DATA16_OFFSET 0x008c + + +/* register fields */ + +#define TWI_CLKDIV_CLKHI_MASK 0xff00 +#define TWI_CLKDIV_CLKHI_SHIFT 8 +#define TWI_CLKDIV_CLKLOW_MASK 0x00ff +#define TWI_CLKDIV_CLKLOW_SHIFT 0 + +#define TWI_CONTROL_SCCB 0x0200 +#define TWI_CONTROL_TWI_ENA 0x0080 +#define TWI_CONTROL_PRESCALE_MASK 0x007f +#define TWI_CONTROL_PRESCALE_SHIFT 0 + +#define TWI_SLAVE_CTL_GEN 0x0010 +#define TWI_SLAVE_CTL_NAK 0x0008 +#define TWI_SLAVE_CTL_STDVAL 0x0004 +#define TWI_SLAVE_CTL_SEN 0x0001 + +#define TWI_SLAVE_STAT_GCALL 0x0002 +#define TWI_SLAVE_STAT_SDIR 0x0001 + +#define TWI_SLAVE_ADDR_SADDR_MASK 0x007f +#define TWI_SLAVE_ADDR_SADDR_SHIFT 0 + +#define TWI_MASTER_CTL_SCLOVR 0x8000 +#define TWI_MASTER_CTL_SDAOVR 0x4000 +#define TWI_MASTER_CTL_DCNT_MASK 0x3fc0 +#define TWI_MASTER_CTL_DCNT_SHIFT 6 +#define TWI_MASTER_CTL_RSTART 0x0020 +#define TWI_MASTER_CTL_STOP 0x0010 +#define TWI_MASTER_CTL_FAST 0x0008 +#define TWI_MASTER_CTL_MDIR 0x0004 +#define TWI_MASTER_CTL_MEN 0x0001 + +#define TWI_MASTER_STAT_BUSBUSY 0x0100 +#define TWI_MASTER_STAT_SCLSEN 0x0080 +#define TWI_MASTER_STAT_SDASEN 0x0040 +#define TWI_MASTER_STAT_BUFWRERR 0x0020 +#define TWI_MASTER_STAT_BUFRDERR 0x0010 +#define TWI_MASTER_STAT_DNAK 0x0008 +#define TWI_MASTER_STAT_ANAK 0x0004 +#define TWI_MASTER_STAT_LOSTARB 0x0002 +#define TWI_MASTER_STAT_MPROG 0x0001 + +#define TWI_MASTER_ADDR_MADDR_MASK 0x007f +#define TWI_MASTER_ADDR_MADDR_SHIFT 0 + +#define TWI_INT_STAT_RCVSERV 0x0080 +#define TWI_INT_STAT_XMTSERV 0x0040 +#define TWI_INT_STAT_MERR 0x0020 +#define TWI_INT_STAT_MCOMP 0x0010 +#define TWI_INT_STAT_SOVF 0x0008 +#define TWI_INT_STAT_SERR 0x0004 +#define TWI_INT_STAT_SCOMP 0x0002 +#define TWI_INT_STAT_SINIT 0x0001 + +#define TWI_INT_MASK_RCVSERVM 0x0080 +#define TWI_INT_MASK_XMTSERVM 0x0040 +#define TWI_INT_MASK_MERRM 0x0020 +#define TWI_INT_MASK_MCOMPM 0x0010 +#define TWI_INT_MASK_SOVFM 0x0008 +#define TWI_INT_MASK_SERRM 0x0004 +#define TWI_INT_MASK_SCOMPM 0x0002 +#define TWI_INT_MASK_SINITM 0x0001 + +#define TWI_FIFO_CTL_RCVINTLEN 0x0008 +#define TWI_FIFO_CTL_XMTINTLEN 0x0004 +#define TWI_FIFO_CTL_RCVFLUSH 0x0002 +#define TWI_FIFO_CTL_XMTFLUSH 0x0001 + +#define TWI_FIFO_STAT_RCVSTAT_MASK 0x000c +#define TWI_FIFO_STAT_RCVSTAT_EMPTY 0x0000 +#define TWI_FIFO_STAT_RCVSTAT_SHIFT 2 +#define TWI_FIFO_STAT_XMTSTAT_MASK 0x0003 +#define TWI_FIFO_STAT_XMTSTAT_FULL 0x0003 +#define TWI_FIFO_STAT_XMTSTAT_SHIFT 0 + +#define TWI_XMT_DATA8_XMTDATA8_MASK 0x00ff +#define TWI_XMT_DATA8_XMTDATA8_SHIFT 0 + +#define TWI_RCV_DATA8_RCVDATA8_MASK 0x00ff +#define TWI_RCV_DATA8_RCVDATA8_SHIFT 0 + + +#endif /* _twiRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/uartRegs.h b/c/src/lib/libcpu/bfin/include/uartRegs.h new file mode 100644 index 0000000000..d921b17723 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/uartRegs.h @@ -0,0 +1,73 @@ +/* Blackfin UART Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _uartRegs_h_ +#define _uartRegs_h_ + +/* register addresses */ + +#define UART_RBR_OFFSET 0x0000 +#define UART_THR_OFFSET 0x0000 +#define UART_DLL_OFFSET 0x0000 +#define UART_IER_OFFSET 0x0004 +#define UART_DLH_OFFSET 0x0004 +#define UART_IIR_OFFSET 0x0008 +#define UART_LCR_OFFSET 0x000c +#define UART_MCR_OFFSET 0x0010 +#define UART_LSR_OFFSET 0x0014 +#define UART_SCR_OFFSET 0x001c +#define UART_GCTL_OFFSET 0x0024 + + +/* register fields */ + +#define UART_LCR_DLAB 0x80 +#define UART_LCR_SB 0x40 +#define UART_LCR_STP 0x20 +#define UART_LCR_EPS 0x10 +#define UART_LCR_PEN 0x08 +#define UART_LCR_STB 0x04 +#define UART_LCR_WLS_MASK 0x03 +#define UART_LCR_WLS_5 0x00 +#define UART_LCR_WLS_6 0x01 +#define UART_LCR_WLS_7 0x02 +#define UART_LCR_WLS_8 0x03 + +#define UART_MCR_LOOP 0x10 + +#define UART_LSR_TEMT 0x40 +#define UART_LSR_THRE 0x20 +#define UART_LSR_BI 0x10 +#define UART_LSR_FE 0x08 +#define UART_LSR_PE 0x04 +#define UART_LSR_OE 0x02 +#define UART_LSR_DR 0x01 + +#define UART_IER_ELSI 0x04 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ERBFI 0x01 + +#define UART_IIR_STATUS_MASK 0x06 +#define UART_IIR_STATUS_THRE 0x02 +#define UART_IIR_STATUS_RDR 0x04 +#define UART_IIR_STATUS_LS 0x06 +#define UART_IIR_NINT 0x01 + +#define UART_GCTL_FFE 0x20 +#define UART_GCTL_FPE 0x10 +#define UART_GCTL_RPOLC 0x08 +#define UART_GCTL_TPOLC 0x04 +#define UART_GCTL_IREN 0x02 +#define UART_GCTL_UCEN 0x01 + +#endif /* _uartRegs_h_ */ + diff --git a/c/src/lib/libcpu/bfin/include/wdogRegs.h b/c/src/lib/libcpu/bfin/include/wdogRegs.h new file mode 100644 index 0000000000..f56073276c --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/wdogRegs.h @@ -0,0 +1,36 @@ +/* Blackfin Watchdog Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _wdogRegs_h_ +#define _wdogRegs_h_ + +/* register addresses */ + +#define WDOG_CTL (WDOG_BASE_ADDRESS + 0x0000) +#define WDOG_CNT (WDOG_BASE_ADDRESS + 0x0004) +#define WDOG_STAT (WDOG_BASE_ADDRESS + 0x0008) + + +/* register fields */ + +#define WDOG_CTL_WDRO 0x8000 +#define WDOG_CTL_WDEN_MASK 0x0ff0 +#define WDOG_CTL_WDEN_DISABLE 0x0ad0 +#define WDOG_CTL_WDEV_MASK 0x0006 +#define WDOG_CTL_WDEV_RESET 0x0000 +#define WDOG_CTL_WDEV_NMI 0x0002 +#define WDOG_CTL_WDEV_GPI 0x0004 +#define WDOG_CTL_WDEV_DISABLE 0x0006 + + +#endif /* _wdogRegs_h_ */ + |