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author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-09-03 01:30:20 +0200 |
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committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:34 +0200 |
commit | 6f4e903cf0f99b289ce80d5108600ab11abeeee9 (patch) | |
tree | 13be5f6c429e1ff630b6fdbd5b09cb3add6f7bbf /c/src/lib/libcpu/arm/shared/include/arm-cp15.h | |
parent | arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when initializ... (diff) | |
download | rtems-6f4e903cf0f99b289ce80d5108600ab11abeeee9.tar.bz2 |
bsps/arm: use defines for cache type register format field.
The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
Updates #2782
Updates #2783
Diffstat (limited to 'c/src/lib/libcpu/arm/shared/include/arm-cp15.h')
-rw-r--r-- | c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h index a27e50df40..4e4cac430d 100644 --- a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h +++ b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h @@ -211,6 +211,20 @@ extern "C" { /** @} */ /** + * @name CTR, Cache Type Register Defines + * + * The format can be obtained from CP15 by call + * arm_cp15_cache_type_get_format(arm_cp15_get_cache_type()); + * + * @{ + */ + +#define ARM_CP15_CACHE_TYPE_FORMAT_ARMV6 0 +#define ARM_CP15_CACHE_TYPE_FORMAT_ARMV7 4 + +/** @} */ + +/** * @name CCSIDR, Cache Size ID Register Defines * * @{ @@ -685,18 +699,25 @@ arm_cp15_get_cache_type(void) return val; } +/* Extract format version from cache type CTR */ +ARM_CP15_TEXT_SECTION static inline int +arm_cp15_cache_type_get_format(uint32_t ct) +{ + return (ct >> 29) & 0x7U; +} + /* Read size of smallest cache line of all instruction/data caches controlled by the processor */ ARM_CP15_TEXT_SECTION static inline uint32_t arm_cp15_get_min_cache_line_size(void) { uint32_t mcls = 0; uint32_t ct = arm_cp15_get_cache_type(); - uint32_t format = (ct >> 29) & 0x7U; + uint32_t format = arm_cp15_cache_type_get_format(ct); - if (format == 0x4) { + if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) { /* ARMv7 format */ mcls = (1U << (ct & 0xf)) * 4; - } else if (format == 0x0) { + } else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) { /* ARMv6 format */ uint32_t mask = (1U << 12) - 1; uint32_t dcls = (ct >> 12) & mask; @@ -714,12 +735,12 @@ arm_cp15_get_data_cache_line_size(void) { uint32_t mcls = 0; uint32_t ct = arm_cp15_get_cache_type(); - uint32_t format = (ct >> 29) & 0x7U; + uint32_t format = arm_cp15_cache_type_get_format(ct); - if (format == 0x4) { + if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) { /* ARMv7 format */ mcls = (1U << ((ct & 0xf0000) >> 16)) * 4; - } else if (format == 0x0) { + } else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) { /* ARMv6 format */ uint32_t mask = (1U << 12) - 1; mcls = (ct >> 12) & mask; @@ -734,12 +755,12 @@ arm_cp15_get_instruction_cache_line_size(void) { uint32_t mcls = 0; uint32_t ct = arm_cp15_get_cache_type(); - uint32_t format = (ct >> 29) & 0x7U; + uint32_t format = arm_cp15_cache_type_get_format(ct); - if (format == 0x4) { + if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) { /* ARMv7 format */ mcls = (1U << (ct & 0x0000f)) * 4; - } else if (format == 0x0) { + } else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) { /* ARMv6 format */ uint32_t mask = (1U << 12) - 1; mcls = ct & mask;; |