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author | Ric Claus <claus@slac.stanford.edu> | 2013-08-22 14:00:51 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-22 14:20:47 +0200 |
commit | c9b66f5ed312a2bccccd6c3c9f8f4abe5984aeb0 (patch) | |
tree | 810c4b250b9bcb4a5a198af1cbafd62d1a2d0b47 /c/src/lib/libcpu/arm/shared/include/arm-cp15.h | |
parent | arm: Make barrier operations more visible (diff) | |
download | rtems-c9b66f5ed312a2bccccd6c3c9f8f4abe5984aeb0.tar.bz2 |
bsps/arm: Add more CP15 cache functions
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h index 3f032f22c1..0117a5e1cd 100644 --- a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h +++ b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h @@ -577,6 +577,71 @@ static inline uint32_t arm_cp15_get_min_cache_line_size(void) return mcls; } +/* CCSIDR, Cache Size ID Register */ + +static inline uint32_t arm_cp15_get_cache_size_id(void) +{ + ARM_SWITCH_REGISTERS; + uint32_t val; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 1, %[val], c0, c0, 0\n" + ARM_SWITCH_BACK + : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT + ); + + return val; +} + +/* CLIDR, Cache Level ID Register */ + +static inline uint32_t arm_cp15_get_cache_level_id(void) +{ + ARM_SWITCH_REGISTERS; + uint32_t val; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 1, %[val], c0, c0, 1\n" + ARM_SWITCH_BACK + : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT + ); + + return val; +} + +/* CSSELR, Cache Size Selection Register */ + +static inline uint32_t arm_cp15_get_cache_size_selection(void) +{ + ARM_SWITCH_REGISTERS; + uint32_t val; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 2, %[val], c0, c0, 0\n" + ARM_SWITCH_BACK + : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT + ); + + return val; +} + +static inline void arm_cp15_set_cache_size_selection(uint32_t val) +{ + ARM_SWITCH_REGISTERS; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 2, %[val], c0, c0, 0\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [val] "r" (val) + : "memory" + ); +} + static inline void arm_cp15_cache_invalidate(void) { ARM_SWITCH_REGISTERS; |