diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 10:19:28 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 13:08:36 +0200 |
| commit | fbcd7c8fa65eb695e96a62ea1c1ac7a024fa9dfc (patch) | |
| tree | a17e285cf22cd49cd42e8b3ad562febc3987d566 /c/src/lib/libbsp | |
| parent | bsps: Move console drivers to bsps (diff) | |
| download | rtems-fbcd7c8fa65eb695e96a62ea1c1ac7a024fa9dfc.tar.bz2 | |
bsps: Move start files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'c/src/lib/libbsp')
152 files changed, 112 insertions, 17423 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 63449347ad..b8843af4da 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -33,7 +33,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/atsam/Makefile.am b/c/src/lib/libbsp/arm/atsam/Makefile.am index 758b84b343..e5e55bd510 100644 --- a/c/src/lib/libbsp/arm/atsam/Makefile.am +++ b/c/src/lib/libbsp/arm/atsam/Makefile.am @@ -9,7 +9,7 @@ include $(top_srcdir)/../../bsp.am dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am index 9e351295a3..a73f8ff9f8 100644 --- a/c/src/lib/libbsp/arm/beagle/Makefile.am +++ b/c/src/lib/libbsp/arm/beagle/Makefile.am @@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am b/c/src/lib/libbsp/arm/csb336/Makefile.am index 45f9ce342e..16184ed159 100644 --- a/c/src/lib/libbsp/arm/csb336/Makefile.am +++ b/c/src/lib/libbsp/arm/csb336/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/csb336/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/csb336/start/start.S b/c/src/lib/libbsp/arm/csb336/start/start.S deleted file mode 100644 index ce452f52a2..0000000000 --- a/c/src/lib/libbsp/arm/csb336/start/start.S +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Cogent CSB336 startup code - * - * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bsp/linker-symbols.h> - -/* Some standard definitions...*/ -.equ PSR_MODE_USR, 0x10 -.equ PSR_MODE_FIQ, 0x11 -.equ PSR_MODE_IRQ, 0x12 -.equ PSR_MODE_SVC, 0x13 -.equ PSR_MODE_ABT, 0x17 -.equ PSR_MODE_UNDEF, 0x1B -.equ PSR_MODE_SYS, 0x1F - -.equ PSR_I, 0x80 -.equ PSR_F, 0x40 -.equ PSR_T, 0x20 - -.section .bsp_start_text,"ax" - .code 32 -_start_jump_at_origin: - ldr pc, _start_address -_start_address: - .word _start - -.text -.globl _start -_start: - /* - * Since I don't plan to return to the bootloader, - * I don't have to save the registers. - * - * I'll just set the CPSR for SVC mode, interrupts - * off, and ARM instructions. - */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) - msr cpsr, r0 - - /* zero the bss */ - ldr r1, =bsp_section_bss_end - ldr r0, =bsp_section_bss_begin - -_bss_init: - mov r2, #0 - cmp r0, r1 - strlot r2, [r0], #4 - blo _bss_init /* loop while r0 < r1 */ - - - /* --- Initialize stack pointer registers */ - /* Enter IRQ mode and set up the IRQ stack pointer */ - mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_irq_size - ldr sp, =bsp_stack_irq_begin - add sp, sp, r1 - - /* Enter FIQ mode and set up the FIQ stack pointer */ - mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_fiq_size - ldr sp, =bsp_stack_fiq_begin - add sp, sp, r1 - - /* Enter ABT mode and set up the ABT stack pointer */ - mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_abt_size - ldr sp, =bsp_stack_abt_begin - add sp, sp, r1 - - /* Enter UNDEF mode and set up the UNDEF stack pointer */ - mov r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_und_size - ldr sp, =bsp_stack_und_begin - add sp, sp, r1 - - /* Set up the SVC stack pointer last and stay in SVC mode */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_svc_size - ldr sp, =bsp_stack_svc_begin - add sp, sp, r1 - sub sp, sp, #0x64 - - /* - * Initialize the MMU. After we return, the MMU is enabled, - * and memory may be remapped. I hope we don't remap this - * memory away. - */ - ldr r0, =mem_map - bl mmu_init - - /* - * Initialize the exception vectors. This includes the - * exceptions vectors (0x00000000-0x0000001c), and the - * pointers to the exception handlers (0x00000020-0x0000003c). - */ - mov r0, #0 - adr r1, vector_block - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - - /* Now we are prepared to start the BSP's C code */ - mov r0, #0 - bl boot_card - - /* - * Theoretically, we could return to what started us up, - * but we'd have to have saved the registers and stacks. - * Instead, we'll just reset. - */ - bl bsp_reset - - /* We shouldn't get here. If we do, hang */ -_hang: b _hang - - -/* - * This is the exception vector table and the pointers to - * the functions that handle the exceptions. It's a total - * of 16 words (64 bytes) - */ -vector_block: - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - nop - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - .word bsp_reset - -handler_addr_undef: - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - .word _ARMV4_Exception_fiq_default diff --git a/c/src/lib/libbsp/arm/csb337/Makefile.am b/c/src/lib/libbsp/arm/csb337/Makefile.am index 523f4a5523..2bb369baee 100644 --- a/c/src/lib/libbsp/arm/csb337/Makefile.am +++ b/c/src/lib/libbsp/arm/csb337/Makefile.am @@ -14,7 +14,7 @@ noinst_PROGRAMS = if ENABLE_LCD endif -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/csb337/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/csb337/start/start.S b/c/src/lib/libbsp/arm/csb337/start/start.S deleted file mode 100644 index f88cf41d78..0000000000 --- a/c/src/lib/libbsp/arm/csb337/start/start.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Cogent CSB337 startup code - * - * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ - -#include <bsp/linker-symbols.h> - -/* Some standard definitions...*/ -.equ PSR_MODE_USR, 0x10 -.equ PSR_MODE_FIQ, 0x11 -.equ PSR_MODE_IRQ, 0x12 -.equ PSR_MODE_SVC, 0x13 -.equ PSR_MODE_ABT, 0x17 -.equ PSR_MODE_UNDEF, 0x1B -.equ PSR_MODE_SYS, 0x1F - -.equ PSR_I, 0x80 -.equ PSR_F, 0x40 -.equ PSR_T, 0x20 - -.text -.globl _start -_start: - /* - * Since I don't plan to return to the bootloader, - * I don't have to save the registers. - * - * I'll just set the CPSR for SVC mode, interrupts - * off, and ARM instructions. - */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) - msr cpsr, r0 - - /* zero the bss */ - ldr r1, =bsp_section_bss_end - ldr r0, =bsp_section_bss_begin - -_bss_init: - mov r2, #0 - cmp r0, r1 - strlot r2, [r0], #4 - blo _bss_init /* loop while r0 < r1 */ - - - /* --- Initialize stack pointer registers */ - /* Enter IRQ mode and set up the IRQ stack pointer */ - mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_irq_size - ldr sp, =bsp_stack_irq_begin - add sp, sp, r1 - - /* Enter FIQ mode and set up the FIQ stack pointer */ - mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_fiq_size - ldr sp, =bsp_stack_fiq_begin - add sp, sp, r1 - - /* Enter ABT mode and set up the ABT stack pointer */ - mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_abt_size - ldr sp, =bsp_stack_abt_begin - add sp, sp, r1 - - /* Set up the SVC stack pointer last and stay in SVC mode */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_svc_size - ldr sp, =bsp_stack_svc_begin - add sp, sp, r1 - sub sp, sp, #0x64 - - /* - * Initialize the MMU. After we return, the MMU is enabled, - * and memory may be remapped. I hope we don't remap this - * memory away. - */ - ldr r0, =mem_map - bl mmu_init - - /* - * Initialize the exception vectors. This includes the - * exceptions vectors (0x00000000-0x0000001c), and the - * pointers to the exception handlers (0x00000020-0x0000003c). - */ - mov r0, #0 - adr r1, vector_block - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - - /* Now we are prepared to start the BSP's C code */ - mov r0, #0 - bl boot_card - - /* - * Theoretically, we could return to what started us up, - * but we'd have to have saved the registers and stacks. - * Instead, we'll just reset. - */ - bl bsp_reset - - /* We shouldn't get here. If we do, hang */ -_hang: b _hang - - -/* - * This is the exception vector table and the pointers to - * the functions that handle the exceptions. It's a total - * of 16 words (64 bytes) - */ -vector_block: - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - nop - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - .word bsp_reset - -handler_addr_undef: - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - .word _ARMV4_Exception_fiq_default diff --git a/c/src/lib/libbsp/arm/edb7312/Makefile.am b/c/src/lib/libbsp/arm/edb7312/Makefile.am index 6404930f8f..3d6385d5fa 100644 --- a/c/src/lib/libbsp/arm/edb7312/Makefile.am +++ b/c/src/lib/libbsp/arm/edb7312/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/edb7312/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/edb7312/start/start.S b/c/src/lib/libbsp/arm/edb7312/start/start.S deleted file mode 100644 index e03707bfcf..0000000000 --- a/c/src/lib/libbsp/arm/edb7312/start/start.S +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Cirrus EP7312 Startup code - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com> - * - * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ - -#include <bsp/linker-symbols.h> - -/* Some standard definitions...*/ - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_ABORT, 0x17 -.equ Mode_UNDEF, 0x1B -.equ Mode_SYS, 0x1F /*only available on ARM Arch. v4*/ - -.equ I_Bit, 0x80 -.equ F_Bit, 0x40 - -.section ".bsp_start_text", "ax" -.arm - -/******************************************************* - standard exception vectors table - *** Must be located at address 0 -********************************************************/ - -Vector_Init_Block: - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - nop - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - .word _start - -handler_addr_undef: - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - .word _ARMV4_Exception_fiq_default - - .globl _start -_start: - /* store the sp */ - mov r12, sp -/* - * Here is the code to initialize the low-level BSP environment - * (Chip Select, PLL, ....?) - */ - -/* zero the bss */ - LDR r1, =bsp_section_bss_end /* get end of ZI region */ - LDR r0, =bsp_section_bss_begin /* load base address of ZI region */ - -zi_init: - MOV r2, #0 - CMP r0, r1 /* loop whilst r0 < r1 */ - STRLOT r2, [r0], #4 - BLO zi_init - -/* --- Initialise stack pointer registers */ - -/* Enter IRQ mode and set up the IRQ stack pointer */ - MOV r0, #Mode_IRQ | I_Bit | F_Bit /* No interrupts */ - MSR cpsr, r0 - ldr r1, =bsp_stack_irq_size - LDR sp, =bsp_stack_irq_begin - add sp, sp, r1 - sub sp, sp, #0x64 - -/* Enter FIQ mode and set up the FIQ stack pointer */ - MOV r0, #Mode_FIQ | I_Bit | F_Bit /* No interrupts */ - MSR cpsr, r0 - ldr r1, =bsp_stack_fiq_size - LDR sp, =bsp_stack_fiq_begin - add sp, sp, r1 - sub sp, sp, #0x64 - -/* Enter ABT mode and set up the ABT stack pointer */ - MOV r0, #Mode_ABT | I_Bit | F_Bit /* No interrupts */ - MSR cpsr, r0 - ldr r1, =bsp_stack_abt_size - LDR sp, =bsp_stack_abt_begin - add sp, sp, r1 - sub sp, sp, #0x64 - -/* Set up the SVC stack pointer last and stay in SVC mode */ - MOV r0, #Mode_SVC | I_Bit | F_Bit /* No interrupts */ - MSR cpsr, r0 - ldr r1, =bsp_stack_svc_size - LDR sp, =bsp_stack_svc_begin - add sp, sp, r1 - sub sp, sp, #0x64 - - /* save the original registers */ - stmdb sp!, {r4-r12, lr} - -/* --- Now we enter the C code */ - - mov r0, #0 - bl boot_card - - ldmia sp!, {r4-r12, lr} - mov sp, r12 - mov pc, lr diff --git a/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am b/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am index 68521ca1c2..ab88e3c405 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am +++ b/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/gumstix/Makefile.am b/c/src/lib/libbsp/arm/gumstix/Makefile.am index d262811e47..ffb456b833 100644 --- a/c/src/lib/libbsp/arm/gumstix/Makefile.am +++ b/c/src/lib/libbsp/arm/gumstix/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/gumstix/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/gumstix/start/start.S b/c/src/lib/libbsp/arm/gumstix/start/start.S deleted file mode 100644 index dccc99993e..0000000000 --- a/c/src/lib/libbsp/arm/gumstix/start/start.S +++ /dev/null @@ -1,156 +0,0 @@ -/* - * By Yang Xi <hiyangxi@gmail.com>. - * Based upon CSB337 - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bsp/linker-symbols.h> - -/* Some standard definitions...*/ -.equ PSR_MODE_USR, 0x10 -.equ PSR_MODE_FIQ, 0x11 -.equ PSR_MODE_IRQ, 0x12 -.equ PSR_MODE_SVC, 0x13 -.equ PSR_MODE_ABT, 0x17 -.equ PSR_MODE_UNDEF, 0x1B -.equ PSR_MODE_SYS, 0x1F - -.equ PSR_I, 0x80 -.equ PSR_F, 0x40 -.equ PSR_T, 0x20 - -.text -.globl _start -_start: - /* - * Since I don't plan to return to the bootloader, - * I don't have to save the registers. - * - * I'll just set the CPSR for SVC mode, interrupts - * off, and ARM instructions. - */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) - msr cpsr, r0 - - - /* zero the bss */ - ldr r1, =bsp_section_bss_end - ldr r0, =bsp_section_bss_begin - -_bss_init: - mov r2, #0 - cmp r0, r1 - strlot r2, [r0], #4 - blo _bss_init /* loop while r0 < r1 */ - - /* --- Initialize stack pointer registers */ - /* Enter IRQ mode and set up the IRQ stack pointer */ - mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_irq_size - ldr sp, =bsp_stack_irq_begin - add sp, sp, r1 - - /* Enter FIQ mode and set up the FIQ stack pointer */ - mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_fiq_size - ldr sp, =bsp_stack_fiq_begin - add sp, sp, r1 - - /* Enter ABT mode and set up the ABT stack pointer */ - mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_abt_size - ldr sp, =bsp_stack_abt_begin - add sp, sp, r1 - - /* Set up the SVC stack pointer last and stay in SVC mode */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_und_size - ldr sp, =bsp_stack_und_begin - add sp, sp, r1 - sub sp, sp, #0x64 - - /* - * Initialize the MMU. After we return, the MMU is enabled, - * and memory may be remapped. I hope we don't remap this - * memory away. - */ - - ldr r0, =mem_map - bl mmu_init - - - - /* - * Initialize the exception vectors. This includes the - * exceptions vectors (0x00000000-0x0000001c), and the - * pointers to the exception handlers (0x00000020-0x0000003c). - */ - mov r0, #0 - adr r1, vector_block - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - - - - /* Now we are prepared to start the BSP's C code */ - mov r0, #0 - bl boot_card - - /* - * Theoretically, we could return to what started us up, - * but we'd have to have saved the registers and stacks. - * Instead, we'll just reset. - */ - bl bsp_reset - - /* We shouldn't get here. If we do, hang */ -_hang: b _hang - - -/* - * This is the exception vector table and the pointers to - * the functions that handle the exceptions. It's a total - * of 16 words (64 bytes) - */ -vector_block: - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - nop - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - .word bsp_reset - -handler_addr_undef: - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - .word _ARMV4_Exception_fiq_default diff --git a/c/src/lib/libbsp/arm/imx/Makefile.am b/c/src/lib/libbsp/arm/imx/Makefile.am index 2d62ed445d..0dc1b30f96 100644 --- a/c/src/lib/libbsp/arm/imx/Makefile.am +++ b/c/src/lib/libbsp/arm/imx/Makefile.am @@ -13,7 +13,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am b/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am index 52bbb89ce3..dc4b7bb30c 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lm3s69xx/Makefile.am @@ -9,7 +9,7 @@ include $(top_srcdir)/../../bsp.am dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/lpc176x/Makefile.am b/c/src/lib/libbsp/arm/lpc176x/Makefile.am index ba2475febb..1632cb879e 100644 --- a/c/src/lib/libbsp/arm/lpc176x/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc176x/Makefile.am @@ -22,7 +22,7 @@ dist_project_lib_DATA = startup/bsp_specs # ------ Data # ---------------------------- -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am index a597be7e05..4ad4ac30fc 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am @@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am index d07607060d..d0bfb3c018 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am @@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am index 106c0b43f9..d0c168867e 100644 --- a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am +++ b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am @@ -22,7 +22,7 @@ noinst_HEADERS = ../../../../../../bsps/arm/raspberrypi/console/font_data.h # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am index bc1e0437cb..829fa617dc 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am @@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/rtl22xx/Makefile.am b/c/src/lib/libbsp/arm/rtl22xx/Makefile.am index e64bbeee9f..d4ac6664e9 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/Makefile.am +++ b/c/src/lib/libbsp/arm/rtl22xx/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/rtl22xx/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/rtl22xx/start/start.S b/c/src/lib/libbsp/arm/rtl22xx/start/start.S deleted file mode 100644 index c038198aff..0000000000 --- a/c/src/lib/libbsp/arm/rtl22xx/start/start.S +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Philips LPC22XX/LPC21xx Startup code - * - * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com> - * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com> - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ - -#include <bsp/linker-symbols.h> - -/* Some standard definitions...*/ -.equ PSR_MODE_USR, 0x10 -.equ PSR_MODE_FIQ, 0x11 -.equ PSR_MODE_IRQ, 0x12 -.equ PSR_MODE_SVC, 0x13 -.equ PSR_MODE_ABT, 0x17 -.equ PSR_MODE_UNDEF, 0x1B -.equ PSR_MODE_SYS, 0x1F - -.equ PSR_I, 0x80 -.equ PSR_F, 0x40 -.equ PSR_T, 0x20 - -.text -.code 32 -.globl _start -_start: - /* - * Since I don't plan to return to the bootloader, - * I don't have to save the registers. - * - * I'll just set the CPSR for SVC mode, interrupts - * off, and ARM instructions. - */ - - /* --- Initialize stack pointer registers */ - /* Enter IRQ mode and set up the IRQ stack pointer */ - mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ - bic r0, r0, #PSR_T - msr cpsr, r0 - ldr r1, =bsp_stack_irq_size - ldr sp, =bsp_stack_irq_begin - add sp, sp, r1 - - /* Enter FIQ mode and set up the FIQ stack pointer */ - mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ - bic r0, r0, #PSR_T - msr cpsr, r0 - ldr r1, =bsp_stack_fiq_size - ldr sp, =bsp_stack_fiq_begin - add sp, sp, r1 - - /* Enter ABT mode and set up the ABT stack pointer */ - mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ - bic r0, r0, #PSR_T - msr cpsr, r0 - bic r0, r0, #PSR_T - ldr r1, =bsp_stack_abt_size - ldr sp, =bsp_stack_abt_begin - add sp, sp, r1 - - /* Set up the SVC stack pointer last and stay in SVC mode */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ - bic r0, r0, #PSR_T - msr cpsr, r0 - ldr r1, =bsp_stack_svc_size - ldr sp, =bsp_stack_svc_begin - add sp, sp, r1 - sub sp, sp, #0x64 - - /* - * Initialize the exception vectors. This includes the - * exceptions vectors (0x00000000-0x0000001c), and the - * pointers to the exception handlers (0x00000020-0x0000003c). - */ - mov r0, #0 - adr r1, vector_block - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - - - /* zero the bss */ - ldr r1, =bsp_section_bss_end - ldr r0, =bsp_section_bss_begin - -_bss_init: - mov r2, #0 - cmp r0, r1 - strlot r2, [r0], #4 - blo _bss_init /* loop while r0 < r1 */ - - - /* Now we are prepared to start the BSP's C code */ - mov r0, #0 -#ifdef __thumb__ - ldr r3, =boot_card - bx r3 -#else - bl boot_card - - - /* - * Theoretically, we could return to what started us up, - * but we'd have to have saved the registers and stacks. - * Instead, we'll just reset. - */ - bl bsp_reset -#endif - .code 32 - - /* We shouldn't get here. If we do, hang */ -_hang: b _hang - - -/******************************************************* - standard exception vectors table - *** Must be located at address 0 -********************************************************/ - -vector_block: - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - nop - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - .word _start - -handler_addr_undef: - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - .word _ARMV4_Exception_fiq_default diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S deleted file mode 100755 index aa0f3782c9..0000000000 --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ /dev/null @@ -1,462 +0,0 @@ -/** - * @file - * - * @brief Boot and system start code. - */ - -/* - * Copyright (c) 2008, 2016 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include <rtems/system.h> -#include <rtems/score/percpu.h> - -#include <bspopts.h> -#include <bsp/irq.h> -#include <bsp/linker-symbols.h> - - /* External symbols */ - .extern bsp_reset - .extern boot_card - .extern bsp_start_hook_0 - .extern bsp_start_hook_1 - .extern bsp_stack_irq_end - .extern bsp_stack_fiq_end - .extern bsp_stack_abt_end - .extern bsp_stack_und_end - .extern bsp_stack_svc_end -#ifdef RTEMS_SMP - .extern bsp_stack_all_size -#endif - .extern _ARMV4_Exception_undef_default - .extern _ARMV4_Exception_swi_default - .extern _ARMV4_Exception_data_abort_default - .extern _ARMV4_Exception_pref_abort_default - .extern _ARMV4_Exception_reserved_default - .extern _ARMV4_Exception_interrupt - .extern _ARMV4_Exception_fiq_default - .extern _ARMV7M_Exception_default - -#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION - .extern bsp_start_init_registers_core - .extern bsp_start_init_registers_banked_fiq - .extern bsp_start_init_registers_vfp -#endif - -#ifdef BSP_START_IN_HYP_SUPPORT - .extern bsp_start_arm_drop_hyp_mode - .globl bsp_start_hyp_vector_table_begin -#endif - - /* Global symbols */ - .globl _start - .globl bsp_start_vector_table_begin - .globl bsp_start_vector_table_end - .globl bsp_start_vector_table_size - .globl bsp_vector_table_size - .globl bsp_start_hook_0_done - - .section ".bsp_start_text", "ax" - -#if defined(ARM_MULTILIB_ARCH_V4) - - .arm - -/* - * This is the exception vector table and the pointers to the default - * exceptions handlers. - */ - -bsp_start_vector_table_begin: - - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - - /* Program signature checked by boot loader */ - .word 0xb8a06f58 - - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - -#ifdef BSP_START_RESET_VECTOR - .word BSP_START_RESET_VECTOR -#else - .word _start -#endif - -handler_addr_undef: - - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - - .word _ARMV4_Exception_fiq_default - -bsp_start_vector_table_end: - -#ifdef BSP_START_IN_HYP_SUPPORT -bsp_start_hyp_vector_table_begin: - ldr pc, handler_addr_hyp_reset - ldr pc, handler_addr_hyp_undef - ldr pc, handler_addr_hyp_swi - ldr pc, handler_addr_hyp_prefetch - ldr pc, handler_addr_hyp_abort - ldr pc, handler_addr_hyp_hyp - ldr pc, handler_addr_hyp_irq - ldr pc, handler_addr_hyp_fiq - -handler_addr_hyp_reset: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_undef: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_swi: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_prefetch: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_abort: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_hyp: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_irq: - .word _ARMV4_Exception_reserved_default - -handler_addr_hyp_fiq: - .word _ARMV4_Exception_reserved_default - -bsp_start_hyp_vector_table_end: -#endif - -/* Start entry */ - -_start: - - /* - * We do not save the context since we do not return to the boot - * loader but preserve r1 and r2 to allow access to bootloader parameters - */ -#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION - mov r5, r1 /* machine type number or ~0 for DT boot */ - mov r6, r2 /* physical address of ATAGs or DTB */ -#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */ - bl bsp_start_init_registers_core -#endif - -#ifdef RTEMS_SMP - /* Read MPIDR and get current processor index */ - mrc p15, 0, r7, c0, c0, 5 - and r7, #0xff -#endif - -#ifdef BSP_START_COPY_FDT_FROM_U_BOOT -#ifdef RTEMS_SMP - cmp r7, #0 - bne 1f -#endif - mov r0, r6 - bl bsp_fdt_copy -1: -#endif - -#ifdef RTEMS_SMP - /* - * Get current per-CPU control and store it in PL1 only Thread ID - * Register (TPIDRPRW). - */ - ldr r1, =_Per_CPU_Information - add r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2 - mcr p15, 0, r1, c13, c0, 4 - - /* Calculate stack offset */ - ldr r1, =bsp_stack_all_size - mul r1, r7 -#endif - - mrs r4, cpsr /* save original procesor status value */ -#ifdef BSP_START_IN_HYP_SUPPORT - orr r0, r4, #(ARM_PSR_I | ARM_PSR_F) - msr cpsr, r4 - - and r0, r4, #ARM_PSR_M_MASK - cmp r0, #ARM_PSR_M_HYP - bne bsp_start_skip_hyp_svc_switch - - /* Boot loader stats kernel in HYP mode, switch to SVC necessary */ - ldr sp, =bsp_stack_hyp_end -#ifdef RTEMS_SMP - add sp, r1 -#endif - bl bsp_start_arm_drop_hyp_mode - -bsp_start_skip_hyp_svc_switch: -#endif - /* - * Set SVC mode, disable interrupts and enable ARM instructions. - */ - mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) - msr cpsr, r0 - - /* Initialize stack pointer registers for the various modes */ - - /* Enter IRQ mode and set up the IRQ stack pointer */ - mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) - msr cpsr, r0 - ldr sp, =bsp_stack_irq_end -#ifdef RTEMS_SMP - add sp, r1 -#endif - - /* Enter FIQ mode and set up the FIQ stack pointer */ - mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) - msr cpsr, r0 - ldr sp, =bsp_stack_fiq_end -#ifdef RTEMS_SMP - add sp, r1 -#endif - -#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION - bl bsp_start_init_registers_banked_fiq -#endif - - /* Enter ABT mode and set up the ABT stack pointer */ - mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) - msr cpsr, r0 - ldr sp, =bsp_stack_abt_end -#ifdef RTEMS_SMP - add sp, r1 -#endif - - /* Enter UND mode and set up the UND stack pointer */ - mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) - msr cpsr, r0 - ldr sp, =bsp_stack_und_end -#ifdef RTEMS_SMP - add sp, r1 -#endif - - /* Enter SVC mode and set up the SVC stack pointer */ - mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) - msr cpsr, r0 - ldr sp, =bsp_stack_svc_end -#ifdef RTEMS_SMP - add sp, r1 -#endif - - /* Stay in SVC mode */ - -#ifdef ARM_MULTILIB_VFP -#ifdef ARM_MULTILIB_HAS_CPACR - /* Read CPACR */ - mrc p15, 0, r0, c1, c0, 2 - - /* Enable CP10 and CP11 */ - orr r0, r0, #(1 << 20) - orr r0, r0, #(1 << 22) - - /* - * Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16. - */ - bic r0, r0, #(3 << 30) - - /* Write CPACR */ - mcr p15, 0, r0, c1, c0, 2 - isb -#endif - - /* Enable FPU */ - mov r0, #(1 << 30) - vmsr FPEXC, r0 - -#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION - bl bsp_start_init_registers_vfp -#endif - -#endif /* ARM_MULTILIB_VFP */ - - /* - * Branch to start hook 0. - * - * The previous code and parts of the start hook 0 may run with an - * address offset. This implies that only branches relative to the - * program counter are allowed. After the start hook 0 it is assumed - * that the code can run at its intended position. Thus the link - * register will be loaded with the absolute address. In THUMB mode - * the start hook 0 must be within a 2kByte range due to the branch - * instruction limitation. - */ - - ldr lr, =bsp_start_hook_0_done -#ifdef __thumb__ - orr lr, #1 -#endif - - SWITCH_FROM_ARM_TO_THUMB r0 - - mov r0, r4 /* original cpsr value */ - mov r1, r5 /* machine type number or ~0 for DT boot */ - mov r2, r6 /* physical address of ATAGs or DTB */ - - b bsp_start_hook_0 - -bsp_start_hook_0_done: - - SWITCH_FROM_THUMB_TO_ARM - - /* - * Initialize the exception vectors. This includes the exceptions - * vectors and the pointers to the default exception handlers. - */ - - stmdb sp!, {r4, r5, r6} - - ldr r0, =bsp_vector_table_begin - adr r1, bsp_start_vector_table_begin - cmp r0, r1 - beq bsp_vector_table_copy_done - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - -bsp_vector_table_copy_done: - - ldmia sp!, {r0, r1, r2} - - SWITCH_FROM_ARM_TO_THUMB r3 - - /* Branch to start hook 1 */ - bl bsp_start_hook_1 - - /* Branch to boot card */ - mov r0, #0 - bl boot_card - -twiddle: - - /* Branch to reset function */ - bl bsp_reset - - b twiddle - -#elif defined(ARM_MULTILIB_ARCH_V7M) - -#include <rtems/score/armv7m.h> - - .syntax unified - - .extern bsp_stack_main_end - - .thumb - -bsp_start_vector_table_begin: - - .word bsp_stack_main_end - .word _start /* Reset */ - .word _ARMV7M_Exception_default /* NMI */ - .word _ARMV7M_Exception_default /* Hard Fault */ - .word _ARMV7M_Exception_default /* MPU Fault */ - .word _ARMV7M_Exception_default /* Bus Fault */ - .word _ARMV7M_Exception_default /* Usage Fault */ - .word _ARMV7M_Exception_default /* Reserved */ - .word _ARMV7M_Exception_default /* Reserved */ - .word _ARMV7M_Exception_default /* Reserved */ - .word _ARMV7M_Exception_default /* Reserved */ - .word _ARMV7M_Exception_default /* SVC */ - .word _ARMV7M_Exception_default /* Debug Monitor */ - .word _ARMV7M_Exception_default /* Reserved */ - .word _ARMV7M_Exception_default /* PendSV */ - .word _ARMV7M_Exception_default /* SysTick */ - .rept BSP_INTERRUPT_VECTOR_MAX + 1 - .word _ARMV7M_Exception_default /* IRQ */ - .endr - -bsp_start_vector_table_end: - - .thumb_func - -_start: - -#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION - bl bsp_start_init_registers_core -#endif - -#ifdef ARM_MULTILIB_VFP -#ifdef ARM_MULTILIB_HAS_CPACR - /* - * Enable CP10 and CP11 coprocessors for privileged and user mode in - * CPACR (bits 20-23). Ensure that write to register completes. - */ - ldr r0, =ARMV7M_CPACR - ldr r1, [r0] - orr r1, r1, #(0xf << 20) - str r1, [r0] - dsb - isb -#endif - -#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION - bl bsp_start_init_registers_vfp -#endif - -#endif /* ARM_MULTILIB_VFP */ - - ldr sp, =bsp_stack_main_end - ldr lr, =bsp_start_hook_0_done + 1 - b bsp_start_hook_0 - -bsp_start_hook_0_done: - - bl bsp_start_hook_1 - movs r0, #0 - bl boot_card - -twiddle: - - bl bsp_reset - b twiddle - -#endif /* defined(ARM_MULTILIB_ARCH_V7M) */ - - .set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin - .set bsp_vector_table_size, bsp_start_vector_table_size diff --git a/c/src/lib/libbsp/arm/smdk2410/Makefile.am b/c/src/lib/libbsp/arm/smdk2410/Makefile.am index 748cde9c94..7fa8df5a80 100644 --- a/c/src/lib/libbsp/arm/smdk2410/Makefile.am +++ b/c/src/lib/libbsp/arm/smdk2410/Makefile.am @@ -6,7 +6,7 @@ include $(top_srcdir)/../../bsp.am dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/smdk2410/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/smdk2410/start/start.S b/c/src/lib/libbsp/arm/smdk2410/start/start.S deleted file mode 100644 index 95d781cb89..0000000000 --- a/c/src/lib/libbsp/arm/smdk2410/start/start.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * SMDK2410 startup code - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bsp/linker-symbols.h> - -/* Some standard definitions...*/ -.equ PSR_MODE_USR, 0x10 -.equ PSR_MODE_FIQ, 0x11 -.equ PSR_MODE_IRQ, 0x12 -.equ PSR_MODE_SVC, 0x13 -.equ PSR_MODE_ABT, 0x17 -.equ PSR_MODE_UNDEF, 0x1B -.equ PSR_MODE_SYS, 0x1F - -.equ PSR_I, 0x80 -.equ PSR_F, 0x40 -.equ PSR_T, 0x20 - -.text -.globl _start -_start: - b _start2 - -@--------------------------------------------------------------------------------- -@ AXF addresses -@--------------------------------------------------------------------------------- - .word bsp_section_text_begin - .word bsp_section_rodata_end - .word bsp_section_data_begin - .word bsp_section_bss_end - .word bsp_section_bss_begin - .word bsp_section_bss_end - -@--------------------------------------------------------------------------------- -@ GamePark magic sequence -@--------------------------------------------------------------------------------- - .word 0x44450011 - .word 0x44450011 - .word 0x01234567 - .word 0x12345678 - .word 0x23456789 - .word 0x34567890 - .word 0x45678901 - .word 0x56789012 - .word 0x23456789 - .word 0x34567890 - .word 0x45678901 - .word 0x56789012 - .word 0x23456789 - .word 0x34567890 - .word 0x45678901 - .word 0x56789012 - -@--------------------------------------------------------------------------------- -_start2: -@--------------------------------------------------------------------------------- - - /* - * Since I don't plan to return to the bootloader, - * I don't have to save the registers. - * - * I'll just set the CPSR for SVC mode, interrupts - * off, and ARM instructions. - */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) - msr cpsr, r0 - - /* --- Initialize stack pointer registers */ - /* Enter IRQ mode and set up the IRQ stack pointer */ - mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_irq_size - ldr sp, =bsp_stack_irq_begin - add sp, sp, r1 - - /* Enter FIQ mode and set up the FIQ stack pointer */ - mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_fiq_size - ldr sp, =bsp_stack_fiq_begin - add sp, sp, r1 - - /* Enter ABT mode and set up the ABT stack pointer */ - mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_abt_size - ldr sp, =bsp_stack_abt_begin - add sp, sp, r1 - - /* Set up the SVC stack pointer last and stay in SVC mode */ - mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ - msr cpsr, r0 - ldr r1, =bsp_stack_svc_size - ldr sp, =bsp_stack_svc_begin - add sp, sp, r1 - sub sp, sp, #0x64 - - - /* disable mmu, I and D caches*/ - nop - nop - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x01 - bic r0, r0, #0x04 - bic r0, r0, #0x01000 - mcr p15, 0, r0, c1, c0, 0 - nop - nop - - /* clean data cache */ - mov r1,#0x00 -Loop1: - mov r2,#0x00 -Loop2: - mov r3, r2, lsl#26 - orr r3, r3, r1, lsl#5 - mcr p15, 0, r3, c7, c14, 2 - add r2, r2, #0x01 - cmp r2, #64 - bne Loop2 - add r1, r1, #0x01 - cmp r1, #8 - bne Loop1 - - - /* - * Initialize the MMU. After we return, the MMU is enabled, - * and memory may be remapped. I hope we don't remap this - * memory away. - */ - ldr r0, =mem_map - bl mmu_init - - /* - * Initialize the exception vectors. This includes the - * exceptions vectors (0x00000000-0x0000001c), and the - * pointers to the exception handlers (0x00000020-0x0000003c). - */ - mov r0, #0 - adr r1, vector_block - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - ldmia r1!, {r2-r9} - stmia r0!, {r2-r9} - - /* Now we are prepared to start the BSP's C code */ - mov r0, #0 - bl boot_card - - /* - * Theoretically, we could return to what started us up, - * but we'd have to have saved the registers and stacks. - * Instead, we'll just reset. - */ - bl bsp_reset - - /* We shouldn't get here. If we do, hang */ -_hang: b _hang - - -/* - * This is the exception vector table and the pointers to - * the functions that handle the exceptions. It's a total - * of 16 words (64 bytes) - */ -vector_block: - ldr pc, handler_addr_reset - ldr pc, handler_addr_undef - ldr pc, handler_addr_swi - ldr pc, handler_addr_prefetch - ldr pc, handler_addr_abort - nop - ldr pc, handler_addr_irq - ldr pc, handler_addr_fiq - -handler_addr_reset: - .word bsp_reset - -handler_addr_undef: - .word _ARMV4_Exception_undef_default - -handler_addr_swi: - .word _ARMV4_Exception_swi_default - -handler_addr_prefetch: - .word _ARMV4_Exception_pref_abort_default - -handler_addr_abort: - .word _ARMV4_Exception_data_abort_default - -handler_addr_reserved: - .word _ARMV4_Exception_reserved_default - -handler_addr_irq: - .word _ARMV4_Exception_interrupt - -handler_addr_fiq: - .word _ARMV4_Exception_fiq_default diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am index 760b387a18..4e5a2d5274 100644 --- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am +++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am @@ -9,7 +9,7 @@ include $(top_srcdir)/../../bsp.am dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am index 106d6c1d9e..1a65fc1bb7 100644 --- a/c/src/lib/libbsp/arm/tms570/Makefile.am +++ b/c/src/lib/libbsp/arm/tms570/Makefile.am @@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs # ------ Data # ---------------------------- -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 0b468fd12e..746c605f68 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am b/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am index b47be73d17..1e5e9f18ba 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am +++ b/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/bfin/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am b/c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am index e8c3e183f2..df7e2b939d 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am +++ b/c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/bfin/bf537Stamp/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/start/start.S b/c/src/lib/libbsp/bfin/bf537Stamp/start/start.S deleted file mode 100644 index a835a48764..0000000000 --- a/c/src/lib/libbsp/bfin/bf537Stamp/start/start.S +++ /dev/null @@ -1,115 +0,0 @@ -#include <libcpu/bf537.h> -#include <libcpu/sicRegs.h> -#include <libcpu/cecRegs.h> -#include <libcpu/dmaRegs.h> -#include <libcpu/coreTimerRegs.h> - -#ifndef LO -#define LO(con32) ((con32) & 0xFFFF) -#endif -#ifndef HI -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#endif - - .section .start - .align 4 - - .global __start -__start: - cli r0; - - /* setup an initial stack */ - sp.h = 0xFFB0; - sp.l = 0x0F00; - - /* disable timer interrupts */ - p0.h = HI(TCNTL); - p0.l = LO(TCNTL); - r0 = 0; - [p0] = r0; - - /* disable all interrupts routed through sic */ - p0.h = HI(SIC_IMASK); - p0.l = LO(SIC_IMASK); - [p0] = r0; - - /* clear any pending interrupts */ - p0.h = HI(CEC_ILAT); - p0.l = LO(CEC_ILAT); - r0 = 0xffff (z); - [p0] = r0; - - /* disable all dma channels */ - p0.h = HI(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET); - p0.l = LO(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET); - p1 = DMA_PITCH; - p2 = DMA_CHANNELS; - r0 = ~DMA_CONFIG_DMAEN; - lsetup(loop1,loop2) lc0 = p2; -loop1: r1 = w[p0]; - r1 = r0 & r1; -loop2: w[p0 ++ p1] = r1.l; - - /* this is so we can stay in supervisor mode and still be able to - accept interrupts later. */ - p0.h = start; - p0.l = start; - p1.h = HI(CEC_EVT15); - p1.l = LO(CEC_EVT15); - - [p1] = p0; - - r0 = 0x8000 (z); - sti r0; - - raise 15; - - p0.h = wait; - p0.l = wait; - - reti = p0; - rti; - - /* wait for event 15 */ -wait: - jump wait; - -start: - [--sp] = reti; /* allow us to process interrupts later */ - - /* mask interrupts for now */ - cli r0; - - p0.h = _bss_start; - p0.l = _bss_start; - p1.h = _end; - p1.l = _end; - r0 = p0; - r1 = p1; - r1 = r1 - r0; - p1 = r1; - r0 = 0; - - /* Set _bss_start until _end to zero */ - lsetup(loop3,loop4) lc0 = p1; -loop3: b[p0] = r0; -loop4: p0 +=1; - - l0 = 0; - l1 = 0; - l2 = 0; - l3 = 0; - sp += -12; - /* r0 == const char *cmdline (currently null) */ - p0.h = _boot_card; - p0.l = _boot_card; - call (p0); - sp += 12; - - .global _bsp_reset -_bsp_reset: - HLT - p0.h = _exit; - p0.l = _exit; - jump (p0); - diff --git a/c/src/lib/libbsp/bfin/eZKit533/Makefile.am b/c/src/lib/libbsp/bfin/eZKit533/Makefile.am index d5a0685958..46541c8be4 100644 --- a/c/src/lib/libbsp/bfin/eZKit533/Makefile.am +++ b/c/src/lib/libbsp/bfin/eZKit533/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/bfin/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/bfin/shared/start/start.S b/c/src/lib/libbsp/bfin/shared/start/start.S deleted file mode 100644 index 3440f5ccc9..0000000000 --- a/c/src/lib/libbsp/bfin/shared/start/start.S +++ /dev/null @@ -1,95 +0,0 @@ - -#include <rtems/bfin/bfin.h> - -#include <bsp.h> -#include <bspopts.h> - -#ifndef LO -#define LO(con32) ((con32) & 0xFFFF) -#endif -#ifndef HI -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#endif - -#if (BFIN_ON_SKYEYE) - .section .init -#else - .section .l1code -#endif - .align 4 - - .global __start -__start: - - /* Start by setting up a stack */ - sp.h = 0xFFB0; - sp.l = 0x0F00; - - /* Maybe we should zero the memory in the .bss section. */ - - /* This changes to the supervisor mode */ - p0.l = START; - p0.h = START; - p1.l = LO(EVT15); - p1.h = HI(EVT15); - - [P1] = P0; - - P0.h = HI(IMASK); - P0.l = LO(IMASK); - R0 = [P0]; - /* R1.l = EVT_IVG15 & 0xFFFF; */ - R1.l = 0x8000; - - R0 = R0 | R1; - - [P0] = R0; - - RAISE 15; - - P0.l = WAIT; - P0.h = WAIT; - - RETI = P0; - RTI; - - /* endless loop to wait */ - WAIT: - jump WAIT; - - START: - [--SP] = RETI; - - p0.h = _bss_start; - p0.l = _bss_start; - p1.h = _end; - p1.l = _end; - r0 = p0; - r1 = p1; - r1 = r1 - r0; - p1 = r1; - r0 = 0; - - /* Set _bss_start until _end to zero */ - lsetup(loop1,loop2) LC0 = p1; - loop1: b[p0] = r0; - loop2: p0 +=1; - - /* call boot_card( 0, 0 ) */ - r0 = 0; - r1 = 0; - p0.l = _boot_card; - p0.h = _boot_card; - - call (p0); - - HLT - p0.l = _exit; - p0.h = _exit; - P3 = P4; - jump (p0) /* Should not return. */ - -.global _bfin_null_isr -_bfin_null_isr: - rti; - diff --git a/c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am b/c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am index 4b001ac26c..0e4a1ba0bd 100644 --- a/c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am +++ b/c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am @@ -18,7 +18,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/epiphany/epiphany_sim/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/epiphany/epiphany_sim/start/start.S b/c/src/lib/libbsp/epiphany/epiphany_sim/start/start.S deleted file mode 100644 index 7f828ae151..0000000000 --- a/c/src/lib/libbsp/epiphany/epiphany_sim/start/start.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include <bsp/linker-symbols.h> -#include <rtems/asm.h> - -EXTERN(bsp_section_bss_begin) -EXTERN(bsp_section_bss_end) -EXTERN(_ISR_Handler) -EXTERN(bsp_start_vector_table_end) -EXTERN(bsp_start_vector_table_size) -EXTERN(bsp_vector_table_size) -EXTERN(bsp_section_stack_begin) - -PUBLIC(_EPIPHANY_Exception_default) -PUBLIC(bsp_start_vector_table_begin) -PUBLIC(_start) - -.section .vector, "wax" -TYPE_FUNC(_start) -SYM(_start): - .balign 4 ; - b .normal_start - - .balign 4 ; 0x4 - b .sw_exception - - .balign 4 ; 0x8 - b .normal_start - - .balign 4 ; 0xc - b .clock_isr - - .balign 4 ; 0x10 - b .timer1_isr - - .balign 4 ; 0x14 - b _EPIPHANY_Exception_default - - .balign 4 ; 0x18 - b _EPIPHANY_Exception_default - - .balign 4 ; 0x1c - b _EPIPHANY_Exception_default - - .balign 4 ; 0x20 - b _EPIPHANY_Exception_default - - .balign 4 ; 0x24 - b _EPIPHANY_Exception_default - -bsp_start_vector_table_begin: - .word .normal_start /* Reset */ - .word _EPIPHANY_Exception_default /* SW exception */ - .word _EPIPHANY_Exception_default /* Data Page Fault */ - .word _EPIPHANY_Exception_default /* Timer 0 */ - .word _EPIPHANY_Exception_default /* Timer 1 */ - .word _EPIPHANY_Exception_default /* Message int */ - .word _EPIPHANY_Exception_default /* DMA0 int */ - .word _EPIPHANY_Exception_default /* DMA1 int */ - .word _EPIPHANY_Exception_default /* WAND */ - .word _EPIPHANY_Exception_default /* User interrupt */ - -_bsp_start_vector_table_end: - -.size _start, .-_start - -.section .start,"ax" -.align 4 -.type _external_start, %function -.normal_start: - /* Initialize the stack and frame pointers */ - mov sp, %low(bsp_section_stack_begin) - movt sp, %high(bsp_section_stack_begin) - mov fp, sp - -cpu0: - /* Zero .bss section */ - mov r0, %low(bsp_section_bss_begin) - movt r0, %high(bsp_section_bss_begin) - mov r1, sp - mov r2,#0 - mov r3,#0 - -_bss_clear_loop: - strd r2, [r0], +#1 - sub r5, r1, r0 - bne _bss_clear_loop - - /* Clear the reset interrupt flag */ - mov r0, %low(_jump_to_c) - movt r0, %high(_jump_to_c) - movts iret, r0 - rti - -_jump_to_c: - /* Jump to bootcard */ - mov r3, %low(boot_card) - movt r3, %high(boot_card) - jalr r3 - - /* Should never reach here */ - idle - -.size .normal_start, .-.normal_start - -.balign 4 -.type .sw_exception, %function -.sw_exception: - idle - -.balign 4 -.type .clock_isr, %function -.clock_isr: - /* - * r62 and r63 are saved here, and restored from _ISR_Handler, they - * and hold vector number and _ISR_Handler address repsectively. - */ - add sp, sp, #-8 - str r62, [sp, #0] - str r63, [sp, #4] - mov r62, 3 - mov r63, %low(_ISR_Handler) - movt r63, %high(_ISR_Handler) - jr r6 - -.balign 4 -.type .timer1_isr, %function -.timer1_isr: - /* - * r62 and r63 are saved here, and restored from _ISR_Handler, they - * and hold vector number and _ISR_Handler address repsectively. - */ - add sp, sp, #-8 - str r62, [sp, 0] - str r63, [sp, 4] - mov r62, 4 - mov r63, %low(_ISR_Handler) - movt r63, %high(_ISR_Handler) - jr r63 - -.balign 4 -TYPE_FUNC(_EPIPHANY_Exception_default) -SYM(_EPIPHANY_Exception_default): - idle diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am b/c/src/lib/libbsp/i386/pc386/Makefile.am index aa10b8f2ad..2b3ee03a2a 100644 --- a/c/src/lib/libbsp/i386/pc386/Makefile.am +++ b/c/src/lib/libbsp/i386/pc386/Makefile.am @@ -20,11 +20,11 @@ _SUBDIRS = . tools TMPINSTALL_FILES = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -start16.$(OBJEXT): start/start16.S +start16.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start16.S $(CPPASCOMPILE) $(AM_CPPFLAGS) -DHEADERADDR=$(HEADERADDR) -o $@ -c $< start16-elf32.$(OBJEXT): start16.$(OBJEXT) @@ -136,7 +136,7 @@ librtemsbsp_a_SOURCES += ../shared/smp/getcpuid.c librtemsbsp_a_SOURCES += ../shared/smp/smp-imps.c project_lib_DATA += appstart.$(OBJEXT) -appcpustart.$(OBJEXT): start/start16.S +appcpustart.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start16.S $(CPPASCOMPILE) $(AM_CPPFLAGS) -DSMP_SECONDARY_CORE -o $@ -c $< appstart.$(OBJEXT): appcpustart.$(OBJEXT) diff --git a/c/src/lib/libbsp/i386/pc386/start/start.S b/c/src/lib/libbsp/i386/pc386/start/start.S deleted file mode 100644 index 51cd4711f0..0000000000 --- a/c/src/lib/libbsp/i386/pc386/start/start.S +++ /dev/null @@ -1,345 +0,0 @@ -/*-------------------------------------------------------------------------+ -| start.s v1.1 - PC386 BSP - 1997/08/07 -+--------------------------------------------------------------------------+ -| This file contains the entry point for the application. -| The name of this entry point is compiler dependent. -| It jumps to the BSP which is responsible for performing all initialization. -+--------------------------------------------------------------------------+ -| (C) Copyright 1997 - -| - NavIST Group - Real-Time Distributed Systems and Industrial Automation -| -| http://pandora.ist.utl.pt -| -| Instituto Superior Tecnico * Lisboa * PORTUGAL -+--------------------------------------------------------------------------+ -| Modified the 20/05/1998 by valette@crf.canon.fr in order to give a working -| example of eraly stage debugging via the DEBUG_EARLY_START define. -+--------------------------------------------------------------------------+ -| Disclaimer: -| -| This file is provided "AS IS" without warranty of any kind, either -| expressed or implied. -+--------------------------------------------------------------------------+ -| This code is based on an earlier generation RTEMS i386 start.s and the -| following copyright applies: -| -| ************************************************************************** -| * COPYRIGHT (c) 1989-2012. -| * On-Line Applications Research Corporation (OAR). -| * -| * The license and distribution terms for this file may be -| * found in the file LICENSE in this distribution or at -| * http://www.rtems.org/license/LICENSE. -| ************************************************************************** -+--------------------------------------------------------------------------*/ - -/* - * The most trivial start.s possible. It does not know anything - * about system it is running on, so it will jump to appropriate - * place in BSP specific place to do things it knows nothing about - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> -#include <bspopts.h> - -/*----------------------------------------------------------------------------+ -| Size of heap and stack: -+----------------------------------------------------------------------------*/ - -#ifndef CPU_STACK_ALIGNMENT -#error "Missing header ? CPU_STACK_ALIGNMENT NOT DEFINED" -#endif - -.set STACK_SIZE, 0x1000 - -/*----------------------------------------------------------------------------+ -| CODE section -+----------------------------------------------------------------------------*/ - -BEGIN_CODE - - PUBLIC (start) # GNU default entry point - - EXTERN (boot_card) -#if USE_VBE_RM - EXTERN (vesa_realmode_bootup_init) -#endif - EXTERN (_load_segments) - EXTERN (_return_to_monitor) - EXTERN (_IBMPC_initVideo) - EXTERN (debugPollingGetChar) - EXTERN (checkCPUtypeSetCr0) - EXTERN (printk) -#ifdef __SSE__ - EXTERN (x86_capability) -#ifdef __SSE3__ - EXTERN (x86_capability_x) -#endif -#endif - -/* - * In case this crashes on your machine and this is not due - * to video mode set by the loader, you may try to define - * the following variable: - */ -/* #define DEBUG_EARLY_START */ - -SYM (start): - /* - * When things are really, REALLY!, bad -- turn on the speaker and - * lock up. This shows whether or not we make it to a certain - * location. - */ -#if 0 - inb $0x61, al - orb $0x03, al - outb al, $0x61 # enable the speaker -speakl: jmp speakl # and SPIN!!! -#endif - - nop - cli # DISABLE INTERRUPTS!!! - cld - - /* Save multiboot info if we detect a multiboot loader */ - cmp $0x2badb002,eax - jne 2f - - /* We have multiboot info; let's hope DS and ES are OK... */ - movl ebx, SYM(_boot_multiboot_info_p) - /* Check for memory size info and save */ - movl ebx, esi - movl (esi), eax - movl eax, ebx - movl $SYM(_boot_multiboot_info), edi - /* save flags, always present */ - movsd - /* flag 1 is memory */ - and $1, eax - je 1f - movl $2, ecx - rep movsd - /* flag 2 is the command line */ -1: movl ebx, eax - and $4, eax - je 3f - movl (_boot_multiboot_info_p), eax - movl 16(eax), esi - movl $255, ecx -2: movzbl (esi), eax - test al, al - je 3f - movb al, (edi) - inc edi - inc esi - dec ecx - je 3f - jmp 2b -3: xor al, al - movb al, (edi) -#ifdef DEBUG_EARLY_START - /* - * Must get video attribute to have a working printk. - * Note that the following code assume we already have - * valid segments and a stack. It should be true for - * any loader starting RTEMS in protected mode (or - * at least I hope so : -)). - */ - call _IBMPC_initVideo - /* - * try printk and a getchar in polling mode ASAP - */ - movl $welcome_msg, 0(esp) - call printk - addl $4, esp - - /* call debugPollingGetChar */ - -#endif - -/*----------------------------------------------------------------------------+ -| Load the segment registers (this is done by the board's BSP) and perform any -| other board specific initialization procedures, this piece of code -| does not know anything about -| -| NOTE: Upon return, gs will contain the segment descriptor for a segment which -| maps directly to all of physical memory. -+----------------------------------------------------------------------------*/ - - jmp SYM (_load_segments) # load board dependent segments - -/*----------------------------------------------------------------------------+ -| Set up the stack -+----------------------------------------------------------------------------*/ - - PUBLIC (_establish_stack) -SYM (_establish_stack): - - movl $_end, eax # eax = end of bss/start of heap - addl $STACK_SIZE, eax # make room for stack - subl $4, eax # reserve room for arg to 'boot_card' - andl $ - CPU_STACK_ALIGNMENT, eax # align SP on CPU_STACK_ALIGNMENT boundary - movl eax, esp # set stack pointer - movl eax, ebp # set base pointer - -/*----------------------------------------------------------------------------+ -| Zero out the BSS segment -+----------------------------------------------------------------------------*/ - -SYM (zero_bss): - cld # make direction flag count up - movl $ SYM (_end), ecx # find end of .bss - movl $ SYM (__bss_start), edi # edi = beginning of .bss - subl edi, ecx # ecx = size of .bss in bytes - shrl ecx # size of .bss in longs - shrl ecx - xorl eax, eax # value to clear out memory - repne # while ecx != 0 - stosl # clear a long in the bss - -#if BSP_ENABLE_VGA -/*-------------------------------------------------------------------+ -| Initialize the video because zero_bss has cleared initVideo parameters -| if it was called earlier -| So from now we can use printk -+-------------------------------------------------------------------*/ - call _IBMPC_initVideo - -#if USE_VBE_RM - call vesa_realmode_bootup_init -#endif -#endif - -/*---------------------------------------------------------------------+ -| Check CPU type. Enable Cache and init coprocessor if needed. -+---------------------------------------------------------------------*/ - call checkCPUtypeSetCr0 - -#ifdef __SSE__ - call SYM(enable_sse) -#endif - -/*---------------------------------------------------------------------+ -| Transfer control to User's Board Support Package -| Note: at the top we reserved space for the argument -| so that -| initial_esp = ( TOS - 4 ) & ~(CPU_STACK_ALIGNMENT-1) -| this ensures that -| 1) esp is now aligned -| 2) there is space for the cmdline pointer which we just -| may store at *(esp) -+---------------------------------------------------------------------*/ - - movl $SYM(_boot_multiboot_cmdline), (esp) - call SYM (boot_card) - - cli # stops interrupts from being processed after hlt! - hlt # shutdown - -#ifdef __SSE__ -/*--------------------------------------------------------------------+ - | Enable SSE; we really only care about fxsave/fxrstor and leave - | The only feature *we* (as an OS) use is fxsave/fxrstor. - | But as a courtesy we make sure we don't execute on hardware - | that doesn't support features possibly used by the compiler. -+---------------------------------------------------------------------*/ - PUBLIC (enable_sse) -SYM(enable_sse): - movl SYM (x86_capability), eax - testl $0x01000000, eax - jne 1f - movl $SYM (no_fxsave_msg), 0(esp) - jmp SYM(_sse_panic) -1: - testl $0x02000000, eax - jne 1f - movl $SYM (no_sse_msg), 0(esp) - jmp SYM(_sse_panic) -1: -#ifdef __SSE2__ - testl $0x04000000, eax - jne 1f - movl $SYM (no_sse2_msg), 0(esp) - jmp SYM(_sse_panic) -1: -#endif -#ifdef __SSE3__ - movl SYM (x86_capability_x), eax - testl $1, eax - jne 1f - movl $SYM (no_sse3_msg), 0(esp) - jmp SYM(_sse_panic) -1: -#endif - mov cr4, eax # OK to enable now - or $0x600, eax - mov eax, cr4 - ret - -SYM(_sse_panic): - call SYM(printk) -1: hlt - jmp 1b -#endif - -END_CODE - -BEGIN_DATA - PUBLIC(_boot_multiboot_info_p) -SYM(_boot_multiboot_info_p): - .long 0 - - PUBLIC(_boot_multiboot_info) - PUBLIC(_boot_multiboot_flags) - PUBLIC(_boot_multiboot_memory) - PUBLIC(_boot_multiboot_cmdline) -SYM(_boot_multiboot_info): -SYM(_boot_multiboot_flags): - .long 0 /* flags */ -SYM(_boot_multiboot_memory): - .long 0 /* mem_lower */ - .long 0 /* mem_upper */ -SYM(_boot_multiboot_cmdline): - .rept 256 /* cmd line */ - .byte 0 - .endr - - PUBLIC(_stack_size) -SYM(_stack_size): - .long STACK_SIZE - -#ifdef DEBUG_EARLY_START - - PUBLIC (welcome_msg) -SYM (welcome_msg) : - .string "Ready to debug RTEMS ?\nEnter <CR>\n" - - PUBLIC (hex_msg) -SYM (hex_msg) : - .string "0x%x\n" - - PUBLIC (made_it_msg) -SYM (made_it_msg) : - .string "made it to %d\n" - -#endif - -#ifdef __SSE__ -SYM (no_fxsave_msg) : - .string "PANIC: compiled for SSE but CPU seems to have no FXSAVE/FXRSTOR support (which I need)\n" -SYM (no_sse_msg) : - .string "PANIC: compiled for SSE but your CPU seems to have no SSE support\n" -#ifdef __SSE2__ -SYM (no_sse2_msg) : - .string "PANIC: compiled for SSE2 but your CPU seems to have no SSE2 support\n" -#endif -#ifdef __SSE3__ -SYM (no_sse3_msg) : - .string "PANIC: compiled for SSE3 but your CPU seems to have no SSE3 support\n" -#endif -#endif - -END_DATA - -END diff --git a/c/src/lib/libbsp/i386/pc386/start/start16.S b/c/src/lib/libbsp/i386/pc386/start/start16.S deleted file mode 100644 index 3d46f40ed6..0000000000 --- a/c/src/lib/libbsp/i386/pc386/start/start16.S +++ /dev/null @@ -1,254 +0,0 @@ -/*--------------------------------------------------------------------------+ - * start16.s v1.0 - PC386 BSP - 1998/04/13 - *--------------------------------------------------------------------------+ - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing all initialization. - *--------------------------------------------------------------------------+ - * (C) Copyright 1997 - - * - NavIST Group - Real-Time Distributed Systems and Industrial Automation - * - * http://pandora.ist.utl.pt - * - * Instituto Superior Tecnico * Lisboa * PORTUGAL - *--------------------------------------------------------------------------+ - * Disclaimer: - * - * This file is provided "AS IS" without warranty of any kind, either - * expressed or implied. - *--------------------------------------------------------------------------+ - */ - -/* - * COPYRIGHT (c) 2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include <bspopts.h> - -/*---------------------------------------------------------------------------+ -| Constants -+----------------------------------------------------------------------------*/ - -#if defined(SMP_SECONDARY_CORE) -.set PROT_CODE_SEG, 0x08 # offset of code segment descriptor into GDT -#else -.set PROT_CODE_SEG, 0x0 # offset of code segment descriptor into GDT -#endif - -.set PROT_DATA_SEG, 0x10 # offset of code segment descriptor into GDT -.set CR0_PE, 1 # protected mode flag on CR0 register -.set HDRSTART, HEADERADDR # address of start of bin2boot header -.set HDROFF, 0x24 # offset into bin2boot header of start32 addr -.set STACKOFF, 0x200-0x10 # offset to load into %esp, from start of image - -/* #define NEW_GAS */ -#ifdef NEW_GAS - #define LJMPL ljmpl -#else - #define LJMPL ljmp -#endif - -/*----------------------------------------------------------------------------+ -| CODE section -+----------------------------------------------------------------------------*/ - -.text -#if defined(SMP_SECONDARY_CORE) - .globl app_processor_start # entry point -app_processor_start: -#else - .globl _start16 # entry point - .globl start16 -start16: -_start16: -#endif - -.code16 - cli # DISABLE INTERRUPTS!!! -#if defined(SMP_SECONDARY_CORE) - jmp 1f - .align 4 -app_cpu_start: - .long 0 -app_cpu_stack: - .long 0 -1: -#endif - movw %cs, %ax # Initialize the rest of - movw %ax, %ds # segment registers - movw %ax, %es - movw %ax, %ss - -#if !defined(SMP_SECONDARY_CODE) && (RTEMS_VIDEO_80x50 == 1) - movl $0x0040,%eax # use 32 bit constant to ensure 16 MSB=0 - mov %ax,%es - movw %es:0x4a, %ax # get 16 bit number of columns - cmpw $0, %ax # or 0 if no video adapter - je 1f # if no video, skip touching it - /*---------------------------------------------------------------------+ - | Switch VGA video to 80 lines x 50 columns mode. Has to be done before - | turning protected mode on since it uses BIOS int 10h (video) services. - +---------------------------------------------------------------------*/ - - movw $0x0003, %ax # forced set - int $0x10 - movw $0x1112, %ax # use 8x8 font - xorb %bl, %bl - int $0x10 - movw $0x1201, %ax # turn off cursor emulation - movb $0x34, %bl - int $0x10 - movb $0x01, %ah # define cursor (scan lines 0 to 7) - movw $0x0007, %cx - int $0x10 -1: -#endif /* !SMP_SECONDARY_CODE and RTEMS_VIDEO_80x50 */ - - /*---------------------------------------------------------------------+ - | Bare PC machines boot in real mode! We have to turn protected mode on. - +---------------------------------------------------------------------*/ - -#if defined(SMP_SECONDARY_CORE) - lgdt gdtptr - app_processor_start # load Global Descriptor Table -#else - lgdt gdtptr - start16 # load Global Descriptor Table -#endif /* SMP_SECONDARY_CORE */ - - movl %cr0, %eax - orl $CR0_PE, %eax - movl %eax, %cr0 # turn on protected mode -#if defined(SMP_SECONDARY_CORE) - LJMPL $PROT_CODE_SEG, $2f # flush prefetch queue, and reload %cs -#else - LJMPL $PROT_CODE_SEG, $2f # flush prefetch queue, and reload %cs -#endif -.code32 -2: - - /*---------------------------------------------------------------------+ - | load the other segment registers - +---------------------------------------------------------------------*/ - movl $PROT_DATA_SEG, %eax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss -#if defined(SMP_SECONDARY_CORE) - movl app_cpu_stack, %esp # stack pointer - movl app_cpu_stack, %ebp # base pointer - #else - movl $start16 + STACKOFF, %esp # set up stack pointer - addl $start16 + STACKOFF, %ebp # set up stack pointer -#endif /* SMP_SECONDARY_CORE */ - - /*---------------------------------------------------------------------+ - | we have to enable A20 in order to access memory above 1MByte - +---------------------------------------------------------------------*/ - call empty_8042 - movb $0xD1, %al # command write - outb %al, $0x64 - call empty_8042 - movb $0xDF, %al # A20 on - outb %al, $0x60 - call empty_8042 - - call pc386_delay - call pc386_delay - call pc386_delay - -#if defined(SMP_SECONDARY_CORE) - movl app_cpu_start, %eax # jump to app CPU start -#else - movl %cs:HDRSTART + HDROFF, %eax # jump to start of 32 bit code -#endif /* SMP_SECONDARY_CORE */ - pushl %eax - ret - - -/*----------------------------------------------------------------------------+ -| pc386_delay -+------------------------------------------------------------------------------ -| Delay is needed after doing I/O. -| -| The outb version is OK on most machines BUT the loop version ... -| -| will delay for 1us on 1Gz machine, it will take a little bit -| longer on slower machines, however, it does not matter because we -| are going to call this function only a few times -! -| NOTE: Saving the content of the EAX register just in case. - Rosimildo. -+----------------------------------------------------------------------------*/ - .p2align 4 - .globl _pc386_delay - .globl pc386_delay -pc386_delay: -_pc386_delay: - pushl %eax -#if defined(USE_OUTB_FOR_DELAY) - outb %al, $0x80 # about 1uS delay on most machines - -#else - - movl $0x200, %eax -pc386_delay1: - dec %eax - jnz pc386_delay1 -#endif - popl %eax - ret - -/*----------------------------------------------------------------------------+ -| empty_8042 -+------------------------------------------------------------------------------ -| This routine checks that the keyboard command queue is empty (after emptying -| the output buffers). -| No timeout is used - if this hangs there is something wrong with the machine, -| and we probably couldn't proceed anyway. -+----------------------------------------------------------------------------*/ - .p2align 4 - .globl _empty_8042 - .globl empty_8042 -empty_8042: -_empty_8042: - call pc386_delay - inb $0x64, %al # 8042 status port - testb $0x01, %al # output buffer? - jz no_output - call pc386_delay - in $0x60, %al # read it - jmp empty_8042 -no_output: - test $0x02, %al # is input buffer full? - jnz empty_8042 # yes - loop - ret - -/*----------------------------------------------------------------------------+ -| DATA section -+----------------------------------------------------------------------------*/ - -/************************** -* GLOBAL DESCRIPTOR TABLE * -**************************/ - - .p2align 4 -gdtptr: - /* we use the NULL descriptor to store the GDT pointer - a trick quite - nifty due to: Robert Collins (rcollins@x86.org) */ - .word gdtlen - 1 - .long gdtptr - .word 0x0000 - - /* code segment */ - .word 0xffff, 0 - .byte 0, 0x9f, 0xcf, 0 - - /* data segment */ - .word 0xffff, 0 - .byte 0, 0x93, 0xcf, 0 - - .set gdtlen, . - gdtptr # length of GDT diff --git a/c/src/lib/libbsp/lm32/lm32_evr/Makefile.am b/c/src/lib/libbsp/lm32/lm32_evr/Makefile.am index d294f3503e..cc89f66618 100644 --- a/c/src/lib/libbsp/lm32/lm32_evr/Makefile.am +++ b/c/src/lib/libbsp/lm32/lm32_evr/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/lm32/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/lm32/milkymist/Makefile.am b/c/src/lib/libbsp/lm32/milkymist/Makefile.am index 1af72ccba3..72b269594e 100644 --- a/c/src/lib/libbsp/lm32/milkymist/Makefile.am +++ b/c/src/lib/libbsp/lm32/milkymist/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/lm32/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/lm32/shared/start/start.S b/c/src/lib/libbsp/lm32/shared/start/start.S deleted file mode 100644 index 71cbb54119..0000000000 --- a/c/src/lib/libbsp/lm32/shared/start/start.S +++ /dev/null @@ -1,160 +0,0 @@ -/* LM32 startup code - * - * This is the entry point on reset and when loading the - * executive from a bootloader. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, - * Micro-Research Finland Oy - */ - -#include "bspopts.h" - - .section .boot,"a",@progbits - .align 4 - - .globl start - .type start,@function - .globl _start - .type _start,@function - .globl __start - .type __start,@function - .globl LatticeDDInit - .type LatticeDDInit,@function - .globl crt0 - .type crt0,@function - -LatticeDDInit: -__start: -_start: -start: - /* Clear r0 */ - xor r0,r0,r0 - /* Disable interrupts */ - wcsr IE, r0 - /* Mask all interrupts */ - wcsr IM,r0 - /* Set exception base address */ - mvhi r1, hi(start) - ori r1, r1, lo(start) - wcsr EBA, r1 - bi crt0 - nop -/* - * Unused handlers call debug handlers - */ -breakpoint_handler: - rcsr r7, DEBA - addi r7, r7, 32 - b r7 - nop - nop - nop - nop - nop -instruction_bus_error_handler: - rcsr r7, DEBA - addi r7, r7, 64 - b r7 - nop - nop - nop - nop - nop -watchpoint_handler: - rcsr r7, DEBA - addi r7, r7, 96 - b r7 - nop - nop - nop - nop - nop -data_bus_error_handler: - rcsr r7, DEBA - addi r7, r7, 128 - b r7 - nop - nop - nop - nop - nop -divide_by_zero_handler: - rcsr r7, DEBA - addi r7, r7, 160 - b r7 - nop - nop - nop - nop - nop -interrupt_handler: - .extern _ISR_Handler - mvhi r0, hi(_ISR_Handler) - ori r0, r0, lo(_ISR_Handler) - b r0 - nop - nop - nop - nop - nop -system_call_handler: - rcsr r7, DEBA - addi r7, r7, 224 - b r7 - nop - nop - nop - nop - nop - -crt0: - /* Flush data cache */ - addi r1, r0, 1 - wcsr DCC, r1 - nop - nop - nop - nop - /* Flush Instruction Cache */ - wcsr ICC, r1 - nop - nop - nop - nop - /* Initialize stack pointer */ - mvhi sp, hi(_fstack-4) - ori sp, sp, lo(_fstack-4) - /* Initialize global pointer */ - mvhi gp, hi(_edata) - ori gp, gp, lo(_edata) - /* Clear bss */ - mvhi r1, hi(_clear_start) - ori r1, r1, lo(_clear_start) - mvhi r3, hi(_clear_end) - ori r3, r3, lo(_clear_end) -.clear_bss: - be r1, r3, .end_clear_bss - sw (r1+0), r0 - addi r1, r1, 4 - bi .clear_bss -.end_clear_bss: - mvi r1, 0 - be r4, r0, .no_rescue - mvhi r1, hi(.rescue_str) - ori r1, r1, lo(.rescue_str) -.no_rescue: - mvhi r7, hi(boot_card) - ori r7, r7, lo(boot_card) - call r7 - # boot_card returns when RTEMS is shutdown -.dead_end: - bi .dead_end - -.section .rodata -.rescue_str: - .ascii "rescue" - diff --git a/c/src/lib/libbsp/m32c/m32cbsp/Makefile.am b/c/src/lib/libbsp/m32c/m32cbsp/Makefile.am index feaa61884b..226aadedd8 100644 --- a/c/src/lib/libbsp/m32c/m32cbsp/Makefile.am +++ b/c/src/lib/libbsp/m32c/m32cbsp/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m32c/m32cbsp/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m32c/m32cbsp/start/start.S b/c/src/lib/libbsp/m32c/m32cbsp/start/start.S deleted file mode 100644 index e8268a7bec..0000000000 --- a/c/src/lib/libbsp/m32c/m32cbsp/start/start.S +++ /dev/null @@ -1,183 +0,0 @@ -/* - -Copyright (c) 2005 Red Hat Incorporated. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - The name of Red Hat Incorporated may not be used to endorse - or promote products derived from this software without specific - prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - -#if defined(__r8c_cpu__) || defined(__m16c_cpu__) -#define A16 -#define A(n,w) n -#define W w -#define ALIGN 1 -#else -#define A24 -#define A(n,w) w -#define W l -#define ALIGN 2 -#endif - - .text - - .global _start -_start: -.LFB2: - fset U /* User stack */ - ldc #__stack,sp - -#ifdef A16 - mov.b #%hi8(__romdatastart),r1h - mov.w #%lo16(__romdatastart),a0 - mov.w #__datastart,a1 -#else - mov.l #__romdatastart,a0 - mov.l #__datastart,a1 -#endif - mov.w #__romdatacopysize,r3 - shl.w #-1,r3 - smovf.w - -#ifdef A16 - mov.w #__bssstart,a1 -#else - mov.l #__bssstart,a1 -#endif - mov.w #__bsssize,r3 - shl.w #-1,r3 - mov.w #0,r0 - sstr.w - - /* jsr.a __m32c_init */ - - jsr.a _boot_card -.LFE2: - -#ifdef A24 - /* rv in r0, ok for arg0 */ -#else - mov.w r0,r1 -#endif - - .global _bsp_reset -_bsp_reset: - jsr.a _sys_exit - - .text - - .global _m32c_run_preinit_array - .type _m32c_run_preinit_array,@function -_m32c_run_preinit_array: - mov.W #__preinit_array_start,a0 - mov.W #__preinit_array_end,a1 - jmp.w _m32c_run_inilist - - .global _m32c_run_init_array - .type _m32c_run_init_array,@function -_m32c_run_init_array: - mov.W #__init_array_start,a0 - mov.W #__init_array_end,a1 - jmp.w _m32c_run_inilist - - .global _m32c_run_fini_array - .type _m32c_run_fini_array,@function -_m32c_run_fini_array: - mov.W #__fini_array_start,a0 - mov.W #__fini_array_end,a1 - /* fall through */ - -_m32c_run_inilist: -next_inilist: - cmp.W a0,a1 - jeq done_inilist - pushm a0,a1 - mov.W [a0],a0 -#ifdef A16 - mov.b:s #0,a1 /* zero extends */ - jsri.a a1a0 -#else - jsri.a a0 -#endif - popm a0,a1 - add.W A(#2,#4),a0 - jmp.b next_inilist -done_inilist: - rts - - .section .init,"ax",@progbits - - .global __init - .global __m32c_init -__init: -__m32c_init: - enter #0 - exitd - - .section .fini,"ax",@progbits - - .global __fini - .global __m32c_fini -__fini: -__m32c_fini: - enter #0 - jsr.a _m32c_run_fini_array - exitd - - -;;; Provide Dwarf unwinding information that will help GDB stop -;;; backtraces at the right place. This is stolen from assembly -;;; code generated by GCC with -dA. - .section .debug_frame,"",@progbits -.Lframe0: - .4byte .LECIE0-.LSCIE0 ; Length of Common Information Entry -.LSCIE0: - .4byte 0xffffffff ; CIE Identifier Tag - .byte 0x1 ; CIE Version - .ascii "\0" ; CIE Augmentation - .uleb128 0x1 ; CIE Code Alignment Factor - .sleb128 -1 ; CIE Data Alignment Factor - .byte 0xd ; CIE RA Column - .byte 0xc ; DW_CFA_def_cfa - .uleb128 0xc - .uleb128 0x3 - .byte 0x8d ; DW_CFA_offset, column 0xd - .uleb128 0x3 - .p2align ALIGN -.LECIE0: -.LSFDE0: - .4byte .LEFDE0-.LASFDE0 ; FDE Length -.LASFDE0: - .4byte .Lframe0 ; FDE CIE offset - .4byte .LFB2 ; FDE initial location - .4byte .LFE2-.LFB2 ; FDE address range - .byte 0xf ; DW_CFA_def_cfa_expression - .uleb128 1 ; length of expression - .byte 0x30 ; DW_OP_lit0 - .p2align ALIGN -.LEFDE0: - - .text diff --git a/c/src/lib/libbsp/m68k/av5282/Makefile.am b/c/src/lib/libbsp/m68k/av5282/Makefile.am index 4ad8a6a915..9081d18356 100644 --- a/c/src/lib/libbsp/m68k/av5282/Makefile.am +++ b/c/src/lib/libbsp/m68k/av5282/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/av5282/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/av5282/start/start.S b/c/src/lib/libbsp/m68k/av5282/start/start.S deleted file mode 100644 index 5075851245..0000000000 --- a/c/src/lib/libbsp/m68k/av5282/start/start.S +++ /dev/null @@ -1,393 +0,0 @@ -/* - * uC5282 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bsp.h> -#include <rtems/asm.h> - -#define SRAM_SIZE (64*1024) -#define DEFAULT_IPSBAR 0x40000000 - -BEGIN_CODE -#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4 - - PUBLIC (INTERRUPT_VECTOR) -SYM(INTERRUPT_VECTOR): - .long INITIAL_STACK | 0: Initial 'SSP' - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_spuriousInterrupt) | 64: User spurious handler - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte -/*************************************************************************** - Function : start - - Description : setup the internal SRAM for use and setup the INITIAL STACK ptr. - Also enable the internal peripherals - ***************************************************************************/ -.align 4 - PUBLIC (start) -SYM(start): - move.w #0x0000,d0 | Turn off watchdog timer - move.w d0, (0x40140000) - move.w #0x2000,d0 | Set system frequency to 58960000 - move.w d0, (0x40120000) - move.w #0x2700,sr | Disable interrupts - - move.l #__SRAMBASE+1,d0 | Enable the MCF5282 internal SRAM - movec d0,%rambar | ...so we have a stack - move.l #(INITIAL_STACK),sp | Overwrite the fake stack pointer - - /* - * If we're being started by the debugger, and the debugger has - * moved the IPSBAR, we're doomed........ - */ - move.l #__IPSBAR+1,d0 | Enable the MCF5282 internal peripherals - move.l d0,DEFAULT_IPSBAR - - /* - * Remainder of the startup code is handled by C code - */ - jmp SYM(Init5282) | Start C code (which never returns) - -/*************************************************************************** - Function : CopyDataClearBSSAndStart - - Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, - start C program. Assume that DATA and BSS sizes are multiples of 4. - ***************************************************************************/ -.align 4 - - PUBLIC (CopyDataClearBSSAndStart) -SYM(CopyDataClearBSSAndStart): - lea SYM(_data_dest_start),a0 | Get start of DATA in RAM - lea SYM(_data_src_start),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NODATACOPY | Yes, no copy necessary - lea SYM(_data_dest_end),a1 | Get end of DATA in RAM - bra.s DATACOPYLOOPTEST | Branch into copy loop -DATACOPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -DATACOPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s DATACOPYLOOP | No, skip -NODATACOPY: - -/* Now, clear BSS */ - lea _clear_start,a0 | Get start of BSS - lea _clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - - /* - * Right : Now we're ready to boot RTEMS - */ - clrl d0 | Pass in null to all boot_card() params - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C boot_card function to startup RTEMS - movel a7@+,d0 -MULTI_TASK_EXIT: - nop - nop - trap #14 - bra MULTI_TASK_EXIT - -END_CODE - - .align 2 -BEGIN_DATA_DCL - .align 2 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/csb360/Makefile.am b/c/src/lib/libbsp/m68k/csb360/Makefile.am index 3fd41e5d4c..91812aeec2 100644 --- a/c/src/lib/libbsp/m68k/csb360/Makefile.am +++ b/c/src/lib/libbsp/m68k/csb360/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/csb360/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/csb360/start/start.S b/c/src/lib/libbsp/m68k/csb360/start/start.S deleted file mode 100644 index 299c8dad32..0000000000 --- a/c/src/lib/libbsp/m68k/csb360/start/start.S +++ /dev/null @@ -1,413 +0,0 @@ -/* - * CSB360 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - */ - -/* - * Copyright (C) 2004 Cogent Computer Systems - * Author: Jay Monkman <jtm@lopingdog.com> - * - * Based on start.S from mcf520elite BSP: - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * Based on work: - * David Fiddes, D.J@fiddes.surfaid.org - * http://www.calm.hw.ac.uk/davidf/coldfire/ - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include <bsp.h> - -BEGIN_CODE - -/* Initial stack situated in on-chip static memory */ -#define INITIAL_STACK BSP_MEM_ADDR_SRAM+BSP_MEM_SIZE_SRAM-4 - - PUBLIC (INTERRUPT_VECTOR) -SYM(INTERRUPT_VECTOR): - .long INITIAL_STACK | 00: initial SSP - .long start | 01: Initial PC - .long _unexp_exception | 02: Access Error - .long _unexp_exception | 03: Address Error - .long _unexp_exception | 04: Illegal Instruction - .long _reserved_int | 05: Reserved - .long _reserved_int | 06: Reserved - .long _reserved_int | 07: Reserved - .long _unexp_exception | 08: Priveledge Violation - .long _unexp_exception | 09: Trace - .long _unexp_exception | 0A: Unimplemented A-Line - .long _unexp_exception | 0B: Unimplemented F-Line - .long _unexp_exception | 0C: Debug interrupt - .long _reserved_int | 0D: Reserved - .long _unexp_exception | 0E: Format error - .long _unexp_exception | 0F: Uninitialized interrupt - .long _reserved_int | 10: Reserved - .long _reserved_int | 11: Reserved - .long _reserved_int | 12: Reserved - .long _reserved_int | 13: Reserved - .long _reserved_int | 14: Reserved - .long _reserved_int | 15: Reserved - .long _reserved_int | 16: Reserved - .long _reserved_int | 17: Reserved - .long _spurious_int | 18: Spurious interrupt - .long _avec1_int | 19: Autovector Level 1 - .long _avec2_int | 1A: Autovector Level 2 - .long _avec3_int | 1B: Autovector Level 3 - .long _avec4_int | 1C: Autovector Level 4 - .long _avec5_int | 1D: Autovector Level 5 - .long _avec6_int | 1E: Autovector Level 6 - .long _avec7_int | 1F: Autovector Level 7 - .long _unexp_exception | 20: TRAP #0 - .long _unexp_exception | 21: TRAP #1 - .long _unexp_exception | 22: TRAP #2 - .long _unexp_exception | 23: TRAP #3 - .long _unexp_exception | 24: TRAP #4 - .long _unexp_exception | 25: TRAP #5 - .long _unexp_exception | 26: TRAP #6 - .long _unexp_exception | 27: TRAP #7 - .long _unexp_exception | 28: TRAP #8 - .long _unexp_exception | 29: TRAP #9 - .long _unexp_exception | 2A: TRAP #10 - .long _unexp_exception | 2B: TRAP #11 - .long _unexp_exception | 2C: TRAP #12 - .long _unexp_exception | 2D: TRAP #13 - .long _unexp_exception | 2E: TRAP #14 - .long _unexp_exception | 2F: TRAP #15 - .long _reserved_int | 30: Reserved - .long _reserved_int | 31: Reserved - .long _reserved_int | 32: Reserved - .long _reserved_int | 33: Reserved - .long _reserved_int | 34: Reserved - .long _reserved_int | 35: Reserved - .long _reserved_int | 36: Reserved - .long _reserved_int | 37: Reserved - .long _reserved_int | 38: Reserved - .long _reserved_int | 39: Reserved - .long _reserved_int | 3A: Reserved - .long _reserved_int | 3B: Reserved - .long _reserved_int | 3C: Reserved - .long _reserved_int | 3D: Reserved - .long _reserved_int | 3E: Reserved - .long _reserved_int | 3F: Reserved - - .long _unexp_int | 40-FF: User defined interrupts - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 50: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 60: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 70: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 80: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 90: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | A0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | B0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | C0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | D0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | E0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | F0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - PUBLIC(start) -SYM(start): - move.w #0x2700,sr | First turn off all interrupts! - - move.l #(BSP_RAMBAR + MCF5272_RAMBAR_V), d0 - movec d0,rambar0 | ...so we have a stack - - move.l #(INITIAL_STACK),sp | Set up stack again (may be we are - | going here from monitor or with - | BDM interface assistance) - - /* - * Remainder of the startup code is handled by C code - */ - jmp SYM(init5272) | Start C code (which never returns) - -/*************************************************************************** - Function : clear_bss - - Description : clear BSS segment - ***************************************************************************/ - PUBLIC (clear_bss) -SYM(clear_bss): - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - rts - - - - - PUBLIC (start_csb360) -SYM(start_csb360): - /* - * Right : Now we're ready to boot RTEMS - */ - clrl d0 | Pass in null to all boot_card() params - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C boot_card function to startup RTEMS - - - -# Wait forever -_stop: - nop - stop #0x2700 - jmp _stop - -# The following labelled nops is a placeholders for breakpoints -_unexp_exception: - nop - jmp _stop - -_unexp_int: - nop - jmp _stop - -_reserved_int: - nop - jmp _stop - -_spurious_int: - nop - jmp _stop - -_avec1_int: - nop - jmp _unexp_int - -_avec2_int: - nop - jmp _unexp_int - -_avec3_int: - nop - jmp _unexp_int - -_avec4_int: - nop - jmp _unexp_int - -_avec5_int: - nop - jmp _unexp_int - -_avec6_int: - nop - jmp _unexp_int - -_avec7_int: - nop - jmp _unexp_int - - -END_CODE - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/Makefile.am b/c/src/lib/libbsp/m68k/gen68340/Makefile.am index ab20c9dda3..7bf172e820 100644 --- a/c/src/lib/libbsp/m68k/gen68340/Makefile.am +++ b/c/src/lib/libbsp/m68k/gen68340/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/gen68340/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/gen68340/start/start.S b/c/src/lib/libbsp/m68k/gen68340/start/start.S deleted file mode 100644 index 794c6d75b6..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start/start.S +++ /dev/null @@ -1,877 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - */ - -#include <rtems/asm.h> -#include <m68349.inc> - -#include <bsp.h> /* to indicate dependencies */ - -/* old addresses for AST68340 only, undefine for AST68349 */ -#define _OLD_ASTECC 1 - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - move.w (a7),_boot_panic_registers+4 | SR - move.l 2(a7),_boot_panic_registers | PC - move.w 6(a7),_boot_panic_registers+6 | format & vector - movem.l d0-d7/a0-a7, _boot_panic_registers+8 - movec sfc, d0 - movem.l d0, _boot_panic_registers+72 - movec dfc, d0 - movem.l d0, _boot_panic_registers+76 - movec vbr, d0 - movem.l d0, _boot_panic_registers+80 - jmp SYM(_dbug_dumpanic) - bra.s _crt0_cold_start - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -BEGIN_DATA - -/* equates */ - -.equ _CPU340, 0x0 -.equ _CPU349, 0x31 - -#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ -.equ _EPLD_CS_BASE, 0x1 -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x10000000 /* SRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ - -#else /* new addresses for AST68349 and 68340 */ - -.equ _EPLD_CS_BASE, 0x5 -.equ _PROM_Start, 0x50000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x80000000 /* DRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ -#endif - -.equ _SPEED349, 0xD680 /* 24 Mhz */ -.equ _SPEED340, 0xD700 /* 25 Mhz */ -/* .equ _SPEED340, 0xCE00 16 Mhz */ - -#define crt0_boot_type d0 /* cold/warm start (must be D0) */ -#define crt0_temp d1 -#define crt0_cpu_type d2 -#define crt0_csswitch d3 -#define crt0_buswidth d4 -#define crt0_pdcs d5 -#define crt0_spare6 d6 -#define crt0_spare7 d7 -#define crt0_sim_base a0 -#define crt0_glue a1 -#define crt0_dram a2 -#define crt0_ptr3 a3 -#define crt0_ptr4 a4 -#define crt0_ptr5 a5 -#define crt0_ptr6 a6 - -/* -- PDCS buffer equates -- */ -.equ pdcs_mask, 0x1F /* DRAM configuration */ -.equ pdcs_sw12, 7 /* switch 12 */ -.equ pdcs_sw11, 6 /* switch 11 */ -.equ pdcs_sw14, 5 /* switch 14 */ - -.equ bit_cache, pdcs_sw12 /* enable cache if on */ -.equ bit_meminit, pdcs_sw11 /* init memory if on */ - -/* -- Initialization stack and vars -- */ - -/* When using DWARF, everything must be a multiple of 16-bits. */ -#if 1 -_AsteccBusWidth: ds.w 0x0101 -_AsteccCsSwitch: ds.w 0x0101 -#else -_AsteccBusWidth: ds.b 1 -_AsteccCsSwitch: ds.b 1 -#endif -_AsteccCpuName: ds.l 1 - -.align 4 - -_crt0_init_stack: - ds.l 500 -_crt0_init_stktop: - -/* -- Initialization code -- */ -BEGIN_CODE - -.align 4 - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - -/* When using DWARF, everything must be a multiple of 16-bits. */ - .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards " - .text - dc.w 0 -.align 4 - -.globl start -start: - -_crt0_cold_start: - moveq.l #0,crt0_boot_type | signal cold reset - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,crt0_boot_type | signal warm reset - -_crt0_common_start: - move.w #0x2700,sr | disable interrupts and switch to interrupt mode - movea.l #_crt0_init_stktop,sp | set up initialization stack - - move.l #Entry,crt0_temp | VBR initialization - movec.l crt0_temp,vbr | - moveq.l #0x07,crt0_temp - movec.l crt0_temp,dfc | prepare access in CPU space - move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES - moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) - - movea.l #BASE_SIM,crt0_sim_base - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(crt0_sim_base) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(crt0_sim_base) - - /* -- enable /IRQ3, 5, 6, 7 -- */ - move.b #0xE8,SIM_PPRB(crt0_sim_base) - - /* -- enable autovector on /IRQ7 -- */ - move.b #0x80,SIM_AVR(crt0_sim_base) - - /* -- test CPU type -- */ - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne cpu_is_68340 - -/*-------------------------------------------------------------------------------------------*/ -cpu_is_68349: - - /* -- set cpu clock -- */ - move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock - -sync_wait349: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait349 - - /* to allow access to the EPLD internal registers, it is necessary - to disable the global chip-select /CS0 (which decodes every external - cycles). To do that, we initialize the 68349 internal RAM, - copy a part of the initialization code in it, and jump there. - from that moment, /CS0 is not used, therefore it can be initialized - with its default value. Its width may be incorrect, but it will be - adjusted later. The goal is to avoid any conflict with - the accesses to the EPLD registers. - When this is done, we read the RESET parameters (boot prom width - and chip-select switch) and proceed with the initialization - when all is done, we jump back to the boot prom now - decoded with a properly configured /CS0 */ - - /*-------------------------------------*/ - /* -- configure internal SRAM banks -- */ - - move.l #0x00000000,QDMM_MCR(crt0_sim_base) - move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) - move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) - move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) - move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) - - /*--------------------------------------------------------*/ - /* -- copy to address of the 68349 initialization code -- */ - - lea.l _copy_start_code(%pc),crt0_ptr3 - lea.l _copy_end_code(%pc),crt0_ptr4 - move.l crt0_ptr4,crt0_temp - sub.l crt0_ptr3,crt0_temp - add.l #3,crt0_temp | adjust to next long word - lsr.l #2,crt0_temp - - move.l #_FastRam_Start,crt0_ptr4 -_copy_loop: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - subq.l #1,crt0_temp - bne.s _copy_loop - bra.l _FastRam_Start | jump to code in internal RAM - - /*------------------------------------*/ - /* -- start of initialization code -- */ - -_copy_start_code: - bra.l _begin_68349_init - - /*----------------------------------------------------------*/ - /* Astecc 68349 board : chip-select initialization values */ - -_table_csepld: -/* When using DWARF, everything must be a multiple of 16-bits. */ -#if 1 - dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) | 0x80 | 16 bits, 0ws - dc.w 0x9090 | 16 bits, ext /dsack - -#else - dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws - dc.b 0x80 | 16 bits, 0 ws - dc.b 0x90 | 16 bits, ext /dsack - dc.b 0x90 | 16 bits, ext /dsack -#endif - -_table_cs349: - dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) - dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 - dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) - dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 - dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) - dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 - dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) - dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 - - /*-------------------------------------------------*/ -_begin_68349_init: - - /*-------------------------------------------------*/ - /* 68349 chip select initialization - - at this stage, the width of /CS0 may be incorrect - it will be corrected later - */ - -_cs68349_init: - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - - moveq.l #0x07,crt0_temp -_cs349_init2: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - dbra crt0_temp,_cs349_init2 - - /*-----------------------------------------------*/ - /* -- prepare access to the internal registers --*/ - moveq.l #EPLD_SPACE,crt0_temp - movec.l crt0_temp,dfc - movec.l crt0_temp,sfc - move.l #GLUE_EPLD,crt0_glue - move.l #DRAM_EPLD,crt0_dram - - /*-------------------------------------------*/ - /* EPLD generated /CS[3..0] must be disabled */ - -_csepld_clear: - move.l crt0_glue,crt0_ptr4 - move.w #3,crt0_spare6 - clr.b crt0_temp - -_csepld_clear1: - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld_clear1 - - /*---------------------------------------------------------*/ - /* -- get width of boot PROM, and active chip-select set --*/ - moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch - move.b crt0_csswitch,crt0_buswidth - - /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) - : sel == 1 => EPLD chip_selects (/CS[3..0]) */ - and.b #1,crt0_csswitch - - /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 - bus width : 32 16 8 ext./dsackx */ - rol.b #2,crt0_buswidth - and.b #3,crt0_buswidth - - /*----------------------------------------------------*/ - /* -- configure chip select 0 with boot prom width -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - move.l (crt0_ptr3)+,crt0_temp - and.b #0xFC,crt0_temp | clear PS0 & PS1 - or.b crt0_buswidth,crt0_temp | set boot PROM bus width - move.l crt0_temp,(crt0_ptr4)+ - - /*------------------------*/ - /* -- read PDCS buffer -- */ - moves.b REG_PDCS(crt0_glue),crt0_pdcs -/* move.b #0x3F,crt0_pdcs pour test */ - - /*---------------------------------------*/ - /* -- EPLD chip-select initialization -- */ - /*---------------------------------------*/ - btst.b #0,crt0_csswitch - beq _cs_init_end - - /*--------------------------------------------*/ - /* 68349 generated /CS[3..0] must be disabled */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - moveq.l #0x03,crt0_temp -_cs349_clear: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - move.l (crt0_ptr3)+,crt0_spare6 - and.b #0xFE,crt0_spare6 | disable chip-select - move.l crt0_spare6,(crt0_ptr4)+ - dbra crt0_temp,_cs349_clear - - /*---------------------------------------------*/ - /* EPLD generated /CS[3..0] must be configured */ -_csepld_init: - move.l crt0_glue,crt0_ptr4 - lea.l _table_csepld(%pc),crt0_ptr3 - - move.b (crt0_ptr3)+,crt0_temp - or.b #0x20,crt0_temp | default width is 32 bits - tst.b crt0_buswidth | is boot PROM bus width 32 bits ? - beq _csepld1 | if not - and.b #0xDF,crt0_temp | set width to 16 bits -_csepld1: - moves.b crt0_temp,(crt0_ptr4)+ - - moveq.l #0x02,crt0_spare6 -_csepld2: - move.b (crt0_ptr3)+,crt0_temp - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld2 - -_cs_init_end: - - /*--------------------------------------*/ - /* -- DRAM controller initialization -- */ -_dram_init: - move.w #15,crt0_temp - move.l #_ExtRam_Start,crt0_ptr3 - -_dram_init1: - clr.l (crt0_ptr3)+ | must access DRAM - dbra crt0_temp,_dram_init1 | prior to init refresh - -_dram_init2: - move.b #3,crt0_temp - moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states - - move.b #0x81,crt0_temp - moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs - - move.b #0,crt0_temp - moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes - - /*-----------------------*/ - /* -- configure cache -- */ -_init_cache: - move.l #0x000001E0,CACHE_MCR(crt0_sim_base) - btst.b #bit_cache,crt0_pdcs - bne _init_cache_end - or.l #0x00000001,CACHE_MCR(crt0_sim_base) - -_init_cache_end: - - /*-----------------------------*/ - /* -- timers initialization -- */ - - clr.b crt0_temp - moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 - moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 - - /*--------------------------*/ - /* -- I2C initialization -- */ - move.b #3,crt0_temp - moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports - - /*-----------------------------------------*/ - /* -- baudrate generator initialization -- */ - move.b #2,crt0_temp - moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 - - /*-------------------------------*/ - /* -- IO port initialization -- */ - clr.b crt0_temp - moves.b crt0_temp,REG_IO(crt0_glue) | set port as input - - /* -- */ - - move.l #68349,crt0_cpu_type - - /* -- jump back to PROM -- */ - - jmp.l (_fill_test) | must be absolute long - -_copy_end_code: - -/*------------------------------------------------- - initialization code for the 68340 board - -------------------------------------------------*/ - - /* Astecc 68340 board : chip-select initialization values */ -_table_cs340: - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -cpu_is_68340: - - /* -- set cpu clock -- */ - move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock -sync_wait340: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait340 - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs340(%pc),crt0_ptr3 - moveq.l #0x07,crt0_temp -_b_cs340: - move.l (crt0_ptr3)+,crt0_ptr5 - move.l crt0_ptr5,(crt0_ptr4)+ | pour test - dbra crt0_temp,_b_cs340 - - move.l #68340,crt0_cpu_type - move.b #0,crt0_csswitch | CPU - move.b #1,crt0_buswidth | 16 bits - - /*------------------------------------------------- - fill RAM if COLDSTART - -------------------------------------------------*/ -_fill_test: - - tst.l crt0_boot_type - bne _dont_fill - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill - btst.b #bit_meminit,crt0_pdcs - bne _dont_fill - - /* fill main memory */ -_fill: - move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars - move.l #_ExtRam_Start,crt0_temp - sub.l #_crt0_init_stack,crt0_temp - add.l #_ExtRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_fill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _fill_loop - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill_bccram - - /* fill QDMM memory */ - movea.l #_FastRam_Start,crt0_ptr3 | get start - move.l #_FastRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word - -_QDMMfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _QDMMfill_loop - bra _dont_fill - - /* fill BCC memory */ -_fill_bccram: - movea.l #_BCCram_Start,crt0_ptr3 | get start - move.l #_BCCram_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_BCCfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _BCCfill_loop - - /*-------------------------------------------------*/ -_dont_fill: - move.b crt0_csswitch,_AsteccCsSwitch - move.b crt0_buswidth,_AsteccBusWidth - move.l crt0_cpu_type,_AsteccCpuName - - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea SYM(_copy_start),a0 | Get start of DATA in RAM - lea SYM(_etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea SYM(_copy_end),a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea _clear_start,a0 | Get start of BSS - lea _clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #_stack_init,a7 | set master stack pointer - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - bra.l SYM(_mainDone) | Stuck forever - - .align 2 -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END diff --git a/c/src/lib/libbsp/m68k/gen68360/Makefile.am b/c/src/lib/libbsp/m68k/gen68360/Makefile.am index 42b1c51f5f..f4d4ec6319 100644 --- a/c/src/lib/libbsp/m68k/gen68360/Makefile.am +++ b/c/src/lib/libbsp/m68k/gen68360/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/gen68360/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/gen68360/start/start.S b/c/src/lib/libbsp/m68k/gen68360/start/start.S deleted file mode 100644 index 8511960e16..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/start/start.S +++ /dev/null @@ -1,418 +0,0 @@ -/* - * - * This file contains the entry point for the application. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Based on the `gen68302' board support package, and covered by the - * original distribution terms. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - */ - -#include <rtems/asm.h> - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long m360+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long _uhoh | 2: Bus error - .long _uhoh | 3: Address error - .long _uhoh | 4: Illegal instruction - .long _uhoh | 5: Zero division - .long _uhoh | 6: CHK, CHK2 instruction - .long _uhoh | 7: TRAPcc, TRAPV instructions - .long _uhoh | 8: Privilege violation - .long _uhoh | 9: Trace - .long _uhoh | 10: Line 1010 emulator - .long _uhoh | 11: Line 1111 emulator - .long _uhoh | 12: Hardware breakpoint - .long _uhoh | 13: Reserved for coprocessor violation - .long _uhoh | 14: Format error - .long _uhoh | 15: Uninitialized interrupt - .long _uhoh | 16: Unassigned, reserved - .long _uhoh | 17: - .long _uhoh | 18: - .long _uhoh | 19: - .long _uhoh | 20: - .long _uhoh | 21: - .long _uhoh | 22: - .long _uhoh | 23: - .long _spuriousInterrupt | 24: Spurious interrupt - .long _uhoh | 25: Level 1 interrupt autovector - .long _uhoh | 26: Level 2 interrupt autovector - .long _uhoh | 27: Level 3 interrupt autovector - .long _uhoh | 28: Level 4 interrupt autovector - .long _uhoh | 29: Level 5 interrupt autovector - .long _uhoh | 30: Level 6 interrupt autovector - .long _uhoh | 31: Level 7 interrupt autovector - .long _uhoh | 32: Trap instruction (0-15) - .long _uhoh | 33: - .long _uhoh | 34: - .long _uhoh | 35: - .long _uhoh | 36: - .long _uhoh | 37: - .long _uhoh | 38: - .long _uhoh | 39: - .long _uhoh | 40: - .long _uhoh | 41: - .long _uhoh | 42: - .long _uhoh | 43: - .long _uhoh | 44: - .long _uhoh | 45: - .long _uhoh | 46: - .long _uhoh | 47: - .long _uhoh | 48: Reserved for coprocessor - .long _uhoh | 49: - .long _uhoh | 50: - .long _uhoh | 51: - .long _uhoh | 52: - .long _uhoh | 53: - .long _uhoh | 54: - .long _uhoh | 55: - .long _uhoh | 56: - .long _uhoh | 57: - .long _uhoh | 58: - .long _uhoh | 59: Unassigned, reserved - .long _uhoh | 60: - .long _uhoh | 61: - .long _uhoh | 62: - .long _uhoh | 63: - .long _uhoh | 64: User defined vectors (192) - .long _uhoh | 65: - .long _uhoh | 66: - .long _uhoh | 67: - .long _uhoh | 68: - .long _uhoh | 69: - .long _uhoh | 70: - .long _uhoh | 71: - .long _uhoh | 72: - .long _uhoh | 73: - .long _uhoh | 74: - .long _uhoh | 75: - .long _uhoh | 76: - .long _uhoh | 77: - .long _uhoh | 78: - .long _uhoh | 79: - .long _uhoh | 80: - .long _uhoh | 81: - .long _uhoh | 82: - .long _uhoh | 83: - .long _uhoh | 84: - .long _uhoh | 85: - .long _uhoh | 86: - .long _uhoh | 87: - .long _uhoh | 88: - .long _uhoh | 89: - .long _uhoh | 90: - .long _uhoh | 91: - .long _uhoh | 92: - .long _uhoh | 93: - .long _uhoh | 94: - .long _uhoh | 95: - .long _uhoh | 96: - .long _uhoh | 97: - .long _uhoh | 98: - .long _uhoh | 99: - .long _uhoh | 100: - .long _uhoh | 101: - .long _uhoh | 102: - .long _uhoh | 103: - .long _uhoh | 104: - .long _uhoh | 105: - .long _uhoh | 106: - .long _uhoh | 107: - .long _uhoh | 108: - .long _uhoh | 109: - .long _uhoh | 110: - .long _uhoh | 111: - .long _uhoh | 112: - .long _uhoh | 113: - .long _uhoh | 114: - .long _uhoh | 115: - .long _uhoh | 116: - .long _uhoh | 117: - .long _uhoh | 118: - .long _uhoh | 119: - .long _uhoh | 120: - .long _uhoh | 121: - .long _uhoh | 122: - .long _uhoh | 123: - .long _uhoh | 124: - .long _uhoh | 125: - .long _uhoh | 126: - .long _uhoh | 127: - .long _uhoh | 128: - .long _uhoh | 129: - .long _uhoh | 130: - .long _uhoh | 131: - .long _uhoh | 132: - .long _uhoh | 133: - .long _uhoh | 134: - .long _uhoh | 135: - .long _uhoh | 136: - .long _uhoh | 137: - .long _uhoh | 138: - .long _uhoh | 139: - .long _uhoh | 140: - .long _uhoh | 141: - .long _uhoh | 142: - .long _uhoh | 143: - .long _uhoh | 144: - .long _uhoh | 145: - .long _uhoh | 146: - .long _uhoh | 147: - .long _uhoh | 148: - .long _uhoh | 149: - .long _uhoh | 150: - .long _uhoh | 151: - .long _uhoh | 152: - .long _uhoh | 153: - .long _uhoh | 154: - .long _uhoh | 155: - .long _uhoh | 156: - .long _uhoh | 157: - .long _uhoh | 158: - .long _uhoh | 159: - .long _uhoh | 160: - .long _uhoh | 161: - .long _uhoh | 162: - .long _uhoh | 163: - .long _uhoh | 164: - .long _uhoh | 165: - .long _uhoh | 166: - .long _uhoh | 167: - .long _uhoh | 168: - .long _uhoh | 169: - .long _uhoh | 170: - .long _uhoh | 171: - .long _uhoh | 172: - .long _uhoh | 173: - .long _uhoh | 174: - .long _uhoh | 175: - .long _uhoh | 176: - .long _uhoh | 177: - .long _uhoh | 178: - .long _uhoh | 179: - .long _uhoh | 180: - .long _uhoh | 181: - .long _uhoh | 182: - .long _uhoh | 183: - .long _uhoh | 184: - .long _uhoh | 185: - .long _uhoh | 186: - .long _uhoh | 187: - .long _uhoh | 188: - .long _uhoh | 189: - .long _uhoh | 190: - .long _uhoh | 191: - .long _uhoh | 192: - .long _uhoh | 193: - .long _uhoh | 194: - .long _uhoh | 195: - .long _uhoh | 196: - .long _uhoh | 197: - .long _uhoh | 198: - .long _uhoh | 199: - .long _uhoh | 200: - .long _uhoh | 201: - .long _uhoh | 202: - .long _uhoh | 203: - .long _uhoh | 204: - .long _uhoh | 205: - .long _uhoh | 206: - .long _uhoh | 207: - .long _uhoh | 208: - .long _uhoh | 209: - .long _uhoh | 210: - .long _uhoh | 211: - .long _uhoh | 212: - .long _uhoh | 213: - .long _uhoh | 214: - .long _uhoh | 215: - .long _uhoh | 216: - .long _uhoh | 217: - .long _uhoh | 218: - .long _uhoh | 219: - .long _uhoh | 220: - .long _uhoh | 221: - .long _uhoh | 222: - .long _uhoh | 223: - .long _uhoh | 224: - .long _uhoh | 225: - .long _uhoh | 226: - .long _uhoh | 227: - .long _uhoh | 228: - .long _uhoh | 229: - .long _uhoh | 230: - .long _uhoh | 231: - .long _uhoh | 232: - .long _uhoh | 233: - .long _uhoh | 234: - .long _uhoh | 235: - .long _uhoh | 236: - .long _uhoh | 237: - .long _uhoh | 238: - .long _uhoh | 239: - .long _uhoh | 240: - .long _uhoh | 241: - .long _uhoh | 242: - .long _uhoh | 243: - .long _uhoh | 244: - .long _uhoh | 245: - .long _uhoh | 246: - .long _uhoh | 247: - .long _uhoh | 248: - .long _uhoh | 249: - .long _uhoh | 250: - .long _uhoh | 251: - .long _uhoh | 252: - .long _uhoh | 253: - .long _uhoh | 254: - .long _uhoh | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -_uhoh: nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.l _uhoh | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -_spuriousInterrupt: - addql #1,_M68kSpuriousInterruptCount - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* - * Initial PC - */ -.globl start -start: - /* - * Step 2: Stay in Supervisor Mode - */ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - oriw #0x3000,sr | Switch to Master Stack Pointer - lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram - | a little below the interrupt stack -#endif - - /* - * Step 3: Write the VBR - */ - lea Entry,a0 | Get base of vector table - movec a0,vbr | Set up the VBR - - /* - * Step 4: Write the MBAR - */ - movec dfc,d1 | Save destination register - moveq #7,d0 | CPU-space funcction code - movec d0,dfc | Set destination function code register - movel #m360+0x101,d0 | MBAR value (mask CPU space accesses) - movesl d0,0x3FF00 | Set MBAR - movec d1,dfc | Restore destination register - - /* - * Step 5: Verify a dual-port RAM location - */ - lea m360,a0 | Point a0 to first DPRAM location - moveb #0x33,d0 | Set the test value - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne _uhoh | If not, bad news! - notb d0 | Flip bits - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne _uhoh | If not, bad news! - - /* - * Remaining steps are handled by C code - */ - jmp _Init68360 | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -_CopyDataClearBSSAndStart: - lea _copy_start,a0 | Get start of DATA in RAM - lea etext,a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea _copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea _clear_start,a0 | Get start of BSS - lea _clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #_stack_init,a7 | set master stack pointer - movel d0,a7@- | command line - jsr boot_card | Call C main - - PUBLIC (_mainDone) -_mainDone: - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.l _mainDone | Stuck forever - - .align 2 -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -environ: - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -_M68kSpuriousInterruptCount: - .long 0 -END_DATA_DCL - -END diff --git a/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am b/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am index 3ba91a7f92..751ae37092 100644 --- a/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am +++ b/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/genmcf548x/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/genmcf548x/start/start.S b/c/src/lib/libbsp/m68k/genmcf548x/start/start.S deleted file mode 100644 index d4d1d9b273..0000000000 --- a/c/src/lib/libbsp/m68k/genmcf548x/start/start.S +++ /dev/null @@ -1,432 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic mcf548x BSP | -+-----------------------------------------------------------------+ -| File: start.S | -+-----------------------------------------------------------------+ -| The file contains the assembly part of MCF548x init code | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| | -| Parts of the code has been derived from the "dBUG source code" | -| package Freescale is providing for M548X EVBs. The usage of | -| the modified or unmodified code and it's integration into the | -| generic mcf548x BSP has been done according to the Freescale | -| license terms. | -| | -| The Freescale license terms can be reviewed in the file | -| | -| Freescale_license.txt | -| | -+-----------------------------------------------------------------+ -| | -| The generic mcf548x BSP has been developed on the basic | -| structures and modules of the av5282 BSP. | -| | -+-----------------------------------------------------------------+ -| | -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| | -| date history ID | -| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | -| 12.11.07 1.0 ras | -| | -\*===============================================================*/ - -/*===============================================================*\ -| Includes | -\*===============================================================*/ -#include <rtems/asm.h> -#include <bsp/linker-symbols.h> - -/*===============================================================*\ -| External references | -\*===============================================================*/ -.extern __MBAR -.extern _CoreSramBase0 -.extern _CoreSramBase1 -.extern _CoreSramSize1 -.extern mcf548x_init -.extern boot_card - -/*===============================================================*\ -| Global symbols | -\*===============================================================*/ - -.global interrupt_vector_table -.global spurious_int_count -.global start - - -/*===============================================================*\ -| Exception Table | -\*===============================================================*/ - -.section ".vectors","ax" /* begin of vectors section */ -PUBLIC (InterruptVectorTable) -SYM(InterruptVectorTable): -INITSP: .long bsp_initstack_end /* Initial SP */ -INITPC: .long start /* Initial PC */ -vector002: .long asm_default_interrupt /* Access Error */ -vector003: .long asm_default_interrupt /* Address Error */ -vector004: .long asm_default_interrupt /* Illegal Instruction */ -vector005: .long asm_default_interrupt /* Reserved */ -vector006: .long asm_default_interrupt /* Reserved */ -vector007: .long asm_default_interrupt /* Reserved */ -vector008: .long asm_default_interrupt /* Privilege Violation */ -vector009: .long asm_default_interrupt /* Trace */ -vector010: .long asm_default_interrupt /* Unimplemented A-Line */ -vector011: .long asm_default_interrupt /* Unimplemented F-Line */ -vector012: .long asm_default_interrupt /* Debug Interrupt */ -vector013: .long asm_default_interrupt /* Reserved */ -vector014: .long asm_default_interrupt /* Format Error */ -vector015: .long asm_default_interrupt /* Unitialized Int. */ -vector016: .long asm_default_interrupt /* Reserved */ -vector017: .long asm_default_interrupt /* Reserved */ -vector018: .long asm_default_interrupt /* Reserved */ -vector019: .long asm_default_interrupt /* Reserved */ -vector020: .long asm_default_interrupt /* Reserved */ -vector021: .long asm_default_interrupt /* Reserved */ -vector022: .long asm_default_interrupt /* Reserved */ -vector023: .long asm_default_interrupt /* Reserved */ -vector024: .long asm_spurious_interrupt /* Spurious Interrupt */ -vector025: .long asm_default_interrupt /* Autovector Level 1 */ -vector026: .long asm_default_interrupt /* Autovector Level 2 */ -vector027: .long asm_default_interrupt /* Autovector Level 3 */ -vector028: .long asm_default_interrupt /* Autovector Level 4 */ -vector029: .long asm_default_interrupt /* Autovector Level 5 */ -vector030: .long asm_default_interrupt /* Autovector Level 6 */ -vector031: .long asm_default_interrupt /* Autovector Level 7 */ -vector032: .long asm_default_interrupt /* TRAP #0 */ -vector033: .long asm_default_interrupt /* TRAP #1 */ -vector034: .long asm_default_interrupt /* TRAP #2 */ -vector035: .long asm_default_interrupt /* TRAP #3 */ -vector036: .long asm_default_interrupt /* TRAP #4 */ -vector037: .long asm_default_interrupt /* TRAP #5 */ -vector038: .long asm_default_interrupt /* TRAP #6 */ -vector039: .long asm_default_interrupt /* TRAP #7 */ -vector040: .long asm_default_interrupt /* TRAP #8 */ -vector041: .long asm_default_interrupt /* TRAP #9 */ -vector042: .long asm_default_interrupt /* TRAP #10 */ -vector043: .long asm_default_interrupt /* TRAP #11 */ -vector044: .long asm_default_interrupt /* TRAP #12 */ -vector045: .long asm_default_interrupt /* TRAP #13 */ -vector046: .long asm_default_interrupt /* TRAP #14 */ -vector047: .long asm_default_interrupt /* TRAP #15 */ -vector048: .long asm_default_interrupt /* Reserved */ -vector049: .long asm_default_interrupt /* Reserved */ -vector050: .long asm_default_interrupt /* Reserved */ -vector051: .long asm_default_interrupt /* Reserved */ -vector052: .long asm_default_interrupt /* Reserved */ -vector053: .long asm_default_interrupt /* Reserved */ -vector054: .long asm_default_interrupt /* Reserved */ -vector055: .long asm_default_interrupt /* Reserved */ -vector056: .long asm_default_interrupt /* Reserved */ -vector057: .long asm_default_interrupt /* Reserved */ -vector058: .long asm_default_interrupt /* Reserved */ -vector059: .long asm_default_interrupt /* Reserved */ -vector060: .long asm_default_interrupt /* Reserved */ -vector061: .long asm_default_interrupt /* Reserved */ -vector062: .long asm_default_interrupt /* Reserved */ -vector063: .long asm_default_interrupt /* Reserved */ -vector064: .long asm_default_interrupt -vector065: .long asm_default_interrupt -vector066: .long asm_default_interrupt -vector067: .long asm_default_interrupt -vector068: .long asm_default_interrupt -vector069: .long asm_default_interrupt -vector070: .long asm_default_interrupt -vector071: .long asm_default_interrupt -vector072: .long asm_default_interrupt -vector073: .long asm_default_interrupt -vector074: .long asm_default_interrupt -vector075: .long asm_default_interrupt -vector076: .long asm_default_interrupt -vector077: .long asm_default_interrupt -vector078: .long asm_default_interrupt -vector079: .long asm_default_interrupt -vector080: .long asm_default_interrupt -vector081: .long asm_default_interrupt -vector082: .long asm_default_interrupt -vector083: .long asm_default_interrupt -vector084: .long asm_default_interrupt -vector085: .long asm_default_interrupt -vector086: .long asm_default_interrupt -vector087: .long asm_default_interrupt -vector088: .long asm_default_interrupt -vector089: .long asm_default_interrupt -vector090: .long asm_default_interrupt -vector091: .long asm_default_interrupt -vector092: .long asm_default_interrupt -vector093: .long asm_default_interrupt -vector094: .long asm_default_interrupt -vector095: .long asm_default_interrupt -vector096: .long asm_default_interrupt -vector097: .long asm_default_interrupt -vector098: .long asm_default_interrupt -vector099: .long asm_default_interrupt -vector100: .long asm_default_interrupt -vector101: .long asm_default_interrupt -vector102: .long asm_default_interrupt -vector103: .long asm_default_interrupt -vector104: .long asm_default_interrupt -vector105: .long asm_default_interrupt -vector106: .long asm_default_interrupt -vector107: .long asm_default_interrupt -vector108: .long asm_default_interrupt -vector109: .long asm_default_interrupt -vector110: .long asm_default_interrupt -vector111: .long asm_default_interrupt -vector112: .long asm_default_interrupt -vector113: .long asm_default_interrupt -vector114: .long asm_default_interrupt -vector115: .long asm_default_interrupt -vector116: .long asm_default_interrupt -vector117: .long asm_default_interrupt -vector118: .long asm_default_interrupt -vector119: .long asm_default_interrupt -vector120: .long asm_default_interrupt -vector121: .long asm_default_interrupt -vector122: .long asm_default_interrupt -vector123: .long asm_default_interrupt -vector124: .long asm_default_interrupt -vector125: .long asm_default_interrupt -vector126: .long asm_default_interrupt -vector127: .long asm_default_interrupt -vector128: .long asm_default_interrupt -vector129: .long asm_default_interrupt -vector130: .long asm_default_interrupt -vector131: .long asm_default_interrupt -vector132: .long asm_default_interrupt -vector133: .long asm_default_interrupt -vector134: .long asm_default_interrupt -vector135: .long asm_default_interrupt -vector136: .long asm_default_interrupt -vector137: .long asm_default_interrupt -vector138: .long asm_default_interrupt -vector139: .long asm_default_interrupt -vector140: .long asm_default_interrupt -vector141: .long asm_default_interrupt -vector142: .long asm_default_interrupt -vector143: .long asm_default_interrupt -vector144: .long asm_default_interrupt -vector145: .long asm_default_interrupt -vector146: .long asm_default_interrupt -vector147: .long asm_default_interrupt -vector148: .long asm_default_interrupt -vector149: .long asm_default_interrupt -vector150: .long asm_default_interrupt -vector151: .long asm_default_interrupt -vector152: .long asm_default_interrupt -vector153: .long asm_default_interrupt -vector154: .long asm_default_interrupt -vector155: .long asm_default_interrupt -vector156: .long asm_default_interrupt -vector157: .long asm_default_interrupt -vector158: .long asm_default_interrupt -vector159: .long asm_default_interrupt -vector160: .long asm_default_interrupt -vector161: .long asm_default_interrupt -vector162: .long asm_default_interrupt -vector163: .long asm_default_interrupt -vector164: .long asm_default_interrupt -vector165: .long asm_default_interrupt -vector166: .long asm_default_interrupt -vector167: .long asm_default_interrupt -vector168: .long asm_default_interrupt -vector169: .long asm_default_interrupt -vector170: .long asm_default_interrupt -vector171: .long asm_default_interrupt -vector172: .long asm_default_interrupt -vector173: .long asm_default_interrupt -vector174: .long asm_default_interrupt -vector175: .long asm_default_interrupt -vector176: .long asm_default_interrupt -vector177: .long asm_default_interrupt -vector178: .long asm_default_interrupt -vector179: .long asm_default_interrupt -vector180: .long asm_default_interrupt -vector181: .long asm_default_interrupt -vector182: .long asm_default_interrupt -vector183: .long asm_default_interrupt -vector184: .long asm_default_interrupt -vector185: .long asm_default_interrupt -vector186: .long asm_default_interrupt -vector187: .long asm_default_interrupt -vector188: .long asm_default_interrupt -vector189: .long asm_default_interrupt -vector190: .long asm_default_interrupt -vector191: .long asm_default_interrupt -vector192: .long asm_default_interrupt -vector193: .long asm_default_interrupt -vector194: .long asm_default_interrupt -vector195: .long asm_default_interrupt -vector196: .long asm_default_interrupt -vector197: .long asm_default_interrupt -vector198: .long asm_default_interrupt -vector199: .long asm_default_interrupt -vector200: .long asm_default_interrupt -vector201: .long asm_default_interrupt -vector202: .long asm_default_interrupt -vector203: .long asm_default_interrupt -vector204: .long asm_default_interrupt -vector205: .long asm_default_interrupt -vector206: .long asm_default_interrupt -vector207: .long asm_default_interrupt -vector208: .long asm_default_interrupt -vector209: .long asm_default_interrupt -vector210: .long asm_default_interrupt -vector211: .long asm_default_interrupt -vector212: .long asm_default_interrupt -vector213: .long asm_default_interrupt -vector214: .long asm_default_interrupt -vector215: .long asm_default_interrupt -vector216: .long asm_default_interrupt -vector217: .long asm_default_interrupt -vector218: .long asm_default_interrupt -vector219: .long asm_default_interrupt -vector220: .long asm_default_interrupt -vector221: .long asm_default_interrupt -vector222: .long asm_default_interrupt -vector223: .long asm_default_interrupt -vector224: .long asm_default_interrupt -vector225: .long asm_default_interrupt -vector226: .long asm_default_interrupt -vector227: .long asm_default_interrupt -vector228: .long asm_default_interrupt -vector229: .long asm_default_interrupt -vector230: .long asm_default_interrupt -vector231: .long asm_default_interrupt -vector232: .long asm_default_interrupt -vector233: .long asm_default_interrupt -vector234: .long asm_default_interrupt -vector235: .long asm_default_interrupt -vector236: .long asm_default_interrupt -vector237: .long asm_default_interrupt -vector238: .long asm_default_interrupt -vector239: .long asm_default_interrupt -vector240: .long asm_default_interrupt -vector241: .long asm_default_interrupt -vector242: .long asm_default_interrupt -vector243: .long asm_default_interrupt -vector244: .long asm_default_interrupt -vector245: .long asm_default_interrupt -vector246: .long asm_default_interrupt -vector247: .long asm_default_interrupt -vector248: .long asm_default_interrupt -vector249: .long asm_default_interrupt -vector250: .long asm_default_interrupt -vector251: .long asm_default_interrupt -vector252: .long asm_default_interrupt -vector253: .long asm_default_interrupt -vector254: .long asm_default_interrupt -vector255: .long asm_default_interrupt - -/*===============================================================*\ -| Start of code | -\*===============================================================*/ -.text -PUBLIC (start) -SYM(start): - move.w #0x3700,sr /* disable interrupts */ - jmp start_init - -/*===============================================================*\ -| Sspurious interrupt counter | -\*===============================================================*/ -.align 4 -.data /* begin of data section */ -PUBLIC (spurious_int_count) -SYM(spurious_int_count): - .long 0 /* spurious interrupt counter */ - -/*===============================================================*\ -| Function: Default exception handler | -+-----------------------------------------------------------------+ -| - stop and disable all interrupts | -| - loop forever | -\*===============================================================*/ -.text /* start of text section */ -.align 4 -PUBLIC (asm_default_interrupt) -SYM(asm_default_interrupt): - nop - stop #0x3700 /* stop */ - bra.w asm_default_interrupt /* loop forever */ - -/*===============================================================*\ -| Function: Exception handler for spurious interrupts | -+-----------------------------------------------------------------+ -| - count spurious interrupts | -\*===============================================================*/ -.align 4 -PUBLIC (asm_spurious_interrupt) -SYM(asm_spurious_interrupt): - add.l #1,spurious_int_count - rte - -/*===============================================================*\ -| Function: start_init | -+-----------------------------------------------------------------+ -| - Disable all intterupts | -| - Setup the internal SRAM | -| - Initialize mcf548x peripherals | -| - Set initial stack pointer | -| - Boot RTEMS -\*===============================================================*/ -.align 4 -PUBLIC (start_init) -SYM(start_init): - - move.l #0x01040100,d0 /* invalidate instruction/data/branch cache, disable all caches */ - movec d0,cacr - - move.l #_CoreSramBase0,d0 /* initialize RAMBAR0 */ - add.l #0x21,d0 /* for code & data */ - movec d0,rambar0 - - move.l #_CoreSramBase1,d0 /* initialize RAMBAR1 */ - add.l #0x21,d0 /* for code & data */ - movec d0,rambar1 /* movec d0,RAMBAR1 */ - - move.l #__MBAR,d0 /* initialize MBAR */ - movec d0,mbar - - move.l #_CoreSramBase1,d0 /* set sp to end of Core SRAM temporarily */ - add.l #_CoreSramSize1,d0 - move.l d0,sp - - move.l #0,d0 /* initialize frame pointer */ - movea.l d0,a6 - - jsr mcf548x_init /* Initialize mcf548x peripherals */ - - move.l #bsp_initstack_end,sp /* relocate sp */ - - clrl d0 /* clear d0 */ - movel d0,a7@- /* command line == 0 */ - - jsr boot_card /* boot rtems */ - - movel a7@+,d0 - -exit_multitasking: - nop - nop - halt - bra exit_multitasking - -.end /* end of start.S module */ - - - diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am b/c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am index 465a4f8b53..437ea430c9 100644 --- a/c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am +++ b/c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am @@ -10,7 +10,7 @@ _SUBDIRS = . tools -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5206elite/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/start/start.S b/c/src/lib/libbsp/m68k/mcf5206elite/start/start.S deleted file mode 100644 index 57848ff92b..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5206elite/start/start.S +++ /dev/null @@ -1,415 +0,0 @@ -/* - * MCF5206eLITE startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - */ - -/* - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * Based on work: - * Author: - * David Fiddes, D.J@fiddes.surfaid.org - * http://www.calm.hw.ac.uk/davidf/coldfire/ - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include "bsp.h" - -BEGIN_CODE - -/* Initial stack situated in on-chip static memory */ -#define INITIAL_STACK BSP_MEM_ADDR_SRAM+BSP_MEM_SIZE_SRAM-4 - - PUBLIC (INTERRUPT_VECTOR) -SYM(INTERRUPT_VECTOR): - .long INITIAL_STACK | 00: initial SSP - .long start | 01: Initial PC - .long _unexp_exception | 02: Access Error - .long _unexp_exception | 03: Address Error - .long _unexp_exception | 04: Illegal Instruction - .long _reserved_int | 05: Reserved - .long _reserved_int | 06: Reserved - .long _reserved_int | 07: Reserved - .long _unexp_exception | 08: Priveledge Violation - .long _unexp_exception | 09: Trace - .long _unexp_exception | 0A: Unimplemented A-Line - .long _unexp_exception | 0B: Unimplemented F-Line - .long _unexp_exception | 0C: Debug interrupt - .long _reserved_int | 0D: Reserved - .long _unexp_exception | 0E: Format error - .long _unexp_exception | 0F: Uninitialized interrupt - .long _reserved_int | 10: Reserved - .long _reserved_int | 11: Reserved - .long _reserved_int | 12: Reserved - .long _reserved_int | 13: Reserved - .long _reserved_int | 14: Reserved - .long _reserved_int | 15: Reserved - .long _reserved_int | 16: Reserved - .long _reserved_int | 17: Reserved - .long _spurious_int | 18: Spurious interrupt - .long _avec1_int | 19: Autovector Level 1 - .long _avec2_int | 1A: Autovector Level 2 - .long _avec3_int | 1B: Autovector Level 3 - .long _avec4_int | 1C: Autovector Level 4 - .long _avec5_int | 1D: Autovector Level 5 - .long _avec6_int | 1E: Autovector Level 6 - .long _avec7_int | 1F: Autovector Level 7 - .long _unexp_exception | 20: TRAP #0 - .long _unexp_exception | 21: TRAP #1 - .long _unexp_exception | 22: TRAP #2 - .long _unexp_exception | 23: TRAP #3 - .long _unexp_exception | 24: TRAP #4 - .long _unexp_exception | 25: TRAP #5 - .long _unexp_exception | 26: TRAP #6 - .long _unexp_exception | 27: TRAP #7 - .long _unexp_exception | 28: TRAP #8 - .long _unexp_exception | 29: TRAP #9 - .long _unexp_exception | 2A: TRAP #10 - .long _unexp_exception | 2B: TRAP #11 - .long _unexp_exception | 2C: TRAP #12 - .long _unexp_exception | 2D: TRAP #13 - .long _unexp_exception | 2E: TRAP #14 - .long _unexp_exception | 2F: TRAP #15 - .long _reserved_int | 30: Reserved - .long _reserved_int | 31: Reserved - .long _reserved_int | 32: Reserved - .long _reserved_int | 33: Reserved - .long _reserved_int | 34: Reserved - .long _reserved_int | 35: Reserved - .long _reserved_int | 36: Reserved - .long _reserved_int | 37: Reserved - .long _reserved_int | 38: Reserved - .long _reserved_int | 39: Reserved - .long _reserved_int | 3A: Reserved - .long _reserved_int | 3B: Reserved - .long _reserved_int | 3C: Reserved - .long _reserved_int | 3D: Reserved - .long _reserved_int | 3E: Reserved - .long _reserved_int | 3F: Reserved - - .long _unexp_int | 40-FF: User defined interrupts - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 50: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 60: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 70: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 80: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | 90: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | A0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | B0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | C0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | D0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | E0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - .long _unexp_int | F0: - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - .long _unexp_int - - PUBLIC(start) -SYM(start): - move.w #0x2700,sr | First turn off all interrupts! - - move.l #(BSP_MEM_ADDR_SRAM + MCF5206E_RAMBAR_V),d0 - movec d0,rambar0 | ...so we have a stack - - move.l #(INITIAL_STACK),sp | Set up stack again (may be we are - | going here from monitor or with - | BDM interface assistance) - - /* - * Remainder of the startup code is handled by C code - */ - jmp SYM(Init5206e) | Start C code (which never returns) - -/*************************************************************************** - Function : CopyDataClearBSSAndStart - - Description : Copy DATA segment, clear BSS segment, initialize heap, - initialise real stack, start C program. Assume that DATA and BSS sizes - are multiples of 4. - ***************************************************************************/ - PUBLIC (CopyDataClearBSSAndStart) -SYM(CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - move 4(a7),d0 - - /* - * Right : Now we're ready to boot RTEMS - */ - clrl d0 | Pass in null to all boot_card() params - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C boot_card function to startup RTEMS - -# Wait forever -_stop: - nop - stop #0x2700 - jmp _stop - -# The following labelled nops is a placeholders for breakpoints -_unexp_exception: - nop - jmp _stop - -_unexp_int: - nop - jmp _stop - -_reserved_int: - nop - jmp _stop - -_spurious_int: - nop - jmp _stop - -_avec1_int: - nop - jmp _unexp_int - -_avec2_int: - nop - jmp _unexp_int - -_avec3_int: - nop - jmp _unexp_int - -_avec4_int: - nop - jmp _unexp_int - -_avec5_int: - nop - jmp _unexp_int - -_avec6_int: - nop - jmp _unexp_int - -_avec7_int: - nop - jmp _unexp_int - -END_CODE - -END diff --git a/c/src/lib/libbsp/m68k/mcf52235/Makefile.am b/c/src/lib/libbsp/m68k/mcf52235/Makefile.am index c9138f2d66..49e66b59ca 100644 --- a/c/src/lib/libbsp/m68k/mcf52235/Makefile.am +++ b/c/src/lib/libbsp/m68k/mcf52235/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/mcf52235/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mcf52235/start/start.S b/c/src/lib/libbsp/m68k/mcf52235/start/start.S deleted file mode 100644 index e1d837cab5..0000000000 --- a/c/src/lib/libbsp/m68k/mcf52235/start/start.S +++ /dev/null @@ -1,449 +0,0 @@ -/* - * mcf52235 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -.extern _StackInit - -BEGIN_CODE - - PUBLIC (_INTERRUPT_VECTOR) -SYM(_INTERRUPT_VECTOR): - - .long _StackInit /* 00 Initial 'SSP' */ - .long SYM(start) /* 01 Initial PC */ - .long SYM(_uhoh) /* 02 Access Error */ - .long SYM(_uhoh) /* 03 Address Error */ - .long SYM(_uhoh) /* 04 Illegal Instruction */ - .long SYM(_uhoh) /* 05 Divide by Zero */ - .long SYM(_uhoh) /* 06 Reserved */ - .long SYM(_uhoh) /* 07 Reserved */ - .long SYM(_uhoh) /* 08 Privilege Violation */ - .long SYM(_uhoh) /* 09 Trace */ - .long SYM(_uhoh) /* 10 Unimplemented A-Line */ - .long SYM(_uhoh) /* 11 Unimplemented F-Line */ - .long SYM(_uhoh) /* 12 Debug Interrupt */ - .long SYM(_uhoh) /* 13 Reserved */ - .long SYM(_uhoh) /* 14 Format Error */ - .long SYM(_uhoh) /* 15 Reserved */ - .long SYM(_uhoh) /* 16 Reserved */ - .long SYM(_uhoh) /* 17 Reserved */ - .long SYM(_uhoh) /* 18 Reserved */ - .long SYM(_uhoh) /* 19 Reserved */ - .long SYM(_uhoh) /* 20 Reserved */ - .long SYM(_uhoh) /* 21 Reserved */ - .long SYM(_uhoh) /* 22 Reserved */ - .long SYM(_uhoh) /* 23 Reserved */ - .long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */ - .long SYM(_uhoh) /* 25 Reserved */ - .long SYM(_uhoh) /* 26 Reserved */ - .long SYM(_uhoh) /* 27 Reserved */ - .long SYM(_uhoh) /* 28 Reserved */ - .long SYM(_uhoh) /* 29 Reserved */ - .long SYM(_uhoh) /* 30 Reserved */ - .long SYM(_uhoh) /* 31 Reserved */ - .long SYM(_uhoh) /* 32 TRAP #0 */ - .long SYM(_uhoh) /* 33 TRAP #1 */ - .long SYM(_uhoh) /* 34 TRAP #2 */ - .long SYM(_uhoh) /* 35 TRAP #3 */ - .long SYM(_uhoh) /* 36 TRAP #4 */ - .long SYM(_uhoh) /* 37 TRAP #5 */ - .long SYM(_uhoh) /* 38 TRAP #6 */ - .long SYM(_uhoh) /* 39 TRAP #7 */ - .long SYM(_uhoh) /* 40 TRAP #8 */ - .long SYM(_uhoh) /* 41 TRAP #9 */ - .long SYM(_uhoh) /* 42 TRAP #10 */ - .long SYM(_uhoh) /* 43 TRAP #11 */ - .long SYM(_uhoh) /* 44 TRAP #12 */ - .long SYM(_uhoh) /* 45 TRAP #13 */ - .long SYM(_uhoh) /* 46 TRAP #14 */ - .long SYM(_uhoh) /* 47 TRAP #15 */ - .long SYM(_uhoh) /* 48 Reserved */ - .long SYM(_uhoh) /* 49 Reserved */ - .long SYM(_uhoh) /* 50 Reserved */ - .long SYM(_uhoh) /* 51 Reserved */ - .long SYM(_uhoh) /* 52 Reserved */ - .long SYM(_uhoh) /* 53 Reserved */ - .long SYM(_uhoh) /* 54 Reserved */ - .long SYM(_uhoh) /* 55 Reserved */ - .long SYM(_uhoh) /* 56 Reserved */ - .long SYM(_uhoh) /* 57 Reserved */ - .long SYM(_uhoh) /* 58 Reserved */ - .long SYM(_uhoh) /* 59 Reserved */ - .long SYM(_uhoh) /* 60 Reserved */ - .long SYM(_uhoh) /* 61 Reserved */ - .long SYM(_uhoh) /* 62 Reserved */ - .long SYM(_uhoh) /* 63 Reserved */ - - /* INTC0 */ - - .long SYM(_uhoh) /* 64*/ - .long SYM(_uhoh) /* 65*/ - .long SYM(_uhoh) /* 66*/ - .long SYM(_uhoh) /* 67*/ - .long SYM(_uhoh) /* 68*/ - .long SYM(_uhoh) /* 69*/ - .long SYM(_uhoh) /* 70*/ - .long SYM(_uhoh) /* 71*/ - .long SYM(_uhoh) /* 72*/ - .long SYM(_uhoh) /* 73*/ - .long SYM(_uhoh) /* 74*/ - .long SYM(_uhoh) /* 75*/ - .long SYM(_uhoh) /* 76*/ - .long SYM(_uhoh) /* 77*/ - .long SYM(_uhoh) /* 78*/ - .long SYM(_uhoh) /* 79*/ - .long SYM(_uhoh) /* 80*/ - .long SYM(_uhoh) /* 81*/ - .long SYM(_uhoh) /* 82*/ - .long SYM(_uhoh) /* 83*/ - .long SYM(_uhoh) /* 84*/ - .long SYM(_uhoh) /* 85*/ - .long SYM(_uhoh) /* 86*/ - .long SYM(_uhoh) /* 87*/ - .long SYM(_uhoh) /* 88*/ - .long SYM(_uhoh) /* 89*/ - .long SYM(_uhoh) /* 90*/ - .long SYM(_uhoh) /* 91*/ - .long SYM(_uhoh) /* 92*/ - .long SYM(_uhoh) /* 93*/ - .long SYM(_uhoh) /* 94*/ - .long SYM(_uhoh) /* 95*/ - .long SYM(_uhoh) /* 96*/ - .long SYM(_uhoh) /* 97*/ - .long SYM(_uhoh) /* 98*/ - .long SYM(_uhoh) /* 99*/ - .long SYM(_uhoh) /* 100*/ - .long SYM(_uhoh) /* 101*/ - .long SYM(_uhoh) /* 102*/ - .long SYM(_uhoh) /* 103*/ - .long SYM(_uhoh) /* 104*/ - .long SYM(_uhoh) /* 105*/ - .long SYM(_uhoh) /* 106*/ - .long SYM(_uhoh) /* 107*/ - .long SYM(_uhoh) /* 108*/ - .long SYM(_uhoh) /* 109*/ - .long SYM(_uhoh) /* 110*/ - .long SYM(_uhoh) /* 111*/ - .long SYM(_uhoh) /* 112*/ - .long SYM(_uhoh) /* 113*/ - .long SYM(_uhoh) /* 114*/ - .long SYM(_uhoh) /* 115*/ - .long SYM(_uhoh) /* 116*/ - .long SYM(_uhoh) /* 117*/ - .long SYM(_uhoh) /* 118*/ - .long SYM(_uhoh) /* 119*/ - .long SYM(_uhoh) /* 120*/ - .long SYM(_uhoh) /* 121*/ - .long SYM(_uhoh) /* 122*/ - .long SYM(_uhoh) /* 123*/ - .long SYM(_uhoh) /* 124*/ - .long SYM(_uhoh) /* 125*/ - .long SYM(_uhoh) /* 126*/ - .long SYM(_uhoh) /* 127*/ - - /* INTC1 */ - - .long SYM(_uhoh) /* 128*/ - .long SYM(_uhoh) /* 129*/ - .long SYM(_uhoh) /* 130*/ - .long SYM(_uhoh) /* 131*/ - .long SYM(_uhoh) /* 132*/ - .long SYM(_uhoh) /* 133*/ - .long SYM(_uhoh) /* 134*/ - .long SYM(_uhoh) /* 135*/ - .long SYM(_uhoh) /* 136*/ - .long SYM(_uhoh) /* 137*/ - .long SYM(_uhoh) /* 138*/ - .long SYM(_uhoh) /* 139*/ - .long SYM(_uhoh) /* 140*/ - .long SYM(_uhoh) /* 141*/ - .long SYM(_uhoh) /* 142*/ - .long SYM(_uhoh) /* 143*/ - .long SYM(_uhoh) /* 144*/ - .long SYM(_uhoh) /* 145*/ - .long SYM(_uhoh) /* 146*/ - .long SYM(_uhoh) /* 147*/ - .long SYM(_uhoh) /* 148*/ - .long SYM(_uhoh) /* 149*/ - .long SYM(_uhoh) /* 150*/ - .long SYM(_uhoh) /* 151*/ - .long SYM(_uhoh) /* 152*/ - .long SYM(_uhoh) /* 153*/ - .long SYM(_uhoh) /* 154*/ - .long SYM(_uhoh) /* 155*/ - .long SYM(_uhoh) /* 156*/ - .long SYM(_uhoh) /* 157*/ - .long SYM(_uhoh) /* 158*/ - .long SYM(_uhoh) /* 159*/ - .long SYM(_uhoh) /* 160*/ - .long SYM(_uhoh) /* 161*/ - .long SYM(_uhoh) /* 162*/ - .long SYM(_uhoh) /* 163*/ - .long SYM(_uhoh) /* 164*/ - .long SYM(_uhoh) /* 165*/ - .long SYM(_uhoh) /* 166*/ - .long SYM(_uhoh) /* 167*/ - .long SYM(_uhoh) /* 168*/ - .long SYM(_uhoh) /* 169*/ - .long SYM(_uhoh) /* 170*/ - .long SYM(_uhoh) /* 171*/ - .long SYM(_uhoh) /* 172*/ - .long SYM(_uhoh) /* 173*/ - .long SYM(_uhoh) /* 174*/ - .long SYM(_uhoh) /* 175*/ - .long SYM(_uhoh) /* 176*/ - .long SYM(_uhoh) /* 177*/ - .long SYM(_uhoh) /* 178*/ - .long SYM(_uhoh) /* 179*/ - .long SYM(_uhoh) /* 180*/ - .long SYM(_uhoh) /* 181*/ - .long SYM(_uhoh) /* 182*/ - .long SYM(_uhoh) /* 183*/ - .long SYM(_uhoh) /* 184*/ - .long SYM(_uhoh) /* 185*/ - .long SYM(_uhoh) /* 186*/ - .long SYM(_uhoh) /* 187*/ - .long SYM(_uhoh) /* 188*/ - .long SYM(_uhoh) /* 189*/ - .long SYM(_uhoh) /* 190*/ - .long SYM(_uhoh) /* 191*/ - .long SYM(_uhoh) /* 192*/ - - /* */ - - .long SYM(_uhoh) /* 193*/ - .long SYM(_uhoh) /* 194*/ - .long SYM(_uhoh) /* 195*/ - .long SYM(_uhoh) /* 196*/ - .long SYM(_uhoh) /* 197*/ - .long SYM(_uhoh) /* 198*/ - .long SYM(_uhoh) /* 199*/ - .long SYM(_uhoh) /* 200*/ - .long SYM(_uhoh) /* 201*/ - .long SYM(_uhoh) /* 202*/ - .long SYM(_uhoh) /* 203*/ - .long SYM(_uhoh) /* 204*/ - .long SYM(_uhoh) /* 205*/ - .long SYM(_uhoh) /* 206*/ - .long SYM(_uhoh) /* 207*/ - .long SYM(_uhoh) /* 208*/ - .long SYM(_uhoh) /* 209*/ - .long SYM(_uhoh) /* 210*/ - .long SYM(_uhoh) /* 211*/ - .long SYM(_uhoh) /* 212*/ - .long SYM(_uhoh) /* 213*/ - .long SYM(_uhoh) /* 214*/ - .long SYM(_uhoh) /* 215*/ - .long SYM(_uhoh) /* 216*/ - .long SYM(_uhoh) /* 217*/ - .long SYM(_uhoh) /* 218*/ - .long SYM(_uhoh) /* 219*/ - .long SYM(_uhoh) /* 220*/ - .long SYM(_uhoh) /* 221*/ - .long SYM(_uhoh) /* 222*/ - .long SYM(_uhoh) /* 223*/ - .long SYM(_uhoh) /* 224*/ - .long SYM(_uhoh) /* 225*/ - .long SYM(_uhoh) /* 226*/ - .long SYM(_uhoh) /* 227*/ - .long SYM(_uhoh) /* 228*/ - .long SYM(_uhoh) /* 229*/ - .long SYM(_uhoh) /* 230*/ - .long SYM(_uhoh) /* 231*/ - .long SYM(_uhoh) /* 232*/ - .long SYM(_uhoh) /* 233*/ - .long SYM(_uhoh) /* 234*/ - .long SYM(_uhoh) /* 235*/ - .long SYM(_uhoh) /* 236*/ - .long SYM(_uhoh) /* 237*/ - .long SYM(_uhoh) /* 238*/ - .long SYM(_uhoh) /* 239*/ - .long SYM(_uhoh) /* 240*/ - .long SYM(_uhoh) /* 241*/ - .long SYM(_uhoh) /* 242*/ - .long SYM(_uhoh) /* 243*/ - .long SYM(_uhoh) /* 244*/ - .long SYM(_uhoh) /* 245*/ - .long SYM(_uhoh) /* 246*/ - .long SYM(_uhoh) /* 247*/ - .long SYM(_uhoh) /* 248*/ - .long SYM(_uhoh) /* 249*/ - .long SYM(_uhoh) /* 250*/ - .long SYM(_uhoh) /* 251*/ - .long SYM(_uhoh) /* 252*/ - .long SYM(_uhoh) /* 253*/ - .long SYM(_uhoh) /* 254*/ - .long SYM(_uhoh) /* 255*/ - -/* - * We must write the flash configuration here. This portion of flash is shadowed - * by some flash registers, so we can't put code here! - */ - - PUBLIC (_FLASH_CONFIGURATION_FIELD) -SYM(_FLASH_CONFIGURATION_FIELD): - -_key_upper: .long 0x00000000 -_key_lower: .long 0x00000000 -_cfm_prot: .long 0x00000000 -_cfm_sacc: .long 0x00000000 -_cfm_dacc: .long 0x00000000 -_cfm_msec: .long 0x00000000 - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -/* - * Spurious Interrupt Handler - */ -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1, SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Write VBR Register - */ -.align 4 - PUBLIC (_wr_vbr) -SYM(_wr_vbr): - move.l 4(sp), d0 - movec d0, vbr - nop - rts - -/* - * Board startup - * Disable watchdog, interrupts - * Enable sram - */ -.align 4 - PUBLIC (start) -SYM(start): - - /* Mask off interupts */ - move.w #0x2700, sr - - /* Save off reset values of D0 and D1 */ - move.l d0, d6 - move.l d1, d7 - - /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #RamBase, d0 - add.l #0x21, d0 - movec d0, %rambar - - /* Locate Stack Pointer */ - move.l #_StackInit, sp - - /* Initialize FLASHBAR */ - move.l #_FlashBase, d0 - cmp.l #0x00000000, d0 - bne _change_flashbar - add.l #0x61, d0 - movec d0, %flashbar - -_continue_startup: - - /* Locate Stack Pointer */ - move.l #_StackInit, sp - - /* Save off intial D0 and D1 to RAM */ - move.l d6, SYM(_d0_reset) - move.l d7, SYM(_d1_reset) - - /* - * Remainder of the startup code is handled by C code - * This never returns - */ - jmp SYM(Init52235) - -_change_flashbar: - /* - * The following sequence is used to set FLASHBAR. Since we may - * be executing from Flash, we must put the routine into SRAM for - * execution and then jump back to Flash using the new address. - * - * The following instructions are coded into the SRAM: - * - * move.l #(__FLASH + 0x61),d0 - * movec d0, FLASHBAR - * jmp _continue_startup - * - * An arbitrary SRAM address is chosen until the real address - * can be loaded. - * - * This routine is not necessary if the default Flash address - * (0x00000000) is used. - * - * If running in SRAM, change_flashbar should not be executed - */ - - move.l #RamBase, a0 - - /* Code "move.l #(__FLASH + 0x61),d0" into SRAM */ - move.w #0x203C, d0 - move.w d0, (a0)+ - move.l #_FlashBase, d0 - add.l #0x61, d0 - move.l d0, (a0)+ - - /* Code "movec d0,FLASHBAR" into SRAM */ - move.l #0x4e7b0C04, d0 - move.l d0, (a0)+ - - /* Code "jmp _continue_startup" into SRAM */ - move.w #0x4EF9, d0 - move.w d0, (a0)+ - move.l #_continue_startup, d0 - move.l d0, (a0)+ - - /* Jump to code segment in internal SRAM */ - jmp RamBase - -END_CODE - - -BEGIN_DATA_DCL - - .align 4 - -PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 - -PUBLIC (_d0_reset) -SYM (_d0_reset): - .long 0 - -PUBLIC (_d1_reset) -SYM (_d1_reset): - .long 0 - -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/mcf5225x/Makefile.am b/c/src/lib/libbsp/m68k/mcf5225x/Makefile.am index f93dd98d5f..c269671497 100644 --- a/c/src/lib/libbsp/m68k/mcf5225x/Makefile.am +++ b/c/src/lib/libbsp/m68k/mcf5225x/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5225x/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mcf5225x/start/start.S b/c/src/lib/libbsp/m68k/mcf5225x/start/start.S deleted file mode 100644 index abc7bb99cc..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5225x/start/start.S +++ /dev/null @@ -1,450 +0,0 @@ -/* - * dpu-mcf52258 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -.extern _StackInit - -BEGIN_CODE - - PUBLIC (_INTERRUPT_VECTOR) -SYM(_INTERRUPT_VECTOR): - - .long _StackInit /* 00 Initial 'SSP' */ - .long SYM(start) /* 01 Initial PC */ - .long SYM(_uhoh) /* 02 Access Error */ - .long SYM(_uhoh) /* 03 Address Error */ - .long SYM(_uhoh) /* 04 Illegal Instruction */ - .long SYM(_uhoh) /* 05 Divide by Zero */ - .long SYM(_uhoh) /* 06 Reserved */ - .long SYM(_uhoh) /* 07 Reserved */ - .long SYM(_uhoh) /* 08 Privilege Violation */ - .long SYM(_uhoh) /* 09 Trace */ - .long SYM(_uhoh) /* 10 Unimplemented A-Line */ - .long SYM(_uhoh) /* 11 Unimplemented F-Line */ - .long SYM(_uhoh) /* 12 Debug Interrupt */ - .long SYM(_uhoh) /* 13 Reserved */ - .long SYM(_uhoh) /* 14 Format Error */ - .long SYM(_uhoh) /* 15 Reserved */ - .long SYM(_uhoh) /* 16 Reserved */ - .long SYM(_uhoh) /* 17 Reserved */ - .long SYM(_uhoh) /* 18 Reserved */ - .long SYM(_uhoh) /* 19 Reserved */ - .long SYM(_uhoh) /* 20 Reserved */ - .long SYM(_uhoh) /* 21 Reserved */ - .long SYM(_uhoh) /* 22 Reserved */ - .long SYM(_uhoh) /* 23 Reserved */ - .long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */ - .long SYM(_uhoh) /* 25 Reserved */ - .long SYM(_uhoh) /* 26 Reserved */ - .long SYM(_uhoh) /* 27 Reserved */ - .long SYM(_uhoh) /* 28 Reserved */ - .long SYM(_uhoh) /* 29 Reserved */ - .long SYM(_uhoh) /* 30 Reserved */ - .long SYM(_uhoh) /* 31 Reserved */ - .long SYM(_uhoh) /* 32 TRAP #0 */ - .long SYM(_uhoh) /* 33 TRAP #1 */ - .long SYM(_uhoh) /* 34 TRAP #2 */ - .long SYM(_uhoh) /* 35 TRAP #3 */ - .long SYM(_uhoh) /* 36 TRAP #4 */ - .long SYM(_uhoh) /* 37 TRAP #5 */ - .long SYM(_uhoh) /* 38 TRAP #6 */ - .long SYM(_uhoh) /* 39 TRAP #7 */ - .long SYM(_uhoh) /* 40 TRAP #8 */ - .long SYM(_uhoh) /* 41 TRAP #9 */ - .long SYM(_uhoh) /* 42 TRAP #10 */ - .long SYM(_uhoh) /* 43 TRAP #11 */ - .long SYM(_uhoh) /* 44 TRAP #12 */ - .long SYM(_uhoh) /* 45 TRAP #13 */ - .long SYM(_uhoh) /* 46 TRAP #14 */ - .long SYM(_uhoh) /* 47 TRAP #15 */ - .long SYM(_uhoh) /* 48 Reserved */ - .long SYM(_uhoh) /* 49 Reserved */ - .long SYM(_uhoh) /* 50 Reserved */ - .long SYM(_uhoh) /* 51 Reserved */ - .long SYM(_uhoh) /* 52 Reserved */ - .long SYM(_uhoh) /* 53 Reserved */ - .long SYM(_uhoh) /* 54 Reserved */ - .long SYM(_uhoh) /* 55 Reserved */ - .long SYM(_uhoh) /* 56 Reserved */ - .long SYM(_uhoh) /* 57 Reserved */ - .long SYM(_uhoh) /* 58 Reserved */ - .long SYM(_uhoh) /* 59 Reserved */ - .long SYM(_uhoh) /* 60 Reserved */ - .long SYM(_uhoh) /* 61 Reserved */ - .long SYM(_uhoh) /* 62 Reserved */ - .long SYM(_uhoh) /* 63 Reserved */ - - /* INTC0 */ - - .long SYM(_uhoh) /* 64*/ - .long SYM(_uhoh) /* 65*/ - .long SYM(_uhoh) /* 66*/ - .long SYM(_uhoh) /* 67*/ - .long SYM(_uhoh) /* 68*/ - .long SYM(_uhoh) /* 69*/ - .long SYM(_uhoh) /* 70*/ - .long SYM(_uhoh) /* 71*/ - .long SYM(_uhoh) /* 72*/ - .long SYM(_uhoh) /* 73*/ - .long SYM(_uhoh) /* 74*/ - .long SYM(_uhoh) /* 75*/ - .long SYM(_uhoh) /* 76*/ - .long SYM(_uhoh) /* 77*/ - .long SYM(_uhoh) /* 78*/ - .long SYM(_uhoh) /* 79*/ - .long SYM(_uhoh) /* 80*/ - .long SYM(_uhoh) /* 81*/ - .long SYM(_uhoh) /* 82*/ - .long SYM(_uhoh) /* 83*/ - .long SYM(_uhoh) /* 84*/ - .long SYM(_uhoh) /* 85*/ - .long SYM(_uhoh) /* 86*/ - .long SYM(_uhoh) /* 87*/ - .long SYM(_uhoh) /* 88*/ - .long SYM(_uhoh) /* 89*/ - .long SYM(_uhoh) /* 90*/ - .long SYM(_uhoh) /* 91*/ - .long SYM(_uhoh) /* 92*/ - .long SYM(_uhoh) /* 93*/ - .long SYM(_uhoh) /* 94*/ - .long SYM(_uhoh) /* 95*/ - .long SYM(_uhoh) /* 96*/ - .long SYM(_uhoh) /* 97*/ - .long SYM(_uhoh) /* 98*/ - .long SYM(_uhoh) /* 99*/ - .long SYM(_uhoh) /* 100*/ - .long SYM(_uhoh) /* 101*/ - .long SYM(_uhoh) /* 102*/ - .long SYM(_uhoh) /* 103*/ - .long SYM(_uhoh) /* 104*/ - .long SYM(_uhoh) /* 105*/ - .long SYM(_uhoh) /* 106*/ - .long SYM(_uhoh) /* 107*/ - .long SYM(_uhoh) /* 108*/ - .long SYM(_uhoh) /* 109*/ - .long SYM(_uhoh) /* 110*/ - .long SYM(_uhoh) /* 111*/ - .long SYM(_uhoh) /* 112*/ - .long SYM(_uhoh) /* 113*/ - .long SYM(_uhoh) /* 114*/ - .long SYM(_uhoh) /* 115*/ - .long SYM(_uhoh) /* 116*/ - .long SYM(_uhoh) /* 117*/ - .long SYM(_uhoh) /* 118*/ - .long SYM(_uhoh) /* 119*/ - .long SYM(_uhoh) /* 120*/ - .long SYM(_uhoh) /* 121*/ - .long SYM(_uhoh) /* 122*/ - .long SYM(_uhoh) /* 123*/ - .long SYM(_uhoh) /* 124*/ - .long SYM(_uhoh) /* 125*/ - .long SYM(_uhoh) /* 126*/ - .long SYM(_uhoh) /* 127*/ - - /* INTC1 */ - - .long SYM(_uhoh) /* 128*/ - .long SYM(_uhoh) /* 129*/ - .long SYM(_uhoh) /* 130*/ - .long SYM(_uhoh) /* 131*/ - .long SYM(_uhoh) /* 132*/ - .long SYM(_uhoh) /* 133*/ - .long SYM(_uhoh) /* 134*/ - .long SYM(_uhoh) /* 135*/ - .long SYM(_uhoh) /* 136*/ - .long SYM(_uhoh) /* 137*/ - .long SYM(_uhoh) /* 138*/ - .long SYM(_uhoh) /* 139*/ - .long SYM(_uhoh) /* 140*/ - .long SYM(_uhoh) /* 141*/ - .long SYM(_uhoh) /* 142*/ - .long SYM(_uhoh) /* 143*/ - .long SYM(_uhoh) /* 144*/ - .long SYM(_uhoh) /* 145*/ - .long SYM(_uhoh) /* 146*/ - .long SYM(_uhoh) /* 147*/ - .long SYM(_uhoh) /* 148*/ - .long SYM(_uhoh) /* 149*/ - .long SYM(_uhoh) /* 150*/ - .long SYM(_uhoh) /* 151*/ - .long SYM(_uhoh) /* 152*/ - .long SYM(_uhoh) /* 153*/ - .long SYM(_uhoh) /* 154*/ - .long SYM(_uhoh) /* 155*/ - .long SYM(_uhoh) /* 156*/ - .long SYM(_uhoh) /* 157*/ - .long SYM(_uhoh) /* 158*/ - .long SYM(_uhoh) /* 159*/ - .long SYM(_uhoh) /* 160*/ - .long SYM(_uhoh) /* 161*/ - .long SYM(_uhoh) /* 162*/ - .long SYM(_uhoh) /* 163*/ - .long SYM(_uhoh) /* 164*/ - .long SYM(_uhoh) /* 165*/ - .long SYM(_uhoh) /* 166*/ - .long SYM(_uhoh) /* 167*/ - .long SYM(_uhoh) /* 168*/ - .long SYM(_uhoh) /* 169*/ - .long SYM(_uhoh) /* 170*/ - .long SYM(_uhoh) /* 171*/ - .long SYM(_uhoh) /* 172*/ - .long SYM(_uhoh) /* 173*/ - .long SYM(_uhoh) /* 174*/ - .long SYM(_uhoh) /* 175*/ - .long SYM(_uhoh) /* 176*/ - .long SYM(_uhoh) /* 177*/ - .long SYM(_uhoh) /* 178*/ - .long SYM(_uhoh) /* 179*/ - .long SYM(_uhoh) /* 180*/ - .long SYM(_uhoh) /* 181*/ - .long SYM(_uhoh) /* 182*/ - .long SYM(_uhoh) /* 183*/ - .long SYM(_uhoh) /* 184*/ - .long SYM(_uhoh) /* 185*/ - .long SYM(_uhoh) /* 186*/ - .long SYM(_uhoh) /* 187*/ - .long SYM(_uhoh) /* 188*/ - .long SYM(_uhoh) /* 189*/ - .long SYM(_uhoh) /* 190*/ - .long SYM(_uhoh) /* 191*/ - .long SYM(_uhoh) /* 192*/ - - /* */ - - .long SYM(_uhoh) /* 193*/ - .long SYM(_uhoh) /* 194*/ - .long SYM(_uhoh) /* 195*/ - .long SYM(_uhoh) /* 196*/ - .long SYM(_uhoh) /* 197*/ - .long SYM(_uhoh) /* 198*/ - .long SYM(_uhoh) /* 199*/ - .long SYM(_uhoh) /* 200*/ - .long SYM(_uhoh) /* 201*/ - .long SYM(_uhoh) /* 202*/ - .long SYM(_uhoh) /* 203*/ - .long SYM(_uhoh) /* 204*/ - .long SYM(_uhoh) /* 205*/ - .long SYM(_uhoh) /* 206*/ - .long SYM(_uhoh) /* 207*/ - .long SYM(_uhoh) /* 208*/ - .long SYM(_uhoh) /* 209*/ - .long SYM(_uhoh) /* 210*/ - .long SYM(_uhoh) /* 211*/ - .long SYM(_uhoh) /* 212*/ - .long SYM(_uhoh) /* 213*/ - .long SYM(_uhoh) /* 214*/ - .long SYM(_uhoh) /* 215*/ - .long SYM(_uhoh) /* 216*/ - .long SYM(_uhoh) /* 217*/ - .long SYM(_uhoh) /* 218*/ - .long SYM(_uhoh) /* 219*/ - .long SYM(_uhoh) /* 220*/ - .long SYM(_uhoh) /* 221*/ - .long SYM(_uhoh) /* 222*/ - .long SYM(_uhoh) /* 223*/ - .long SYM(_uhoh) /* 224*/ - .long SYM(_uhoh) /* 225*/ - .long SYM(_uhoh) /* 226*/ - .long SYM(_uhoh) /* 227*/ - .long SYM(_uhoh) /* 228*/ - .long SYM(_uhoh) /* 229*/ - .long SYM(_uhoh) /* 230*/ - .long SYM(_uhoh) /* 231*/ - .long SYM(_uhoh) /* 232*/ - .long SYM(_uhoh) /* 233*/ - .long SYM(_uhoh) /* 234*/ - .long SYM(_uhoh) /* 235*/ - .long SYM(_uhoh) /* 236*/ - .long SYM(_uhoh) /* 237*/ - .long SYM(_uhoh) /* 238*/ - .long SYM(_uhoh) /* 239*/ - .long SYM(_uhoh) /* 240*/ - .long SYM(_uhoh) /* 241*/ - .long SYM(_uhoh) /* 242*/ - .long SYM(_uhoh) /* 243*/ - .long SYM(_uhoh) /* 244*/ - .long SYM(_uhoh) /* 245*/ - .long SYM(_uhoh) /* 246*/ - .long SYM(_uhoh) /* 247*/ - .long SYM(_uhoh) /* 248*/ - .long SYM(_uhoh) /* 249*/ - .long SYM(_uhoh) /* 250*/ - .long SYM(_uhoh) /* 251*/ - .long SYM(_uhoh) /* 252*/ - .long SYM(_uhoh) /* 253*/ - .long SYM(_uhoh) /* 254*/ - .long SYM(_uhoh) /* 255*/ - -/* - * We must write the flash configuration here. - This portion of RAM is shadowed - * by some flash registers, so we can't put code here! - */ - - PUBLIC (_FLASH_CONFIGURATION_FIELD) -SYM(_FLASH_CONFIGURATION_FIELD): - -_key_upper: .long 0x5a5a5a5a -_key_lower: .long 0x5a5a5a5a -_cfm_prot: .long 0x00000000 -_cfm_sacc: .long 0x00000000 -_cfm_dacc: .long 0x00000000 -_cfm_msec: .long 0x80000000 //enable the KEYEN bit to bypass security in backdoor mode - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -/* - * Spurious Interrupt Handler - */ -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1, SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Write VBR Register - */ - -/* -.align 4 - PUBLIC (_wr_vbr) -SYM(_wr_vbr): - move.l 4(sp), d0 - movec d0, vbr - nop - rts -*/ - -/* - * Board startup - * Disable watchdog, interrupts - * Enable sram - */ -.align 4 - PUBLIC (start) -SYM(start): - - /* Mask off interupts */ - move.w #0x2700, sr - - /* Save off intial D0 and D1 to NOT scratched registers conforming to ABI C calling convention */ - move.l d0,d5; - move.l d1,d6; - - /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #RamBase, d7 - add.l #0x21, d7 - movec d7, %rambar - - /* Locate Stack Pointer */ - move.l #_StackInit, sp - - /* Initialize FLASHBAR */ - move.l #_FlashBase, d7 - cmp.l #0x00000000, d7 - bne _change_flashbar - add.l #0x61, d7 - movec d7, %flashbar - -_continue_startup: - - /* Locate Stack Pointer */ -// move.l #_StackInit, sp //is done automatically by the CPU - - /* - * Remainder of the startup code is handled by C code - * This never returns - */ - - jmp SYM(Init5225x) - -_change_flashbar: - /* - * The following sequence is used to set FLASHBAR. Since we may - * be executing from Flash, we must put the routine into SRAM for - * execution and then jump back to Flash using the new address. - * - * The following instructions are coded into the SRAM: - * - * move.l #(__FLASH + 0x61),d0 - * movec d0, FLASHBAR - * jmp _continue_startup - * - * An arbitrary SRAM address is chosen until the real address - * can be loaded. - * - * This routine is not necessary if the default Flash address - * (0x00000000) is used. - * - * If running in SRAM, change_flashbar should not be executed - */ - - move.l #RamBase, a0 - - /* Code "move.l #(__FLASH + 0x61),d0" into SRAM */ - move.w #0x203C, d0 - move.w d0, (a0)+ - move.l #_FlashBase, d0 - add.l #0x61, d0 - move.l d0, (a0)+ - - /* Code "movec d0,FLASHBAR" into SRAM */ - move.l #0x4e7b0C04, d0 - move.l d0, (a0)+ - - /* Code "jmp _continue_startup" into SRAM */ - move.w #0x4EF9, d0 - move.w d0, (a0)+ - move.l #_continue_startup, d0 - move.l d0, (a0)+ - - /* Jump to code segment in internal SRAM */ - jmp RamBase - -END_CODE - - -BEGIN_DATA_DCL - - .align 4 - -PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 - -PUBLIC (_d0_reset) -SYM (_d0_reset): - .long 0 - -PUBLIC (_d1_reset) -SYM (_d1_reset): - .long 0 - -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/mcf5235/Makefile.am b/c/src/lib/libbsp/m68k/mcf5235/Makefile.am index abc3b777d2..1aef14289e 100644 --- a/c/src/lib/libbsp/m68k/mcf5235/Makefile.am +++ b/c/src/lib/libbsp/m68k/mcf5235/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5235/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mcf5235/start/start.S b/c/src/lib/libbsp/m68k/mcf5235/start/start.S deleted file mode 100644 index 66b8f487de..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5235/start/start.S +++ /dev/null @@ -1,387 +0,0 @@ -/* - * mcf5235 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -#define SRAM_SIZE (64*1024) -#define DEFAULT_IPSBAR 0x40000000 - -BEGIN_CODE -#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4 - - PUBLIC (INTERRUPT_VECTOR) -SYM(INTERRUPT_VECTOR): - .long INITIAL_STACK | 0: Initial 'SSP' - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_spuriousInterrupt) | 64: User spurious handler - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte -/*************************************************************************** - Function : start - - Description : setup the internal SRAM for use and setup the INITIAL STACK ptr. - Also enable the internal peripherals - ***************************************************************************/ -.align 4 - PUBLIC (start) -SYM(start): - move.w #0x0000,d0 | Turn off watchdog timer - move.w d0, (0x40140000) - move.l #0x01000000,d0 | Set system frequency to 150 MHz - move.l d0, (0x40120000) - move.w #0x2700,sr | Disable interrupts - - move.l #__SRAMBASE+1,d0 | Enable the MCF5235 internal SRAM - movec d0,%rambar | ...so we have a stack - - move.l #0x20000201, d0 - move.l d0,(0x40000008) | set up 2nd RAMBAR to make 2nd port avail to FEC - - move.l #__IPSBAR+1,d0 | Enable the MCF5235 internal peripherals - move.l d0,DEFAULT_IPSBAR - - /* - * Remainder of the startup code is handled by C code - */ - jmp SYM(Init5235) | Start C code (which never returns) - -/*************************************************************************** - Function : CopyDataClearBSSAndStart - - Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, - start C program. Assume that DATA and BSS sizes are multiples of 4. - ***************************************************************************/ -.align 4 - - PUBLIC (CopyDataClearBSSAndStart) -SYM(CopyDataClearBSSAndStart): - lea SYM(_data_dest_start),a0 | Get start of DATA in RAM - lea SYM(_data_src_start),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NODATACOPY | Yes, no copy necessary - lea SYM(_data_dest_end),a1 | Get end of DATA in RAM - bra.s DATACOPYLOOPTEST | Branch into copy loop -DATACOPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -DATACOPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s DATACOPYLOOP | No, skip -NODATACOPY: - -/* Now, clear BSS */ - lea _clear_start,a0 | Get start of BSS - lea _clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - - /* - * Right : Now we're ready to boot RTEMS - */ - clrl d0 | Pass in null to all boot_card() params - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C boot_card function to startup RTEMS - movel a7@+,d0 -MULTI_TASK_EXIT: - nop - nop - trap #14 - bra MULTI_TASK_EXIT - .align 2 -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/mcf5329/Makefile.am b/c/src/lib/libbsp/m68k/mcf5329/Makefile.am index 1be86750a6..9429d511e2 100644 --- a/c/src/lib/libbsp/m68k/mcf5329/Makefile.am +++ b/c/src/lib/libbsp/m68k/mcf5329/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5329/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mcf5329/start/start.S b/c/src/lib/libbsp/m68k/mcf5329/start/start.S deleted file mode 100644 index 6063fdac74..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5329/start/start.S +++ /dev/null @@ -1,379 +0,0 @@ -/* - * mcf52235 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -.extern _StackInit - -BEGIN_CODE - - PUBLIC (_INTERRUPT_VECTOR) -SYM(_INTERRUPT_VECTOR): - - .long _StackInit /* 00 Initial 'SSP' */ - .long SYM(start) /* 01 Initial PC */ - .long SYM(_uhoh) /* 02 Access Error */ - .long SYM(_uhoh) /* 03 Address Error */ - .long SYM(_uhoh) /* 04 Illegal Instruction */ - .long SYM(_uhoh) /* 05 Divide by Zero */ - .long SYM(_uhoh) /* 06 Reserved */ - .long SYM(_uhoh) /* 07 Reserved */ - .long SYM(_uhoh) /* 08 Privilege Violation */ - .long SYM(_uhoh) /* 09 Trace */ - .long SYM(_uhoh) /* 10 Unimplemented A-Line */ - .long SYM(_uhoh) /* 11 Unimplemented F-Line */ - .long SYM(_uhoh) /* 12 Debug Interrupt */ - .long SYM(_uhoh) /* 13 Reserved */ - .long SYM(_uhoh) /* 14 Format Error */ - .long SYM(_uhoh) /* 15 Reserved */ - .long SYM(_uhoh) /* 16 Reserved */ - .long SYM(_uhoh) /* 17 Reserved */ - .long SYM(_uhoh) /* 18 Reserved */ - .long SYM(_uhoh) /* 19 Reserved */ - .long SYM(_uhoh) /* 20 Reserved */ - .long SYM(_uhoh) /* 21 Reserved */ - .long SYM(_uhoh) /* 22 Reserved */ - .long SYM(_uhoh) /* 23 Reserved */ - .long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* Reserved */ - .long SYM(_uhoh) /* 32 TRAP #0 */ - .long SYM(_uhoh) /* 33 TRAP #1 */ - .long SYM(_uhoh) /* 34 TRAP #2 */ - .long SYM(_uhoh) /* 35 TRAP #3 */ - .long SYM(_uhoh) /* 36 TRAP #4 */ - .long SYM(_uhoh) /* 37 TRAP #5 */ - .long SYM(_uhoh) /* 38 TRAP #6 */ - .long SYM(_uhoh) /* 39 TRAP #7 */ - .long SYM(_uhoh) /* 40 TRAP #8 */ - .long SYM(_uhoh) /* 41 TRAP #9 */ - .long SYM(_uhoh) /* 42 TRAP #10 */ - .long SYM(_uhoh) /* 43 TRAP #11 */ - .long SYM(_uhoh) /* 44 TRAP #12 */ - .long SYM(_uhoh) /* 45 TRAP #13 */ - .long SYM(_uhoh) /* 46 TRAP #14 */ - .long SYM(_uhoh) /* 47 TRAP #15 */ - .long SYM(_uhoh) /* 48 Reserved */ - .long SYM(_uhoh) /* 49 Reserved */ - .long SYM(_uhoh) /* 50 Reserved */ - .long SYM(_uhoh) /* 51 Reserved */ - .long SYM(_uhoh) /* 52 Reserved */ - .long SYM(_uhoh) /* 53 Reserved */ - .long SYM(_uhoh) /* 54 Reserved */ - .long SYM(_uhoh) /* 55 Reserved */ - .long SYM(_uhoh) /* 56 Reserved */ - .long SYM(_uhoh) /* 57 Reserved */ - .long SYM(_uhoh) /* 58 Reserved */ - .long SYM(_uhoh) /* 59 Reserved */ - .long SYM(_uhoh) /* 60 Reserved */ - .long SYM(_uhoh) /* 61 Reserved */ - .long SYM(_uhoh) /* 62 Reserved */ - .long SYM(_uhoh) /* 63 Reserved */ - - /* INTC0 */ - - .long SYM(_uhoh) /* 64*/ - .long SYM(_uhoh) /* 65*/ - .long SYM(_uhoh) /* 66*/ - .long SYM(_uhoh) /* 67*/ - .long SYM(_uhoh) /* 68*/ - .long SYM(_uhoh) /* 69*/ - .long SYM(_uhoh) /* 70*/ - .long SYM(_uhoh) /* 71*/ - .long SYM(_uhoh) /* 72*/ - .long SYM(_uhoh) /* 73*/ - .long SYM(_uhoh) /* 74*/ - .long SYM(_uhoh) /* 75*/ - .long SYM(_uhoh) /* 76*/ - .long SYM(_uhoh) /* 77*/ - .long SYM(_uhoh) /* 78*/ - .long SYM(_uhoh) /* 79*/ - .long SYM(_uhoh) /* 80*/ - .long SYM(_uhoh) /* 81*/ - .long SYM(_uhoh) /* 82*/ - .long SYM(_uhoh) /* 83*/ - .long SYM(_uhoh) /* 84*/ - .long SYM(_uhoh) /* 85*/ - .long SYM(_uhoh) /* 86*/ - .long SYM(_uhoh) /* 87*/ - .long SYM(_uhoh) /* 88*/ - .long SYM(_uhoh) /* 89*/ - .long SYM(_uhoh) /* 90*/ - .long SYM(_uhoh) /* 91*/ - .long SYM(_uhoh) /* 92*/ - .long SYM(_uhoh) /* 93*/ - .long SYM(_uhoh) /* 94*/ - .long SYM(_uhoh) /* 95*/ - .long SYM(_uhoh) /* 96*/ - .long SYM(_uhoh) /* 97*/ - .long SYM(_uhoh) /* 98*/ - .long SYM(_uhoh) /* 99*/ - .long SYM(_uhoh) /* 100*/ - .long SYM(_uhoh) /* 101*/ - .long SYM(_uhoh) /* 102*/ - .long SYM(_uhoh) /* 103*/ - .long SYM(_uhoh) /* 104*/ - .long SYM(_uhoh) /* 105*/ - .long SYM(_uhoh) /* 106*/ - .long SYM(_uhoh) /* 107*/ - .long SYM(_uhoh) /* 108*/ - .long SYM(_uhoh) /* 109*/ - .long SYM(_uhoh) /* 110*/ - .long SYM(_uhoh) /* 111*/ - .long SYM(_uhoh) /* 112*/ - .long SYM(_uhoh) /* 113*/ - .long SYM(_uhoh) /* 114*/ - .long SYM(_uhoh) /* 115*/ - .long SYM(_uhoh) /* 116*/ - .long SYM(_uhoh) /* 117*/ - .long SYM(_uhoh) /* 118*/ - .long SYM(_uhoh) /* 119*/ - .long SYM(_uhoh) /* 120*/ - .long SYM(_uhoh) /* 121*/ - .long SYM(_uhoh) /* 122*/ - .long SYM(_uhoh) /* 123*/ - .long SYM(_uhoh) /* 124*/ - .long SYM(_uhoh) /* 125*/ - .long SYM(_uhoh) /* 126*/ - .long SYM(_uhoh) /* 127*/ - - /* INTC1 */ - - .long SYM(_uhoh) /* 128*/ - .long SYM(_uhoh) /* 129*/ - .long SYM(_uhoh) /* 130*/ - .long SYM(_uhoh) /* 131*/ - .long SYM(_uhoh) /* 132*/ - .long SYM(_uhoh) /* 133*/ - .long SYM(_uhoh) /* 134*/ - .long SYM(_uhoh) /* 135*/ - .long SYM(_uhoh) /* 136*/ - .long SYM(_uhoh) /* 137*/ - .long SYM(_uhoh) /* 138*/ - .long SYM(_uhoh) /* 139*/ - .long SYM(_uhoh) /* 140*/ - .long SYM(_uhoh) /* 141*/ - .long SYM(_uhoh) /* 142*/ - .long SYM(_uhoh) /* 143*/ - .long SYM(_uhoh) /* 144*/ - .long SYM(_uhoh) /* 145*/ - .long SYM(_uhoh) /* 146*/ - .long SYM(_uhoh) /* 147*/ - .long SYM(_uhoh) /* 148*/ - .long SYM(_uhoh) /* 149*/ - .long SYM(_uhoh) /* 150*/ - .long SYM(_uhoh) /* 151*/ - .long SYM(_uhoh) /* 152*/ - .long SYM(_uhoh) /* 153*/ - .long SYM(_uhoh) /* 154*/ - .long SYM(_uhoh) /* 155*/ - .long SYM(_uhoh) /* 156*/ - .long SYM(_uhoh) /* 157*/ - .long SYM(_uhoh) /* 158*/ - .long SYM(_uhoh) /* 159*/ - .long SYM(_uhoh) /* 160*/ - .long SYM(_uhoh) /* 161*/ - .long SYM(_uhoh) /* 162*/ - .long SYM(_uhoh) /* 163*/ - .long SYM(_uhoh) /* 164*/ - .long SYM(_uhoh) /* 165*/ - .long SYM(_uhoh) /* 166*/ - .long SYM(_uhoh) /* 167*/ - .long SYM(_uhoh) /* 168*/ - .long SYM(_uhoh) /* 169*/ - .long SYM(_uhoh) /* 170*/ - .long SYM(_uhoh) /* 171*/ - .long SYM(_uhoh) /* 172*/ - .long SYM(_uhoh) /* 173*/ - .long SYM(_uhoh) /* 174*/ - .long SYM(_uhoh) /* 175*/ - .long SYM(_uhoh) /* 176*/ - .long SYM(_uhoh) /* 177*/ - .long SYM(_uhoh) /* 178*/ - .long SYM(_uhoh) /* 179*/ - .long SYM(_uhoh) /* 180*/ - .long SYM(_uhoh) /* 181*/ - .long SYM(_uhoh) /* 182*/ - .long SYM(_uhoh) /* 183*/ - .long SYM(_uhoh) /* 184*/ - .long SYM(_uhoh) /* 185*/ - .long SYM(_uhoh) /* 186*/ - .long SYM(_uhoh) /* 187*/ - .long SYM(_uhoh) /* 188*/ - .long SYM(_uhoh) /* 189*/ - .long SYM(_uhoh) /* 190*/ - .long SYM(_uhoh) /* 191*/ - .long SYM(_uhoh) /* 192*/ - - /* */ - - .long SYM(_uhoh) /* 193*/ - .long SYM(_uhoh) /* 194*/ - .long SYM(_uhoh) /* 195*/ - .long SYM(_uhoh) /* 196*/ - .long SYM(_uhoh) /* 197*/ - .long SYM(_uhoh) /* 198*/ - .long SYM(_uhoh) /* 199*/ - .long SYM(_uhoh) /* 200*/ - .long SYM(_uhoh) /* 201*/ - .long SYM(_uhoh) /* 202*/ - .long SYM(_uhoh) /* 203*/ - .long SYM(_uhoh) /* 204*/ - .long SYM(_uhoh) /* 205*/ - .long SYM(_uhoh) /* 206*/ - .long SYM(_uhoh) /* 207*/ - .long SYM(_uhoh) /* 208*/ - .long SYM(_uhoh) /* 209*/ - .long SYM(_uhoh) /* 210*/ - .long SYM(_uhoh) /* 211*/ - .long SYM(_uhoh) /* 212*/ - .long SYM(_uhoh) /* 213*/ - .long SYM(_uhoh) /* 214*/ - .long SYM(_uhoh) /* 215*/ - .long SYM(_uhoh) /* 216*/ - .long SYM(_uhoh) /* 217*/ - .long SYM(_uhoh) /* 218*/ - .long SYM(_uhoh) /* 219*/ - .long SYM(_uhoh) /* 220*/ - .long SYM(_uhoh) /* 221*/ - .long SYM(_uhoh) /* 222*/ - .long SYM(_uhoh) /* 223*/ - .long SYM(_uhoh) /* 224*/ - .long SYM(_uhoh) /* 225*/ - .long SYM(_uhoh) /* 226*/ - .long SYM(_uhoh) /* 227*/ - .long SYM(_uhoh) /* 228*/ - .long SYM(_uhoh) /* 229*/ - .long SYM(_uhoh) /* 230*/ - .long SYM(_uhoh) /* 231*/ - .long SYM(_uhoh) /* 232*/ - .long SYM(_uhoh) /* 233*/ - .long SYM(_uhoh) /* 234*/ - .long SYM(_uhoh) /* 235*/ - .long SYM(_uhoh) /* 236*/ - .long SYM(_uhoh) /* 237*/ - .long SYM(_uhoh) /* 238*/ - .long SYM(_uhoh) /* 239*/ - .long SYM(_uhoh) /* 240*/ - .long SYM(_uhoh) /* 241*/ - .long SYM(_uhoh) /* 242*/ - .long SYM(_uhoh) /* 243*/ - .long SYM(_uhoh) /* 244*/ - .long SYM(_uhoh) /* 245*/ - .long SYM(_uhoh) /* 246*/ - .long SYM(_uhoh) /* 247*/ - .long SYM(_uhoh) /* 248*/ - .long SYM(_uhoh) /* 249*/ - .long SYM(_uhoh) /* 250*/ - .long SYM(_uhoh) /* 251*/ - .long SYM(_uhoh) /* 252*/ - .long SYM(_uhoh) /* 253*/ - .long SYM(_uhoh) /* 254*/ - .long SYM(_uhoh) /* 255*/ - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -/* - * Spurious Interrupt Handler - */ -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1, SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Write VBR Register - */ -.align 4 - PUBLIC (_wr_vbr) -SYM(_wr_vbr): - move.l 4(sp), d0 - movec d0, vbr - nop - rts - -/* - * Board startup - * Disable watchdog, interrupts - * Enable sram - */ -.align 4 - PUBLIC (start) -SYM(start): - - /* Mask off interupts */ - move.w #0x2700,sr - - /* Save off reset values of D0 and D1 */ - move.l d0,d6 - move.l d1,d7 - - /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #_CoreSRamBase,d0 - add.l #0x221,d0 - movec d0,%rambar - - /* Save off intial D0 and D1 to RAM */ - move.l d6, SYM(_d0_reset) - move.l d7, SYM(_d1_reset) - - /* Locate Stack Pointer */ - move.l #_StackInit,sp - - /* - * Remainder of the startup code is handled by C code - * This never returns - */ - jmp SYM(Init5329) - -END_CODE - - -BEGIN_DATA_DCL - - .align 4 - -PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 - -PUBLIC (_d0_reset) -SYM (_d0_reset): - .long 0 - -PUBLIC (_d1_reset) -SYM (_d1_reset): - .long 0 - -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/mrm332/Makefile.am b/c/src/lib/libbsp/m68k/mrm332/Makefile.am index 4677565797..11d6ea953c 100644 --- a/c/src/lib/libbsp/m68k/mrm332/Makefile.am +++ b/c/src/lib/libbsp/m68k/mrm332/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/mrm332/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mrm332/start/start.S b/c/src/lib/libbsp/m68k/mrm332/start/start.S deleted file mode 100644 index 5e2bbebc8e..0000000000 --- a/c/src/lib/libbsp/m68k/mrm332/start/start.S +++ /dev/null @@ -1,71 +0,0 @@ -/** - * @file - * - * MRM332 Assembly Start Up Code - */ - -/* - * COPYRIGHT (c) 2000. - * Matt Cross <profesor@gweep.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#include "mrm332.h" -#include <rtems/asm.h> -#include <rtems/m68k/sim.h> - -BEGIN_CODE - - /* Put the header necessary for the modified CPU32bug to automatically - start up rtems: */ -#if 1 -.long 0xbeefbeef ; -#endif -.long 0 ; -.long start ; - -.global start - start: - - oriw #0x0700,sr /* Mask off interupts */ - - // Set VBR to CPU32Bug vector table address - movel #0x0,d0 /* Use the initial vectors until we get going */ - movecl d0,vbr - - movel #end, d0 /* Next 3 instructions set stack pointer */ - addl #_StackSize,d0 /* sp = end + _StackSize from linker script */ - movel d0,sp - movel d0,a6 - - /* include in ram_init.S */ - /* - * Initalize the SIM module. - * The stack pointer is not usable until the RAM chip select lines - * are configured. The following code must remain inline. - */ - - /* Module Configuration Register */ - /* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */ - /* SIMCR etc and SAM macro all defined in sim.h found at */ - /* /cpukit/score/cpu/m68k/rtems/m68k/sim.h */ - /* The code below does the following: */ - /* - Sets Freeze Software Enable */ - /* - Turns off Show Cycle Enable */ - /* - Sets the location of SIM module mapping */ - /* - Sets the SIM Interrupt Arbitration Field */ - lea SIMCR, a0 - movew #FRZSW,d0 - oriw #SAM(0,8,SHEN),d0 - oriw #(MM*SIM_MM),d0 - oriw #SAM(SIM_IARB,0,IARB),d0 - movew d0, a0@ - - jsr start_c /* Jump to the C startup code */ - -END_CODE - diff --git a/c/src/lib/libbsp/m68k/mvme147/Makefile.am b/c/src/lib/libbsp/m68k/mvme147/Makefile.am index 846c77e37c..f3ca13d7ea 100644 --- a/c/src/lib/libbsp/m68k/mvme147/Makefile.am +++ b/c/src/lib/libbsp/m68k/mvme147/Makefile.am @@ -10,7 +10,7 @@ noinst_PROGRAMS = ## Zilog component header files -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mvme147s/Makefile.am b/c/src/lib/libbsp/m68k/mvme147s/Makefile.am index f985e5454a..a295839808 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/Makefile.am +++ b/c/src/lib/libbsp/m68k/mvme147s/Makefile.am @@ -10,7 +10,7 @@ noinst_PROGRAMS = ## Zilog component header files -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mvme162/Makefile.am b/c/src/lib/libbsp/m68k/mvme162/Makefile.am index 72313a9473..229e73ecf3 100644 --- a/c/src/lib/libbsp/m68k/mvme162/Makefile.am +++ b/c/src/lib/libbsp/m68k/mvme162/Makefile.am @@ -9,7 +9,7 @@ noinst_PROGRAMS = ## Zilog component header files -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/mvme167/Makefile.am b/c/src/lib/libbsp/m68k/mvme167/Makefile.am index ac80bf6014..0fee829838 100644 --- a/c/src/lib/libbsp/m68k/mvme167/Makefile.am +++ b/c/src/lib/libbsp/m68k/mvme167/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/shared/start/start.S b/c/src/lib/libbsp/m68k/shared/start/start.S deleted file mode 100644 index b3a3c8b664..0000000000 --- a/c/src/lib/libbsp/m68k/shared/start/start.S +++ /dev/null @@ -1,147 +0,0 @@ -/* entry.s - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -#if (M68K_COLDFIRE_ARCH == 0) /* All ColdFire BSPs must provide their own start vector */ - -BEGIN_CODE - | Default entry points for: - PUBLIC (start) | GNU - PUBLIC (M68Kvec) | Vector Table - -SYM (start): -SYM (M68Kvec): | standard location for vectors - nop | for linkers with problem - | location zero - jmp SYM (start_around) - - /* - * We can use the following space as our vector table - * if the CPU has a VBR or we can save vector table in it - * if the CPU does not. - */ - - .space 4088 | to avoid initial intr stack - | from 135BUG on MVME13? - | and start code at 0x4000 -SYM (vectors): - .space 1016 | reserve space for rest of vectors - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) -SYM (lowintstack): - .space 4092 | reserve for interrupt stack -SYM (hiintstack): - .space 4 | end of interrupt stack -#endif - - PUBLIC (start_around) -SYM (start_around): - move.w sr, SYM (initial_sr) - oriw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movec isp,a0 - move.l a0, SYM (initial_isp) - movec usp,a0 - move.l a0, SYM (initial_usp) - movec msp,a0 - move.l a0, SYM (initial_msp) -#else - move.l a7, SYM (initial_msp) -#endif - - | - | zero out uninitialized data area - | -zerobss: - moveal # SYM (bsp_section_bss_end),a0 | find end of .bss - moveal # SYM (bsp_section_bss_begin),a1 | find beginning of .bss - movel #0,d0 - -loop: movel #0,a1@+ | to zero out uninitialized - cmpal a0,a1 - jlt loop | loop until _end reached - - movel # SYM (_stack_init),d0 | d0 = stop of stack - movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! - movel d0,a7 | set master stack pointer - movel d0,a6 | set base pointer - - /* - * RTEMS should maintain a separate interrupt stack on CPUs - * without one in hardware. This is currently not supported - * on versions of the m68k without a HW intr stack. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - lea SYM (hiintstack),a0 | a0 = high end of intr stack - movec a0,isp | set interrupt stack -#endif - - movel #0,a7@- | push command line - jsr SYM (boot_card) - addl #12,a7 - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - move.l SYM (initial_isp),a0 - movec a0,isp - move.l SYM (initial_usp),a0 - movec a0,usp - move.l SYM (initial_msp),a0 - movec a0,msp -#else - movea.l SYM (initial_msp),a7 -#endif - move.w SYM (initial_sr),sr - rts - -END_CODE - -BEGIN_DATA - - PUBLIC (start_frame) -SYM (start_frame): - .space 4,0 - -END_DATA - -BEGIN_BSS - - PUBLIC (initial_isp) -SYM (initial_isp): - .space 4 - - PUBLIC (initial_msp) -SYM (initial_msp): - .space 4 - - PUBLIC (initial_usp) -SYM (initial_usp): - .space 4 - - PUBLIC (initial_sr) -SYM (initial_sr): - .space 2 - - .align 16 - PUBLIC (starting_stack) -SYM (starting_stack): - .space 0x1000 - PUBLIC (_stack_init) -SYM (_stack_init): - -END_DATA -#endif -END diff --git a/c/src/lib/libbsp/m68k/uC5282/Makefile.am b/c/src/lib/libbsp/m68k/uC5282/Makefile.am index de7e43acb8..85d18e2309 100644 --- a/c/src/lib/libbsp/m68k/uC5282/Makefile.am +++ b/c/src/lib/libbsp/m68k/uC5282/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/m68k/uC5282/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/m68k/uC5282/start/start.S b/c/src/lib/libbsp/m68k/uC5282/start/start.S deleted file mode 100644 index 641c174a92..0000000000 --- a/c/src/lib/libbsp/m68k/uC5282/start/start.S +++ /dev/null @@ -1,403 +0,0 @@ -/* - * uC5282 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -#define SRAM_SIZE (64*1024) -#define DEFAULT_IPSBAR 0x40000000 - -BEGIN_CODE - -/*************************************************************************** - Function : Entry - - Description : Entry point to the system. In a raw system we would have - put the initial stack pointer as the first 4 bytes. Instead we have to - provide a real instruction at the first location since we might be getting - started by dBUG after downloading from TFTP or FLASH. Hack in an - 'initial stack pointer' that actually is a jump to the start address! - ***************************************************************************/ -Entry: - - - nop ; jmp SYM(start) | 0: Initial 'SSP' 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_spuriousInterrupt) | 64: User spurious handler - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -.align 4 - PUBLIC (start) -SYM(start): - move.w #0x2700,sr | Disable interrupts - - /* - * If we're being started by the debugger, and the debugger has - * moved the IPSBAR, we're doomed........ - */ - move.l #__IPSBAR+1,d0 | Enable the MCF5282 internal peripherals - move.l d0,DEFAULT_IPSBAR - move.l #__SRAMBASE+0x201,d0 | Enable the MCF5282 internal SRAM - movec d0,%rambar | CPU-space copy of RAMBAR - move.l d0,DEFAULT_IPSBAR+8 | Memory-space copy of RAMBAR - move.l #__SRAMBASE+SRAM_SIZE-4,sp | Overwrite the fake stack pointer - - /* - * Copy the vector table to address 0 (VBR must be 0 mod 2^20) - * Leave the dBUG vectors (0-63) alone - */ - lea.l (64*4)+Entry,a0 - lea.l (64*4),a1 - move.l #(256-64)-1,d0 -vectcpy: - move.l a0@+,a1@+ | Copy the vector table - sub.l #1,d0 - bne.s vectcpy - - /* - * Remainder of the startup code is handled by C code - */ - jmp SYM(Init5282) | Start C code (which never returns) - -/*************************************************************************** - Function : CopyDataClearBSSAndStart - - Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, - start C program. Assume that DATA and BSS sizes are multiples of 4. - ***************************************************************************/ -.align 4 - - PUBLIC (CopyDataClearBSSAndStart) -SYM(CopyDataClearBSSAndStart): - lea SYM(_data_dest_start),a0 | Get start of DATA in RAM - lea SYM(_data_src_start),a2 | Get start of DATA in ROM - sub.l #SYM(_header_offset),a2 | Change source by the amount of the header offset - cmpl a0,a2 | Are they the same? - beq.s NODATACOPY | Yes, no copy necessary - lea SYM(_data_dest_end),a1 | Get end of DATA in RAM - bra.s DATACOPYLOOPTEST | Branch into copy loop -DATACOPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -DATACOPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s DATACOPYLOOP | No, skip -NODATACOPY: - -/* Now, clear BSS */ - lea _clear_start,a0 | Get start of BSS - lea _clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - - /* - * Right : Now we're ready to boot RTEMS - */ - clrl d0 | Pass in null to all boot_card() params - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C boot_card function to startup RTEMS - movel a7@+,d0 -MULTI_TASK_EXIT: - nop - nop - trap #14 - bra MULTI_TASK_EXIT - - -END_CODE - - .align 2 -BEGIN_DATA_DCL - .align 2 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/mips/csb350/Makefile.am b/c/src/lib/libbsp/mips/csb350/Makefile.am index 49d28530d0..fc43b2e3c4 100644 --- a/c/src/lib/libbsp/mips/csb350/Makefile.am +++ b/c/src/lib/libbsp/mips/csb350/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/mips/csb350/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/mips/csb350/start/start.S b/c/src/lib/libbsp/mips/csb350/start/start.S deleted file mode 100644 index 9aea3f4cae..0000000000 --- a/c/src/lib/libbsp/mips/csb350/start/start.S +++ /dev/null @@ -1,122 +0,0 @@ -/* - * start.S -- startup file for Cogent CSB350 Au1100 based board - * - * Copyright (c) 2005 by Cogent Computer Systems - * Written by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#include <rtems/asm.h> -#include <bsp/regs.h> - - .text - .align 2 - -/* Without the following nop, GDB thinks _start is a data variable. - * This is probably a bug in GDB in handling a symbol that is at the - * start of the .text section. - */ - nop - - .globl _start - .ent _start -_start: - .set noreorder - - /* Get the address of start into $5 in a position independent - * fashion. This lets us know whether we have been relocated or not. - */ - $LF1 = . + 8 - bal $LF1 - nop -_branch: - move $5, $31 /* $5 == where are we */ - li $6, 0x8800000c /* $6 == where we want to be */ - - li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR - mtc0 zero, C0_CAUSE - -1: - li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR -2: -/* Fix high bits, if any, of the PC so that exception handling - doesn't get confused. */ - la v0, 3f - jr v0 - nop -3: - la gp, _gp /* set the global data pointer */ - .end _start - -/* - * zero out the bss section. - */ - .globl zerobss - .ent zerobss -zerobss: - la v0, _fbss - la v1, _end -3: - sw zero,0(v0) - bltu v0,v1,3b - addiu v0,v0,4 /* executed in delay slot */ - - la t0, _stack_init /* initialize stack so we */ - /* We must subtract 24 bytes for the 3 8 byte arguments to main, in - case main wants to write them back to the stack. The caller is - supposed to allocate stack space for parameters in registers in - the old MIPS ABIs. We must do this even though we aren't passing - arguments, because main might be declared to have them. - - Some ports need a larger alignment for the stack, so we subtract - 32, which satisifes the stack for the arguments and keeps the - stack pointer better aligned. */ - subu t0,t0,32 - move sp,t0 /* set stack pointer */ - .end zerobss - - .globl exit .text - .globl init - .ent init -init: - - move a0,zero /* set command line to 0 */ - jal boot_card /* call the program start function */ - nop - - /* fall through to the "exit" routine */ - jal _sys_exit /* call libc exit to run the G++ */ - /* destructors */ - move a0,v0 /* pass through the exit code */ - .end init - -/* - * _sys_exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run. NOTE: This is - * the only other routine we provide in the crt0.o object, since - * it may be tied to the "_start" routine. It also allows - * executables that contain a complete world to be linked with - * just the crt0.o object. - */ - .globl _sys_exit - .ent _sys_exit -_sys_exit: -7: -#ifdef GCRT0 - jal _mcleanup - nop -#endif - /* break inst. can cope with 0xfffff, but GAS limits the range: */ - break 1023 - nop - b 7b /* but loop back just in-case */ - nop - .end _sys_exit - -/* EOF crt0.S */ diff --git a/c/src/lib/libbsp/mips/hurricane/Makefile.am b/c/src/lib/libbsp/mips/hurricane/Makefile.am index b3963916a4..61a75df178 100644 --- a/c/src/lib/libbsp/mips/hurricane/Makefile.am +++ b/c/src/lib/libbsp/mips/hurricane/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs #isr -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/mips/hurricane/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/mips/hurricane/start/start.S b/c/src/lib/libbsp/mips/hurricane/start/start.S deleted file mode 100644 index e3d97cd167..0000000000 --- a/c/src/lib/libbsp/mips/hurricane/start/start.S +++ /dev/null @@ -1,339 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT -*/ - -/************************************************************************* -** -** Copyright 1991-95 Integrated Device Technology, Inc. -** All Rights Reserved -** -**************************************************************************/ - - -#include <rtems/mips/iregdef.h> -#include <rtems/mips/idtcpu.h> -#include <rtems/asm.h> - -#include <bsp.h> - -#if 0 - .extern _fdata,4 /* this is defined by the linker */ - .extern _edata,4 /* this is defined by the linker */ - .extern _idata,4 /* this is defined by the linker */ -#endif - .extern _fbss,4 /* this is defined by the linker */ - .extern end,4 /* this is defined by the linker */ - - .lcomm sim_mem_cfg_struct,12 - - .text - -/* For the V3 Eval board, we can safely assume that we have - at least 16 megabytes of RAM */ -#define HARD_CODED_MEM_SIZE 0x1000000 - -#define TMP_STKSIZE 1024 - -/* -** P_STACKSIZE is the size of the Prom Stack. -** the prom stack grows downward -*/ -#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ - -/************************************************************************** -** -** start - Typical standalone start up code required for R3000/R4000 -** -** -** 1) Initialize the STATUS Register -** a) Clear parity error bit -** b) Set co_processor 1 usable bit ON -** c) Clear all IntMask Enables -** d) Set kernel/disabled mode -** 2) Initialize Cause Register -** a) clear software interrupt bits -** 3) Determine FPU installed or not -** if not, clear CoProcessor 1 usable bit -** 4) Clear bss area -** 5) MUST allocate temporary stack until memory size determined -** It MUST be uncached to prevent overwriting when caches are cleared -** 6) Install exception handlers -** 7) Determine memory and cache sizes -** 8) Establish permanent stack (cached or uncached as defined by bss) -** 9) Flush Instruction and Data caches -** 10) If there is a Translation Lookaside Buffer, Clear the TLB -** 11) Execute initialization code if the IDT/c library is to be used -** -** 12) Jump to user's "main()" (boot_card() for RTEMS) -** 13) Jump to promexit -** -** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. -** This is used to mark code specific to R3xxx or R4xxx processors. -** IDT/C 6.x defines __mips to be the ISA level for which we're -** generating code. This is used to make sure the stack etc. is -** double word aligned, when using -mips3 (default) or -mips2, -** when compiling with IDT/C6.x -** -***************************************************************************/ - -FRAME(start,sp,0,ra) - - .set noreorder -#if __mips_fpr == 64 - li v0,SR_CU1|SR_FR|SR_DE /* initally clear ERL, enable FPU with 64 bit regs, disable cache errors */ -#else - li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPU with 32 bit regs, disable cache errors */ -#endif - - mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ - nop - mtc0 zero,C0_CAUSE /* clear software interrupts */ - nop - - la t0,0xBE200000 /* on Hurricane board, enable interrupt output signal from UART ch. B */ - li t1,0x8 /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */ - sw t1,0x10(t0) - - li v0,CFG_C_NONCOHERENT # initialise default cache mode - mtc0 v0,C0_CONFIG - -/* -** check to see if an fpu is really plugged in -*/ - li t3,0xaaaa5555 /* put a's and 5's in t3 */ - mtc1 t3,fp0 /* try to write them into fp0 */ - mtc1 zero,fp1 /* try to write zero in fp */ - mfc1 t0,fp0 - mfc1 t1,fp1 - nop - bne t0,t3,1f /* branch if no match */ - nop - bne t1,zero,1f /* double check for positive id */ - nop - /* We have a FPU. clear fcsr */ - ctc1 zero, fcr31 - j 2f /* status register already correct */ - nop -1: - li v0,SR_DE /* clear ERL and disable FPA */ - - mtc0 v0, C0_SR /* reset status register */ -2: - la gp, _gp - -#if 0 - /* Initialize data sections from "rom" copy */ - la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ - la t1,_fdata /* start of initialized data section */ - la t2,_edata /* end of initialized data section */ -3: - lw t3,0(t0) - sw t3,0(t1) - addiu t1,t1,4 - bne t1,t2,3b - addiu t0,t0,4 -#endif - - /* clear bss before using it */ - la v0,_fbss /* start of bss */ - la v1,end /* end of bss */ -4: sw zero,0(v0) - bltu v0,v1,4b - add v0,4 - - -/************************************************************************ -** -** Temporary Stack - needed to handle stack saves until -** memory size is determined and permanent stack set -** -** MUST be uncached to avoid confusion at cache -** switching during memory sizing -** -*************************************************************************/ - /* For MIPS 3, we need to be sure that the stack is aligned on a - * double word boundary. - */ - andi t0, v0, 0x7 - beqz t0, 11f /* Last three bits Zero, already aligned */ - nop - add v0, 4 -11: - - or v0, K1BASE /* switch to uncached */ - add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ - sub v1, v1, (4*4) /* overhead */ - move sp, v1 /* set sp to top of stack */ -4: sw zero, 0(v0) - bltu v0, v1, 4b /* clear out temp stack */ - add v0, 4 - -/* jal init_exc_vecs */ /* install exception handlers */ -/* nop */ /* MUST do before memory probes */ - - /* Force processor into uncached space during memory/cache probes */ - la v0, 5f - li v1, K1BASE - or v0, v1 - j v0 - nop -5: - - li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ - jal set_memory_size - nop - - la a0, sim_mem_cfg_struct - jal get_mem_conf /* Make call to get mem size */ - nop - la a0, sim_mem_cfg_struct - lw a0, 0(a0) /* Get memory size from struct */ - - jal config_cache /* determine size of D & I caches */ - nop - - move v0, a0 /* mem_size */ - - /* For MIPS 3, we need to be sure that the stack (and hence v0 - * here) is aligned on a double word boundary. - */ - andi t0, v0, 0x7 - beqz t0, 12f /* Last three bits Zero, already aligned */ - nop - subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ -12: - - - -/************************************************************************** -** -** Permanent Stack - now know top of memory, put permanent stack there -** -***************************************************************************/ - - la t2, _fbss /* cache mode as linked */ - and t2, 0xF0000000 /* isolate segment */ - la t1, 6f - j t1 /* back to original cache mode */ - nop -6: - or v0, t2 /* stack back to original cache mode */ - addiu v0,v0,-16 /* overhead */ - move sp, v0 /* now replace count w top of memory */ - move v1, v0 - subu v1, P_STACKSIZE /* clear requested stack size */ - -7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ - bltu v1,v0,7b - add v1, 4 - .set reorder - -/* FIX THIS - This corrupts memory spaces */ -/* jal flush_cache_nowrite */ /* flush Data & Instruction caches */ - -/* jal mon_flush_cache */ - -/************************************************************************** -** -** If this chip supports a Translation Lookaside Buffer, clear it -** -***************************************************************************/ - - .set noreorder - mfc0 t1, C0_SR /* look at Status Register */ - nop - .set reorder - - jal init_tlb /* clear the tlb */ - -/* Force processor into cached instruction space for rest of initialization */ -#if 0 - la t0, 1f - li t1, K0BASE /* force into cached space */ - or t0, t1 - j t0 - nop -1: -#endif - -/************************************************************************ -** -** Initialization required if using IDT/c or libc.a, standard C Lib -** -** can SKIP if not necessary for application -** -************************************************************************/ -8: - -/* FIX THIS - Need the pmon equivalent - jal idtsim_init_sbrk - jal idtsim_init_file -*/ - -/*********************** END I/O initialization **********************/ - - - move a0,zero /* Set command line passed to main */ - jal boot_card - nop - - # jump to the "exit" routine - jal idtsim__exit - move a0,v0 # pass through the exit code - - - # FIX THIS - Need the pmon equivalent - # jal idtsim_promexit - -1: - beq zero,zero,1b - nop - -ENDFRAME(start) - -/* - * _sys_exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run. NOTE: This is - * the only other routine we provide in the crt0.o object, since - * it may be tied to the "_start" routine. It also allows - * executables that contain a complete world to be linked with - * just the crt0.o object. - */ -FRAME(_sys_exit,sp,0,ra) - - break 1023 - nop -13: - b 13b # but loop back just in-case - nop - -ENDFRAME(_sys_exit) - - - - .globl __sizemem - .ent __sizemem -__sizemem: - li v0,HARD_CODED_MEM_SIZE - j ra - nop - .end __sizemem diff --git a/c/src/lib/libbsp/mips/jmr3904/Makefile.am b/c/src/lib/libbsp/mips/jmr3904/Makefile.am index 5b9516beaf..9c9ffcf56d 100644 --- a/c/src/lib/libbsp/mips/jmr3904/Makefile.am +++ b/c/src/lib/libbsp/mips/jmr3904/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs #isr -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/mips/jmr3904/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/mips/jmr3904/start/start.S b/c/src/lib/libbsp/mips/jmr3904/start/start.S deleted file mode 100644 index 92c0ddd956..0000000000 --- a/c/src/lib/libbsp/mips/jmr3904/start/start.S +++ /dev/null @@ -1,196 +0,0 @@ -/* - * start.S -- startup file for JMR3904 BSP based upon crt0.S from - * newlib-1.8.2/libgloss/mips and adapted for RTEMS. - * - * crt0.S -- startup file for MIPS. - * - * Copyright (c) 1995, 1996, 1997 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#include <rtems/asm.h> -#include <bsp/regs.h> - -#ifdef __mips16 -/* This file contains 32 bit assembly code. */ - .set nomips16 -#endif - -/* This is for referencing addresses that are not in the .sdata or - .sbss section under embedded-pic, or before we've set up gp. */ -#ifdef __mips_embedded_pic -# ifdef __mips64 -# define LA(t,x) la t,x-PICBASE ; daddu t,s0,t -# else -# define LA(t,x) la t,x-PICBASE ; addu t,s0,t -# endif -#else /* __mips_embedded_pic */ -# define LA(t,x) la t,x -#endif /* __mips_embedded_pic */ - - .text - .align 2 - -/* Without the following nop, GDB thinks _start is a data variable. - * This is probably a bug in GDB in handling a symbol that is at the - * start of the .text section. - */ - nop - - .globl _start - .ent _start -_start: - .set noreorder - /* Get the address of start into $5 in a position independent fashion. - ** This lets us know whether we have been relocated or not. - */ - $LF1 = . + 8 - bal $LF1 - nop -_branch: - move $5, $31 # $5 == where are we - li $6, 0x8800000c # $6 == where we want to be -/* #la $6,_branch */ - beq $5, $6, _start_in_ram - nop - /* relocate the code from EEPROM to RAM */ - la $7, _edata -relocate: - lw $8, ($5) # $8 = *EEPROM - addu $5, $5, 4 # EEPROM++ - sw $8, ($6) # *RAM = $8 - addu $6, $6, 4 # RAM++ - bne $6, $7, relocate # copied all the way to edata? - nop - la $6, _start_in_ram - jr $6 - nop - .end _start - - .globl _start_in_ram - .ent _start_in_ram -_start_in_ram: - nop - -#ifdef __mips_embedded_pic - PICBASE = .+8 - bal PICBASE - nop - move s0,$31 -#endif - - li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR - mtc0 zero, C0_CAUSE - -/* Check for FPU presence */ -#ifndef __mips_soft_float -/* This doesn't work if there is no FPU. We get illegal instruction - exceptions. */ - li t2,0xAAAA5555 - mtc1 t2,fp0 /* write to FPR 0 */ - mtc1 zero,fp1 /* write to FPR 1 */ - mfc1 t0,fp0 - mfc1 t1,fp1 - nop - bne t0,t2,1f /* check for match */ - nop - bne t1,zero,1f /* double check */ - nop -#ifndef __mips64 /* Clear the FR bit */ - li v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR -#endif - j 2f - nop -#endif -1: - li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR -2: -/* Fix high bits, if any, of the PC so that exception handling - doesn't get confused. */ - LA (v0, 3f) - jr v0 - nop -3: - LA (gp, _gp) # set the global data pointer - .end _start_in_ram - -/* - * zero out the bss section. - */ - .globl zerobss - .ent zerobss -zerobss: - LA (v0, _fbss) - LA (v1, _end) -3: - sw zero,0(v0) - bltu v0,v1,3b - addiu v0,v0,4 # executed in delay slot - - la t0, _stack_init # initialize stack so we - /* We must subtract 24 bytes for the 3 8 byte arguments to main, in - case main wants to write them back to the stack. The caller is - supposed to allocate stack space for parameters in registers in - the old MIPS ABIs. We must do this even though we aren't passing - arguments, because main might be declared to have them. - - Some ports need a larger alignment for the stack, so we subtract - 32, which satisifes the stack for the arguments and keeps the - stack pointer better aligned. */ - subu t0,t0,32 - move sp,t0 # set stack pointer - .end zerobss - - .globl exit .text - .globl init - .ent init -init: - - move a0,zero # set command line to 0 - jal boot_card # call the program start function - nop - - /* fall through to the "exit" routine */ - jal _sys_exit /* call libc exit to run the G++ */ - /* destructors */ - move a0,v0 /* pass through the exit code */ - .end init - -/* - * _sys_exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run. NOTE: This is - * the only other routine we provide in the crt0.o object, since - * it may be tied to the "_start" routine. It also allows - * executables that contain a complete world to be linked with - * just the crt0.o object. - */ - .globl bsp_reset -bsp_reset: - .globl _sys_exit - .ent _sys_exit -_sys_exit: -7: -#ifdef GCRT0 - jal _mcleanup - nop -#endif - /* break instruction can cope with 0xfffff, but GAS limits the range: */ - break 1023 - nop - b 7b # but loop back just in-case - nop - .end _sys_exit - -/* EOF crt0.S */ diff --git a/c/src/lib/libbsp/mips/malta/Makefile.am b/c/src/lib/libbsp/mips/malta/Makefile.am index c955b58a4a..b7bea74064 100644 --- a/c/src/lib/libbsp/mips/malta/Makefile.am +++ b/c/src/lib/libbsp/mips/malta/Makefile.am @@ -13,7 +13,7 @@ dist_project_lib_DATA = startup/bsp_specs #irq -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/mips/malta/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/mips/malta/start/start.S b/c/src/lib/libbsp/mips/malta/start/start.S deleted file mode 100644 index 8f5f96489f..0000000000 --- a/c/src/lib/libbsp/mips/malta/start/start.S +++ /dev/null @@ -1,221 +0,0 @@ -/* - * start.S -- startup file for JMR3904 BSP based upon crt0.S from - * newlib-1.8.2/libgloss/mips and adapted for RTEMS. - * - * crt0.S -- startup file for MIPS. - * - * Copyright (c) 1995, 1996, 1997 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#include <rtems/asm.h> -#include <bsp/regs.h> - -#include <bsp.h> - -#ifdef __mips16 -/* This file contains 32 bit assembly code. */ - .set nomips16 -#endif - -/* This is for referencing addresses that are not in the .sdata or - .sbss section under embedded-pic, or before we've set up gp. */ -#ifdef __mips_embedded_pic -# ifdef __mips64 -# define LA(t,x) la t,x-PICBASE ; daddu t,s0,t -# else -# define LA(t,x) la t,x-PICBASE ; addu t,s0,t -# endif -#else /* __mips_embedded_pic */ -# define LA(t,x) la t,x -#endif /* __mips_embedded_pic */ - - .text - .align 2 - -/* Without the following nop, GDB thinks _start is a data variable. - * This is probably a bug in GDB in handling a symbol that is at the - * start of the .text section. - */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - .globl _start - .ent _start -_start: - nop - nop - nop - nop - nop - nop - nop - nop - .set noreorder - /* Get the address of start into $5 in a position independent fashion. - ** This lets us know whether we have been relocated or not. - */ - $LF1 = . + 8 - bal $LF1 - nop -_branch: -#if 0 - move $5, $31 # $5 == where are we - li $6, 0x8800000c # $6 == where we want to be -/* #la $6,_branch */ - beq $5, $6, _start_in_ram - nop - /* relocate the code from EEPROM to RAM */ - la $7, _edata -relocate: - nop - lw $8, ($5) # $8 = *EEPROM - addu $5, $5, 4 # EEPROM++ - sw $8, ($6) # *RAM = $8 - addu $6, $6, 4 # RAM++ - bne $6, $7, relocate # copied all the way to edata? - nop - la $6, _start_in_ram - jr $6 - nop - .end _start - - .globl _start_in_ram - .ent _start_in_ram -#endif -_start_in_ram: - nop -#if 0 -#ifdef __mips_embedded_pic - PICBASE = .+8 - bal PICBASE - nop - move s0,$31 -#endif -#endif - li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR - mtc0 zero, C0_CAUSE - -#if 0 -/* Check for FPU presence */ -#ifndef __mips_soft_float -/* This doesn't work if there is no FPU. We get illegal instruction - exceptions. */ - li t2,0xAAAA5555 - mtc1 t2,fp0 /* write to FPR 0 */ - mtc1 zero,fp1 /* write to FPR 1 */ - mfc1 t0,fp0 - mfc1 t1,fp1 - nop - bne t0,t2,1f /* check for match */ - nop - bne t1,zero,1f /* double check */ - nop -#ifndef __mips64 /* Clear the FR bit */ - li v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR -#endif - j 2f - nop -#endif -#endif - -1: - li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX - mtc0 v0, C0_SR -2: -/* Fix high bits, if any, of the PC so that exception handling - doesn't get confused. */ - LA (v0, 3f) - jr v0 - nop -3: - LA (gp, _gp) # set the global data pointer -#if 0 - .end _start_in_ram -#else - .end _start -#endif - -/* - * zero out the bss section. - */ - .globl zerobss - .ent zerobss -zerobss: - LA (v0, _fbss) - LA (v1, _end) -3: - sw zero,0(v0) - bltu v0,v1,3b - addiu v0,v0,4 # executed in delay slot - - la t0, _stack_init # initialize stack so we - /* We must subtract 24 bytes for the 3 8 byte arguments to main, in - case main wants to write them back to the stack. The caller is - supposed to allocate stack space for parameters in registers in - the old MIPS ABIs. We must do this even though we aren't passing - arguments, because main might be declared to have them. - - Some ports need a larger alignment for the stack, so we subtract - 32, which satisifes the stack for the arguments and keeps the - stack pointer better aligned. */ - subu t0,t0,32 - move sp,t0 # set stack pointer - .end zerobss - - .globl exit .text - .globl init - .ent init -init: - nop - jal init_tlb /* clear the tlb */ - move a0,zero # set command line to 0 - jal boot_card # call the program start function - nop - -dead: - b dead - nop - .end init - -/* - * _sys_exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run. NOTE: This is - * the only other routine we provide in the crt0.o object, since - * it may be tied to the "_start" routine. It also allows - * executables that contain a complete world to be linked with - * just the crt0.o object. - */ - .globl _sys_exit - .ent _sys_exit -_sys_exit: -7: -#ifdef GCRT0 - jal _mcleanup - nop -#endif - /* break instruction can cope with 0xfffff, but GAS limits the range: */ - break 1023 - nop - b 7b # but loop back just in-case - nop - .end _sys_exit - -/* EOF crt0.S */ diff --git a/c/src/lib/libbsp/mips/rbtx4925/Makefile.am b/c/src/lib/libbsp/mips/rbtx4925/Makefile.am index 76b2ef77d1..ca8846dfd4 100644 --- a/c/src/lib/libbsp/mips/rbtx4925/Makefile.am +++ b/c/src/lib/libbsp/mips/rbtx4925/Makefile.am @@ -10,7 +10,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/mips/rbtx4925/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/mips/rbtx4925/start/start.S b/c/src/lib/libbsp/mips/rbtx4925/start/start.S deleted file mode 100644 index 058426f8c7..0000000000 --- a/c/src/lib/libbsp/mips/rbtx4925/start/start.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - -************************************************************************* -** -** Copyright 1991-95 Integrated Device Technology, Inc. -** All Rights Reserved -** -** idt_csu.S -- IDT stand alone startup code -** -**************************************************************************/ -#include <rtems/mips/iregdef.h> -#include <rtems/mips/idtcpu.h> -#include <rtems/asm.h> - -#include <bsp.h> - - .extern mon_flush_cache - -#if 0 - .extern _fdata,4 /* this is defined by the linker */ - .extern _edata,4 /* this is defined by the linker */ - .extern _idata,4 /* this is defined by the linker */ -#endif - .extern _fbss,4 /* this is defined by the linker */ - .extern end,4 /* this is defined by the linker */ - - .lcomm sim_mem_cfg_struct,12 - - .text - -#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4925 has 16 megabytes of RAM */ -#define PMON_VECTOR 0xbfc00500 - -#define TMP_STKSIZE 1024 - -/* -** P_STACKSIZE is the size of the Prom Stack. -** the prom stack grows downward -*/ -#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ - - -/************************************************************************** -** -** start - Typical standalone start up code required for R3000/R4000 -** -** -** 1) Initialize the STATUS Register -** a) Clear parity error bit -** b) Set co_processor 1 usable bit ON -** c) Clear all IntMask Enables -** d) Set kernel/disabled mode -** 2) Initialize Cause Register -** a) clear software interrupt bits -** 3) Determine FPU installed or not -** if not, clear CoProcessor 1 usable bit -** 4) Initialize data areas. Clear bss area. -** 5) MUST allocate temporary stack until memory size determined -** It MUST be uncached to prevent overwriting when caches are cleared -** 6) Install exception handlers -** 7) Determine memory and cache sizes -** 8) Establish permanent stack (cached or uncached as defined by bss) -** 9) Flush Instruction and Data caches -** 10) If there is a Translation Lookaside Buffer, Clear the TLB -** 11) Execute initialization code if the IDT/c library is to be used -** -** 12) Jump to user's "main()" -** 13) Jump to promexit -** -** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. -** This is used to mark code specific to R3xxx or R4xxx processors. -** IDT/C 6.x defines __mips to be the ISA level for which we're -** generating code. This is used to make sure the stack etc. is -** double word aligned, when using -mips3 (default) or -mips2, -** when compiling with IDT/C6.x -** -***************************************************************************/ - -FRAME(start,sp,0,ra) - - .set noreorder -#if __mips_fpr == 64 - li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */ -#else - li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */ -#endif - - mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ - nop - mtc0 zero,C0_CAUSE /* clear software interrupts */ - nop - - li v0,CFG_C_NONCOHERENT /* initialise default cache mode */ - mtc0 v0,C0_CONFIG - -/* -** check to see if a fpu is really plugged in -*/ - li t3,0xaaaa5555 /* put a's and 5's in t3 */ - mtc1 t3,fp0 /* try to write them into fp0 */ - mtc1 zero,fp1 /* try to write zero in fp */ - mfc1 t0,fp0 - mfc1 t1,fp1 - nop - bne t0,t3,1f /* branch if no match */ - nop - bne t1,zero,1f /* double check for positive id */ - nop - /* We have a FPU. clear fcsr */ - ctc1 zero, fcr31 - j 2f /* status register already correct */ - nop -1: - li v0,0x0 /* clear ERL and disable FPA */ - - mtc0 v0, C0_SR /* reset status register */ -2: - la gp, _gp /* Initialize gp register (pointer to "small" data)*/ - -#if 0 - /* Initialize data sections from "rom" copy */ - la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ - la t1,_fdata /* start of initialized data section */ - la t2,_edata /* end of initialized data section */ -3: - lw t3,0(t0) - sw t3,0(t1) - addiu t1,t1,4 - bne t1,t2,3b - addiu t0,t0,4 -#endif - - /* clear bss before using it */ - la v0,_fbss /* start of bss */ - la v1,end /* end of bss */ -4: sw zero,0(v0) - bltu v0,v1,4b - add v0,4 - - -/************************************************************************ -** -** Temporary Stack - needed to handle stack saves until -** memory size is determined and permanent stack set -** -** MUST be uncached to avoid confusion at cache -** switching during memory sizing -** -*************************************************************************/ - /* For MIPS 3, we need to be sure that the stack is aligned on a - * double word boundary. - */ - andi t0, v0, 0x7 - beqz t0, 11f /* Last three bits Zero, already aligned */ - nop - add v0, 4 -11: - - or v0, K1BASE /* switch to uncached */ - add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ - sub v1, v1, (4*4) /* overhead */ - move sp, v1 /* set sp to top of stack */ -4: sw zero, 0(v0) - bltu v0, v1, 4b /* clear out temp stack */ - add v0, 4 - -/* jal init_exc_vecs */ /* install exception handlers */ -/* nop */ /* MUST do before memory probes */ - - /* Force processor into uncached space during memory/cache probes */ - la v0, 5f - li v1, K1BASE - or v0, v1 - j v0 - nop -5: - - li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ - jal set_memory_size - nop - - la a0, sim_mem_cfg_struct - jal get_mem_conf /* Make call to get mem size */ - nop - la a0, sim_mem_cfg_struct - lw a0, 0(a0) /* Get memory size from struct */ - - jal config_cache /* determine size of D & I caches */ - nop - - move v0, a0 /* mem_size */ - - /* For MIPS 3, we need to be sure that the stack (and hence v0 - * here) is aligned on a double word boundary. - */ - andi t0, v0, 0x7 - beqz t0, 12f /* Last three bits Zero, already aligned */ - nop - subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ -12: - - - -/************************************************************************** -** -** Permanent Stack - now know top of memory, put permanent stack there -** -***************************************************************************/ - - la t2, _fbss /* cache mode as linked */ - and t2, 0xF0000000 /* isolate segment */ - la t1, 6f - j t1 /* back to original cache mode */ - nop -6: - or v0, t2 /* stack back to original cache mode */ - addiu v0,v0,-16 /* overhead */ - move sp, v0 /* now replace count w top of memory */ - move v1, v0 - subu v1, P_STACKSIZE /* clear requested stack size */ - -7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ - bltu v1,v0,7b - add v1, 4 - - -/* Invalidate data cache*/ - lui t0, 0x8000 /* Set starting address */ - addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ - /* D-Cache Writeback and Invalidate */ -1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ - nop - cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */ - cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */ - cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */ - cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */ - b 1b - addi t0, t0, 32 -2: - -/* Invalidate instruction cache*/ - lui t0, 0x8000 /* Set starting address */ - addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ - /* I-Cache Disable */ - mfc0 t2, C0_CONFIG /* get C0_Config */ - lui t3, 0x2 /* C0_CONFIG#17 ICE# */ - or t3, t2, t3 /* set ICE# bit */ - mtc0 t3, C0_CONFIG /* set C_Config */ - b 1f /* stop streaming */ - nop - /* I-Cache Invalidate */ -1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ - nop - cache 0, 0(t0) /* Index_Invalidate_I way 0 */ - cache 0, 1(t0) /* Index_Invalidate_I way 1 */ - cache 0, 2(t0) /* Index_Invalidate_I way 2 */ - cache 0, 3(t0) /* Index_Invalidate_I way 3 */ - b 1b - addi t0, t0, 32 - /* I-Cache Enable */ -2: mtc0 t2, C0_CONFIG /* set C0_Config */ - nop - -/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which - we don't want to run out of slow flash device. */ - - la t0,0x9fc00000 - li t1, 0x1000 - - move t3, t0 - addu t1, t0, t1 -1: bge t0, t1, 2f - nop - lui t2, 0x1fff /* MASK */ - ori t2, t2, 0xf000 - and t2, t3, t2 /* virtual->physical */ - srl t2, t2, 4 /* [31:12] --> [35:8] */ - ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */ - mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */ - nop - cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/ - nop - cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/ - b 1b - addi t0, t0, 32 -2: nop - - .set reorder - -/* -** Clear Translation Lookaside Buffer (TLB) -*/ - jal init_tlb /* clear the tlb */ - -/* -** End of CPU initialization, ready to start kernel -*/ - move a0,zero /* Set argc passed to main */ - jal boot_card - nop - -/* Kernel has been shutdown, jump to the "exit" routine */ - jal _sys_exit - move a0,v0 # pass through the exit code - -1: - beq zero,zero,1b - nop - -ENDFRAME(start) - -/* - * _sys_exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run. NOTE: This is - * the only other routine we provide in the crt0.o object, since - * it may be tied to the "_start" routine. It also allows - * executables that contain a complete world to be linked with - * just the crt0.o object. - */ -FRAME(_sys_exit,sp,0,ra) - - break 1023 - nop -13: - b 13b # but loop back just in-case - nop - -ENDFRAME(_sys_exit) - - - - .globl __sizemem - .ent __sizemem -__sizemem: - li v0,HARD_CODED_MEM_SIZE - j ra - nop - .end __sizemem - diff --git a/c/src/lib/libbsp/mips/rbtx4938/Makefile.am b/c/src/lib/libbsp/mips/rbtx4938/Makefile.am index 6af4ffc71d..2125aec0e7 100644 --- a/c/src/lib/libbsp/mips/rbtx4938/Makefile.am +++ b/c/src/lib/libbsp/mips/rbtx4938/Makefile.am @@ -10,7 +10,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/mips/rbtx4938/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/mips/rbtx4938/start/start.S b/c/src/lib/libbsp/mips/rbtx4938/start/start.S deleted file mode 100644 index 406f1b6bbd..0000000000 --- a/c/src/lib/libbsp/mips/rbtx4938/start/start.S +++ /dev/null @@ -1,359 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - -************************************************************************* -** -** Copyright 1991-95 Integrated Device Technology, Inc. -** All Rights Reserved -** -** idt_csu.S -- IDT stand alone startup code -** -**************************************************************************/ -#include <rtems/mips/iregdef.h> -#include <rtems/mips/idtcpu.h> -#include <rtems/asm.h> - -#include <bsp.h> - - .extern mon_flush_cache - -#if 0 - .extern _fdata,4 /* this is defined by the linker */ - .extern _edata,4 /* this is defined by the linker */ - .extern _idata,4 /* this is defined by the linker */ -#endif - .extern _fbss,4 /* this is defined by the linker */ - .extern end,4 /* this is defined by the linker */ - - .lcomm sim_mem_cfg_struct,12 - - .text - -#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4938 has 16 megabytes of RAM */ -#define PMON_VECTOR 0xbfc00500 - -#define TMP_STKSIZE 1024 - -/* -** P_STACKSIZE is the size of the Prom Stack. -** the prom stack grows downward -*/ -#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ - -/************************************************************************** -** -** start - Typical standalone start up code required for R3000/R4000 -** -** -** 1) Initialize the STATUS Register -** a) Clear parity error bit -** b) Set co_processor 1 usable bit ON -** c) Clear all IntMask Enables -** d) Set kernel/disabled mode -** 2) Initialize Cause Register -** a) clear software interrupt bits -** 3) Determine FPU installed or not -** if not, clear CoProcessor 1 usable bit -** 4) Initialize data areas. Clear bss area. -** 5) MUST allocate temporary stack until memory size determined -** It MUST be uncached to prevent overwriting when caches are cleared -** 6) Install exception handlers -** 7) Determine memory and cache sizes -** 8) Establish permanent stack (cached or uncached as defined by bss) -** 9) Flush Instruction and Data caches -** 10) If there is a Translation Lookaside Buffer, Clear the TLB -** 11) Execute initialization code if the IDT/c library is to be used -** -** 12) Jump to user's "main()" -** 13) Jump to promexit -** -** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. -** This is used to mark code specific to R3xxx or R4xxx processors. -** IDT/C 6.x defines __mips to be the ISA level for which we're -** generating code. This is used to make sure the stack etc. is -** double word aligned, when using -mips3 (default) or -mips2, -** when compiling with IDT/C6.x -** -***************************************************************************/ - -FRAME(start,sp,0,ra) - - .set noreorder -#if __mips_fpr == 64 - li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */ -#else - li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */ -#endif - - mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ - nop - mtc0 zero,C0_CAUSE /* clear software interrupts */ - nop - - li v0,CFG_C_NONCOHERENT /* initialise default cache mode */ - mtc0 v0,C0_CONFIG - -/* -** check to see if a fpu is really plugged in -*/ - li t3,0xaaaa5555 /* put a's and 5's in t3 */ - mtc1 t3,fp0 /* try to write them into fp0 */ - mtc1 zero,fp1 /* try to write zero in fp */ - mfc1 t0,fp0 - mfc1 t1,fp1 - nop - bne t0,t3,1f /* branch if no match */ - nop - bne t1,zero,1f /* double check for positive id */ - nop - /* We have a FPU. clear fcsr */ - ctc1 zero, fcr31 - j 2f /* status register already correct */ - nop -1: - li v0,0x0 /* clear ERL and disable FPA */ - - mtc0 v0, C0_SR /* reset status register */ -2: - la gp, _gp /* Initialize gp register (pointer to "small" data)*/ - -#if 0 - /* Initialize data sections from "rom" copy */ - la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ - la t1,_fdata /* start of initialized data section */ - la t2,_edata /* end of initialized data section */ -3: - lw t3,0(t0) - sw t3,0(t1) - addiu t1,t1,4 - bne t1,t2,3b - addiu t0,t0,4 -#endif - - /* clear bss before using it */ - la v0,_fbss /* start of bss */ - la v1,end /* end of bss */ -4: sw zero,0(v0) - bltu v0,v1,4b - add v0,4 - - -/************************************************************************ -** -** Temporary Stack - needed to handle stack saves until -** memory size is determined and permanent stack set -** -** MUST be uncached to avoid confusion at cache -** switching during memory sizing -** -*************************************************************************/ - /* For MIPS 3, we need to be sure that the stack is aligned on a - * double word boundary. - */ - andi t0, v0, 0x7 - beqz t0, 11f /* Last three bits Zero, already aligned */ - nop - add v0, 4 -11: - - or v0, K1BASE /* switch to uncached */ - add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ - sub v1, v1, (4*4) /* overhead */ - move sp, v1 /* set sp to top of stack */ -4: sw zero, 0(v0) - bltu v0, v1, 4b /* clear out temp stack */ - add v0, 4 - -/* jal init_exc_vecs */ /* install exception handlers */ -/* nop */ /* MUST do before memory probes */ - - /* Force processor into uncached space during memory/cache probes */ - la v0, 5f - li v1, K1BASE - or v0, v1 - j v0 - nop -5: - - li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ - jal set_memory_size - nop - - la a0, sim_mem_cfg_struct - jal get_mem_conf /* Make call to get mem size */ - nop - la a0, sim_mem_cfg_struct - lw a0, 0(a0) /* Get memory size from struct */ - - jal config_cache /* determine size of D & I caches */ - nop - - move v0, a0 /* mem_size */ - - /* For MIPS 3, we need to be sure that the stack (and hence v0 - * here) is aligned on a double word boundary. - */ - andi t0, v0, 0x7 - beqz t0, 12f /* Last three bits Zero, already aligned */ - nop - subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ -12: - - - -/************************************************************************** -** -** Permanent Stack - now know top of memory, put permanent stack there -** -***************************************************************************/ - - la t2, _fbss /* cache mode as linked */ - and t2, 0xF0000000 /* isolate segment */ - la t1, 6f - j t1 /* back to original cache mode */ - nop -6: - or v0, t2 /* stack back to original cache mode */ - addiu v0,v0,-16 /* overhead */ - move sp, v0 /* now replace count w top of memory */ - move v1, v0 - subu v1, P_STACKSIZE /* clear requested stack size */ - -7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ - bltu v1,v0,7b - add v1, 4 - - -/* Invalidate data cache*/ - lui t0, 0x8000 /* Set starting address */ - addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ - /* D-Cache Writeback and Invalidate */ -1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ - nop - cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */ - cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */ - cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */ - cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */ - b 1b - addi t0, t0, 32 -2: - -/* Invalidate instruction cache*/ - lui t0, 0x8000 /* Set starting address */ - addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ - /* I-Cache Disable */ - mfc0 t2, C0_CONFIG /* get C0_Config */ - lui t3, 0x2 /* C0_CONFIG#17 ICE# */ - or t3, t2, t3 /* set ICE# bit */ - mtc0 t3, C0_CONFIG /* set C_Config */ - b 1f /* stop streaming */ - nop - /* I-Cache Invalidate */ -1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ - nop - cache 0, 0(t0) /* Index_Invalidate_I way 0 */ - cache 0, 1(t0) /* Index_Invalidate_I way 1 */ - cache 0, 2(t0) /* Index_Invalidate_I way 2 */ - cache 0, 3(t0) /* Index_Invalidate_I way 3 */ - b 1b - addi t0, t0, 32 - /* I-Cache Enable */ -2: mtc0 t2, C0_CONFIG /* set C0_Config */ - nop - -/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which - we don't want to run out of slow flash device. */ - - la t0,0x9fc00000 - li t1, 0x1000 - - move t3, t0 - addu t1, t0, t1 -1: bge t0, t1, 2f - nop - lui t2, 0x1fff /* MASK */ - ori t2, t2, 0xf000 - and t2, t3, t2 /* virtual->physical */ - srl t2, t2, 4 /* [31:12] --> [35:8] */ - ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */ - mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */ - nop - cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/ - nop - cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/ - b 1b - addi t0, t0, 32 -2: nop - - .set reorder - -/* -** Clear Translation Lookaside Buffer (TLB) -*/ - jal init_tlb /* clear the tlb */ - -/* -** End of CPU initialization, ready to start kernel -*/ - move a0,zero /* Set command line passed to boot_card */ - jal boot_card - nop - -/* Kernel has been shutdown, jump to the "exit" routine */ - jal _sys_exit - move a0,v0 # pass through the exit code - -1: - beq zero,zero,1b - nop - -ENDFRAME(start) - -/* - * _sys_exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run. NOTE: This is - * the only other routine we provide in the crt0.o object, since - * it may be tied to the "_start" routine. It also allows - * executables that contain a complete world to be linked with - * just the crt0.o object. - */ -FRAME(_sys_exit,sp,0,ra) - - break 1023 - nop -13: - b 13b # but loop back just in-case - nop - -ENDFRAME(_sys_exit) - - - - .globl __sizemem - .ent __sizemem -__sizemem: - li v0,HARD_CODED_MEM_SIZE - j ra - nop - .end __sizemem - diff --git a/c/src/lib/libbsp/moxie/moxiesim/Makefile.am b/c/src/lib/libbsp/moxie/moxiesim/Makefile.am index 16ce5b6d5e..46743bd7da 100644 --- a/c/src/lib/libbsp/moxie/moxiesim/Makefile.am +++ b/c/src/lib/libbsp/moxie/moxiesim/Makefile.am @@ -11,7 +11,7 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/moxie/moxiesim/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/moxie/moxiesim/start/start.S b/c/src/lib/libbsp/moxie/moxiesim/start/start.S deleted file mode 100644 index ae712cb3e4..0000000000 --- a/c/src/lib/libbsp/moxie/moxiesim/start/start.S +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright (C) 2011, 2013, 2014 Anthony Green */ - -/* moxie start up file. */ - -#include "bspopts.h" - -#if defined(HAVE_OLD_MOXIE_ASM) -#define sub sub.l -#endif - - .text - .global _start -_start: - ldi.l $sp, _stack /* load up stack pointer */ - xor $fp, $fp /* zero fp to allow unwinders to stop */ - - /* zero the bss area */ - ldi.l $r0, __bss_start__ - xor $r1, $r1 - ldi.l $r2, __bss_end__ - sub $r2, $r0 - jsra memset - - ldi.l $r0, 0x0 # pass in NULL - jsra boot_card - jmpa _start # restart -.Lend: - .size _start,(.Lend-_start) diff --git a/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am b/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am index 2fe8023b42..8430a359f0 100644 --- a/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am +++ b/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am @@ -7,9 +7,9 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/nios2/nios2_iss/start/start.S $(CPPASCOMPILE) -o $@ -c $< -crtnn.$(OBJEXT): start/crtnn.S +crtnn.$(OBJEXT): ../../../../../../bsps/nios2/nios2_iss/start/crtnn.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) crtnn.$(OBJEXT) diff --git a/c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.S b/c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.S deleted file mode 100644 index ae805bc967..0000000000 --- a/c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.S +++ /dev/null @@ -1,43 +0,0 @@ -/* NIOS2 crtn.asm fix - * - * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* Can't use the original crtn.asm from Altera because it doesn't - restore the stack pointer correctly (in 5.1b73, the stack pointer - is further decreased by 48 instead of increased). This is named - differently (crtnn instead crtn) to make sure it can be picked up - using custom gcc specs instead of gcc's crtn. - kawk */ - - .section .init - ldw ra, 44(sp) - ldw r23, 40(sp) - ldw r22, 36(sp) - ldw r21, 32(sp) - ldw r20, 28(sp) - ldw r19, 24(sp) - ldw r18, 20(sp) - ldw r17, 16(sp) - ldw r16, 12(sp) - ldw fp, 8(sp) - addi sp, sp, 48 - ret - - .section .fini - ldw ra, 44(sp) - ldw r23, 40(sp) - ldw r22, 36(sp) - ldw r21, 32(sp) - ldw r20, 28(sp) - ldw r19, 24(sp) - ldw r18, 20(sp) - ldw r17, 16(sp) - ldw r16, 12(sp) - ldw fp, 8(sp) - addi sp, sp, 48 - ret - diff --git a/c/src/lib/libbsp/nios2/nios2_iss/start/start.S b/c/src/lib/libbsp/nios2/nios2_iss/start/start.S deleted file mode 100644 index 1ffa4fc925..0000000000 --- a/c/src/lib/libbsp/nios2/nios2_iss/start/start.S +++ /dev/null @@ -1,122 +0,0 @@ -/* NIOS2 startup code - * - * This is the entry point on reset and when loading the - * executive from a bootloader. - * - * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - .section .entry - .align 3 - movhi et, %hiadj(start) - addi et, et, %lo(start) - jmp et - - .section .irq - .align 3 - movhi et, %hiadj(_exception_vector) - addi et, et, %lo(_exception_vector) - jmp et - - .section .text - .align 3 - .globl start - .type start,@function - - .extern _exception_vector - -start: - #------------------------------------------------------ - # disable interrupts - wrctl status, zero - wrctl ienable, zero - - #------------------------------------------------------ - # invalidate instruction cache - mov r2, r0 - movhi r3, %hi(__nios2_icache_size) - ori r3, r3, %lo(__nios2_icache_size) -icache_init_loop: - initi r2 - addi r2, r2, __nios2_icache_line_size - bltu r2, r3, icache_init_loop - - #------------------------------------------------------ - # invalidate data cache - mov r2, r0 - movhi r3, %hi(__nios2_dcache_size) - ori r3, r3, %lo(__nios2_dcache_size) -dcache_init_loop: - initd 0(r2) - addi r2, r2, __nios2_dcache_line_size - bltu r2, r3, dcache_init_loop - - #------------------------------------------------------ - # initialize stack pointer - movhi sp, %hiadj(__alt_stack_pointer - 4) - addi sp, sp, %lo(__alt_stack_pointer - 4) - - # initialize global pointer - movhi gp, %hiadj(_gp) - addi gp, gp, %lo(_gp) - - # initialize exception tmp register - movhi et, %hiadj(_end) - addi et, et, %lo(_end) - - #------------------------------------------------------ - # TODO: copy data from flash to RAM, if not there already - # For now its save to assume it is there already when we're - # loading code though JTAG into RAM-only system - - # at least copy exception code to right place - movhi r2, %hiadj(__ram_exceptions_start) - addi r2, r2, %lo(__ram_exceptions_start) - - movhi r3, %hiadj(brto_ev) - addi r3, r3, %lo(brto_ev) - ldw r4, 0(r3) - stw r4, 0(r2) - ldw r4, 4(r3) - stw r4, 4(r2) - ldw r4, 8(r3) - stw r4, 8(r2) - ldw r4, 12(r3) - stw r4, 12(r2) - - #------------------------------------------------------ - # clear bss - movhi r2, %hiadj(__bss_start) - addi r2, r2, %lo(__bss_start) - - movhi r3, %hiadj(__bss_end) - addi r3, r3, %lo(__bss_end) - - beq r2, r3, 1f -0: - stw zero, (r2) - addi r2, r2, 4 - bltu r2, r3, 0b -1: - #------------------------------------------------------ - # jump to (shared) boot_card (never comes back) - mov r4, zero - mov r5, zero - mov r6, zero - call boot_card - # but just in case it does come back, stick here. -_stuck_in_start: - br _stuck_in_start - - #------------------------------------------------------ - # code to be placed at exception address -brto_ev: - movhi et, %hiadj(_exception_vector) - addi et, et, %lo(_exception_vector) - jmp et - - diff --git a/c/src/lib/libbsp/or1k/generic_or1k/Makefile.am b/c/src/lib/libbsp/or1k/generic_or1k/Makefile.am index dd8b7a5c75..fecd2e8c19 100644 --- a/c/src/lib/libbsp/or1k/generic_or1k/Makefile.am +++ b/c/src/lib/libbsp/or1k/generic_or1k/Makefile.am @@ -19,7 +19,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/or1k/generic_or1k/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S deleted file mode 100644 index 26991c8960..0000000000 --- a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE - */ -#include <bsp/linker-symbols.h> - -/* The following macro defines the first instructions every exception - * should execute before jumping to its handler function from the - * exception vector table. r3 is saved into the stack and loaded with - * vector number before jumping to _ISR_Handler. r3 value is restored - * back from _ISR_Handler after handling the exception and before - * returning from interrupt. - */ -#define EXCEPTION_SETUP(vector) \ - l.nop ;\ - l.addi r1, r1, -200 ;\ - l.sw 0(r1), r3; \ - l.addi r3, r0, vector; \ - l.j _ISR_Handler; \ - l.nop - - .extern boot_card - .extern bsp_section_bss_begin - .extern bsp_section_bss_end - - .extern bsp_start_vector_table_end - .extern bsp_start_vector_table_size - .extern bsp_vector_table_size - .extern bsp_section_stack_begin - - .extern exception_frame_save - .extern _OR1K_Exception_Process - .extern _OR1K_Exception_default - .extern rtems_clock_tick - .extern _exit - .extern printk - .extern bsp_interrupt_handler_default - - /* Global symbols */ - .global _start - .global bsp_start_vector_table_begin - -/* Popualte HW vector table */ - -.section .vector, "ax" - -.org 0x100 -_reset: - l.j _start - l.nop - -.org 0x200 -_buserr: - EXCEPTION_SETUP(2) - -.org 0x300 -_dPageFault: - EXCEPTION_SETUP(3) - -.org 0x400 -_iPageFaule: - EXCEPTION_SETUP(4) - -.org 0x500 -_timer: - EXCEPTION_SETUP(5) - -.org 0x600 -_unalign: - EXCEPTION_SETUP(6) - -.org 0x700 -_undefIns: - EXCEPTION_SETUP(7) - -.org 0x800 -_exInt: - EXCEPTION_SETUP(8) - -.org 0x900 -_dTLB: - EXCEPTION_SETUP(9) - -.org 0xA00 -_iTLB: - EXCEPTION_SETUP(10) - -.org 0xB00 -_range: - EXCEPTION_SETUP(11) - -.org 0xC00 -_syscall: - EXCEPTION_SETUP(12) - -.org 0xD00 -_fp: - EXCEPTION_SETUP(13) - -.org 0xE00 -_trap: - EXCEPTION_SETUP(14) - -.org 0xF00 -_undef1: - EXCEPTION_SETUP(15) - -.org 0x1500 -_undef2: - EXCEPTION_SETUP(16) - -.org 0x1900 -_undef3: - EXCEPTION_SETUP(17) - -.org 0x1F00 - -bsp_start_vector_table_begin: - - .word 0 - .word _start /* Reset */ - .word _OR1K_Exception_default /* Bus Error */ - .word _OR1K_Exception_default /* Data Page Fault */ - .word _OR1K_Exception_default /* Instruction Page Fault */ - .word _OR1K_Exception_default /* Tick timer */ - .word _OR1K_Exception_default /* Alignment */ - .word _OR1K_Exception_default /* Undefiend Instruction */ - .word _OR1K_Exception_default /* External Interrupt */ - .word _OR1K_Exception_default /* Data TLB Miss */ - .word _OR1K_Exception_default /* Instruction TLB Miss */ - .word _OR1K_Exception_default /* Range Exception */ - .word _OR1K_Exception_default /* System Call */ - .word _OR1K_Exception_default /* Floating Point Exception */ - .word _OR1K_Exception_default /* Trap */ - .word _OR1K_Exception_default /* Reserver for future use */ - .word _OR1K_Exception_default /* Reserved for implementation-specific */ - .word _OR1K_Exception_default /* Reserved for custom exceptions. */ - -bsp_start_vector_table_end: - - .section ".bsp_start_text", "ax" - .type _start,@function - -_start: - /* Set SR register to Supervision mode */ - l.ori r1, r0, 0x1 - l.mtspr r0, r1, 17 - - /* load stack and frame pointers */ - l.movhi r1, hi(bsp_section_stack_begin) - l.ori r1, r1, lo(bsp_section_stack_begin) - l.add r2, r0, r1 - -/* Clearing .bss */ - l.movhi r13, hi(bsp_section_bss_begin) - l.ori r13, r13, lo(bsp_section_bss_begin) - l.movhi r15, hi(bsp_section_bss_end) - l.ori r15, r15, lo(bsp_section_bss_end) - -_loop_clear_bss: - l.sfgeu r13, r15 - l.bf _end_clear_bss - l.addi r13, r13, 4 - l.sw 0(r13), r0 - l.j _loop_clear_bss - l.nop -_end_clear_bss: - - l.j boot_card - l.nop - -/* Temporary code for unhandled exceptions */ -.section .text -.align -.global _unhandled_exception - -unhandled_exception: - l.nop diff --git a/c/src/lib/libbsp/powerpc/beatnik/Makefile.am b/c/src/lib/libbsp/powerpc/beatnik/Makefile.am index bb295f3a80..ecd7f6a8a4 100644 --- a/c/src/lib/libbsp/powerpc/beatnik/Makefile.am +++ b/c/src/lib/libbsp/powerpc/beatnik/Makefile.am @@ -13,18 +13,18 @@ project_lib_DATA = #include #start -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -DASM -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) -preload.$(OBJEXT): ../shared/start/preload.S +preload.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/preload.S $(CPPASCOMPILE) -DASM -o $@ -c $< -vectors_entry.$(OBJEXT): ../shared/start/vectors_entry.S +vectors_entry.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/vectors_entry.S $(CPPASCOMPILE) -DASM -o $@ -c $< -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/start.S $(CPPASCOMPILE) -DASM -o $@ -c $< motld_start.$(OBJEXT): preload.$(OBJEXT) vectors_entry.$(OBJEXT) start.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/gen5200/Makefile.am b/c/src/lib/libbsp/powerpc/gen5200/Makefile.am index 2138ad053a..72767c0bc8 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/Makefile.am +++ b/c/src/lib/libbsp/powerpc/gen5200/Makefile.am @@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/gen5200/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S deleted file mode 100644 index 0c2dfd5989..0000000000 --- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S +++ /dev/null @@ -1,1000 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MPC5200 BSP | -+-----------------------------------------------------------------+ -| Partially based on the code references which are named below. | -| Adaptions, modifications, enhancements and any recent parts of | -| the code are: | -| Copyright (c) 2005 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the startup assembly code | -\*===============================================================*/ -/***********************************************************************/ -/* */ -/* Module: start.S */ -/* Date: 07/17/2003 */ -/* Purpose: RTEMS MPC5x00 CPU assembly startup */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Description: This file contains the assembler portion of MPC5x00 */ -/* startup code */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Code */ -/* References: startup code for Motorola PQII ADS board */ -/* Module: start.S */ -/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ -/* Version 1.2 */ -/* Date: 04/18/2002 */ -/* */ -/* Author(s) / Copyright(s): */ -/* */ -/* Modified for the Motorola PQII ADS board by */ -/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */ -/* Surrey Satellite Technology Limited */ -/* */ -/* I have a proprietary bootloader programmed into the flash */ -/* on the board which initialises the SDRAM prior to calling */ -/* this function. */ -/* */ -/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/ -/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/ -/* written by: */ -/* */ -/* Author: Andrew Bray <andy@i-cubed.co.uk> */ -/* */ -/* COPYRIGHT (c) 1995 by i-cubed ltd. */ -/* */ -/* To anyone who acknowledges that this file is provided "AS IS" */ -/* without any express or implied warranty: */ -/* permission to use, copy, modify, and distribute this file */ -/* for any purpose is hereby granted without fee, provided that */ -/* the above copyright notice and this notice appears in all */ -/* copies, and that the name of i-cubed limited not be used in */ -/* advertising or publicity pertaining to distribution of the */ -/* software without specific, written prior permission. */ -/* i-cubed limited makes no representations about the suitability */ -/* of this software for any purpose. */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Partially based on the code references which are named above. */ -/* Adaptions, modifications, enhancements and any recent parts of */ -/* the code are under the right of */ -/* */ -/* IPR Engineering, Dachauer Straße 38, D-80335 München */ -/* Copyright(C) 2003 */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* IPR Engineering makes no representation or warranties with */ -/* respect to the performance of this computer program, and */ -/* specifically disclaims any responsibility for any damages, */ -/* special or consequential, connected with the use of this program. */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Version history: 1.0 */ -/* */ -/***********************************************************************/ - -#include <rtems/powerpc/cache.h> - -#include <bsp.h> -#include <bsp/mpc5200.h> - -/* Some register offsets of MPC5x00 memory map registers */ -.set CS0STR, 0x04 -.set CS0STP, 0x08 -.set CS1STR, 0x0C -.set CS1STP, 0x10 -.set SDRAMCS0, 0x34 -.set SDRAMCS1, 0x38 -.set BOOTSTR, 0x4C -.set BOOTSTP, 0x50 -.set ADREN, 0x54 -.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */ -.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */ -.set CFG, 0x20C -.set CSBOOTROM, 0x300 -.set CSCONTROL, 0x318 -.set CS1CONF, 0x304 - - -/* Register offsets of MPC5x00 SDRAM memory controller registers */ -.set MOD, 0x100 -.set CTRL, 0x104 -.set CFG1, 0x108 -.set CFG2, 0x10C -.set ADRSEL, 0x110 -.set SDELAY, 0x190 - -/* Register offsets of MPC5x00 GPIO registers needed */ -.set GPIOPCR, 0xb00 -.set GPIOWE, 0xc00 -.set GPIOWOD, 0xc04 -.set GPIOWDD, 0xc08 -.set GPIOWDO, 0xc0c - -.set GPIOSEN, 0xb04 -.set GPIOSDD, 0xb0c -.set GPIOSDO, 0xb10 - -/* Register offsets of MPC5x00 Arbiter registers */ -.set ARBCFG, 0x1f40 -.set ARBADRTO, 0x1f58 -.set ARBDATTO, 0x1f5c -.set ARBMPREN, 0x1f64 -.set ARBMPRIO, 0x1f68 -.set ARBSNOOP, 0x1f70 - -/* Some bit encodings for MGT5100 registers */ -.set ADREN_BOOT_EN, (1 << (31 - 6)) -.set ADREN_CS0_EN, (1 << (31 - 15)) -.set ADREN_CS1_EN, (1 << (31 - 14)) -.set ADREN_WSE, (1 << (31 - 31)) - -.set CTRL_PRECHARGE_ALL, (1 << (31 - 30)) -.set CTRL_REFRESH, (1 << (31 - 29)) -.set CTRL_MODE_EN, (1 << (31 - 0)) - -.set CSCONF_CE, (1<<12) - -/* Some fixed values for MPC5x00 registers */ -.set CSCONTROL_VAL, 0x91000000 - -/* - * The DDR_MODE bit is a read-only status and should be written as 0. - * - * XLB_CLK = FVCO / 4 - * IPB_CLK = XLB_CLK / 2 - * PCI_CLK = IPB_CLK - */ -.set CFG_VAL, 0x00000100 - -.extern boot_card - -.section ".vectors", "ax" - bl start - .rep 63 - .long 0x04000400 - .endr -__vec2: b __vec2 - .rep 63 - .long 0x04000400 - .endr -__vec3: b __vec3 - .rep 63 - .long 0x04000400 - .endr -__vec4: b __vec4 - .rep 63 - .long 0x04000400 - .endr -__vec5: b __vec5 - .rep 63 - .long 0x04000400 - .endr -__vec6: b __vec6 - .rep 63 - .long 0x04000400 - .endr -__vec7: b __vec7 - .rep 63 - .long 0x04000400 - .endr -__vec8: b __vec8 - .rep 63 - .long 0x04000400 - .endr -__vec9: b __vec9 - .rep 63 - .long 0x04000400 - .endr -__veca: b __veca - .rep 63 - .long 0x04000400 - .endr -__vecb: b __vecb - .rep 63 - .long 0x04000400 - .endr -__vecc: b __vecc - .rep 63 - .long 0x04000400 - .endr -__vecd: b __vecd - .rep 63 - .long 0x04000400 - .endr -__vece: b __vece - .rep 63 - .long 0x04000400 - .endr -__vecf: b __vecf - .rep 63+1024 - .long 0x04000400 - .endr - -.section ".entry" -PUBLIC_VAR (start) -start: -/* 1st: initialization work (common for RAM/ROM startup) */ - mfmsr r30 - SETBITS r30, r29, MSR_ME|MSR_RI - CLRBITS r30, r29, MSR_EE - mtmsr r30 /* Set RI/ME, Clr EE in MSR */ - -#ifdef HAS_UBOOT - mr r14, r3 -#endif /* HAS_UBOOT */ - -#if defined(NEED_LOW_LEVEL_INIT) -/* initialize the MBAR (common RAM/ROM startup) */ - LWI r31, MBAR_RESET - LWI r29, MBAR - rlwinm r30, r29,16,16,31 - stw r30, 0(r31) /* Set the MBAR */ -#endif - - LWI r31, MBAR /* set r31 to current MBAR */ - /* init GPIOPCR */ - lwz r29,GPIOPCR(r31) - LWI r30, BSP_GPIOPCR_INITMASK - not r30,r30 - and r29,r29,r30 - LWI r30, BSP_GPIOPCR_INITVAL - or r29,r29,r30 - stw r29, GPIOPCR(r31) - -/* further initialization work (common RAM/ROM startup) */ - bl TLB_init /* Initialize TLBs */ - - - bl FID_DCache /* Flush, inhibit and disable data cache */ - - - bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */ - - - bl FPU_init /* Initialize FPU */ - - -#if defined(NEED_LOW_LEVEL_INIT) - bl SPRG_init /* Initialize special purpose registers */ -#endif - -#if defined(NEED_LOW_LEVEL_INIT) -/* detect RAM/ROM startup (common for RAM/ROM startup) */ - LWI r20, bsp_rom_start /* set the relocation offset */ - - - LWI r30, CFG_VAL /* get CFG register content */ - lwz r30, CFG(r31) /* set CFG register */ - - - - lwz r30, ADREN(r31) /* get content of ADREN */ - - - - TSTBITS r30, r29, ADREN_BOOT_EN - bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */ - -/* do some board dependent configuration (unique for ROM startup) */ - LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */ - stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */ - - -#if defined(MPC5200_BOARD_BRS5L) - #define CSBOOTROM_VAL 0x0101D910 -#elif defined(MPC5200_BOARD_BRS6L) - #define CSBOOTROM_VAL 0x0202D910 -#endif - -#ifdef CSBOOTROM_VAL - LWI r30, CSBOOTROM_VAL - stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */ -#endif - - /* FIXME: map BOOT ROM into final location with CS0 registers */ - LWI r30, bsp_rom_start - rlwinm r30, r30,17,15,31 - stw r30, CS0STR(r31) /* Set CS0STR */ - - LWI r30, bsp_rom_end - 1 - - rlwinm r30, r30,17,15,31 - stw r30, CS0STP(r31) /* Set CS0STP */ - - lwz r30, ADREN(r31) /* get content of ADREN */ - SETBITS r30, r29, ADREN_CS0_EN - stw r30, ADREN(r31) /* enable CS0 mapping */ - isync - /* jump to same code in final BOOT ROM location */ - LWI r30, reloc_in_CS0 - LWI r29, bsp_ram_start - sub r30,r30,r29 - LWI r29, bsp_rom_start - add r30,r30,r29 - mtctr r30 - bctr - -reloc_in_CS0: - /* disable CSBOOT (or map it to CS0 range) */ - lwz r30, ADREN(r31) /* get content of ADREN */ - CLRBITS r30, r29, ADREN_BOOT_EN - stw r30, ADREN(r31) /* disable BOOT mapping */ - - /* init SDRAM */ - LWI r30, bsp_ram_start - ori r30, r30, 0x1a /* size code: bank is 128MByte */ - stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */ - - LWI r30, bsp_ram_size - srawi r30, r30, 1 - ori r30, r30, 0x1a /* size code: bank is 128MByte */ - stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */ - - bl SDRAM_init /* Initialize SDRAM controller */ - - bl XLB_init -/* copy .text section from ROM to RAM location (unique for ROM startup) */ - LA r30, bsp_section_text_start /* get start address of text section in RAM */ - - - add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */ - - - LA r29, bsp_section_text_start /* get start address of text section in RAM */ - - - LA r28, bsp_section_text_size /* get size of RAM image */ - - - bl copy_image /* copy text section from ROM to RAM location */ - - -/* copy .data section from ROM to RAM location (unique for ROM startup) */ - LA r30, bsp_section_data_start /* get start address of data section in RAM */ - - - add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */ - - - LA r29, bsp_section_data_start /* get start address of data section in RAM */ - - - LA r28, bsp_section_data_size /* get size of RAM image */ - - - bl copy_image /* copy initialized data section from ROM to RAM location */ - - - LA r29, remap_rom /* get compile time address of label */ - mtlr r29 - - blrl /* now further execution RAM */ - -remap_rom: -/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */ - lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */ - - - - CLRBITS r30, r29, CSCONF_CE - stw r30, CSBOOTROM(r31) /* disable BOOT CS */ - - - - lwz r30, ADREN(r31) /* get content of ADREN */ - - - - mr r29, r30 /* move content of r30 to r29 */ - - - LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */ - andc r29,r29,r30 - - - LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */ - or r29,r29,r30 - - - stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */ - - - - lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */ - - - - SETBITS r30, r29, CSCONF_CE - stw r30, CSBOOTROM(r31) /* disable BOOT CS */ - - - -skip_ROM_start: -/* configure external DPRAM CS1 */ - LWI r30, 0xFFFFFB10 - stw r30, CS1CONF(r31) - -/* map external DPRAM (CS1) */ - LWI r30, bsp_dpram_start - srawi r30, r30, 16 - stw r30, CS1STR(r31) - - LWI r30, bsp_dpram_end - srawi r30, r30, 16 - stw r30, CS1STP(r31) - - lwz r30, ADREN(r31) /* get content of ADREN */ - - LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */ - or r30, r30,r29 - - stw r30, ADREN(r31) /* enable CS1 */ - -/* clear entire on chip SRAM (unique for ROM startup) */ - lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */ - ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l - LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */ - - bl clr_mem /* Clear onchip SRAM */ - -#else /* defined(NEED_LOW_LEVEL_INIT) */ - bl XLB_init -#endif /* defined(NEED_LOW_LEVEL_INIT) */ -/* clear .bss section (unique for ROM startup) */ - LWI r30, bsp_section_bss_start /* get start address of bss section */ - LWI r29, bsp_section_bss_size /* get size of bss section */ - - - bl clr_mem /* Clear the bss section */ - -#ifdef HAS_UBOOT - mr r3, r14 - bl bsp_uboot_copy_board_info -#endif /* HAS_UBOOT */ - -/* set stack pointer (common for RAM/ROM startup) */ - LA r1, bsp_section_text_start - addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ - /* tag TOS with a NULL pointer (termination mark for stack dump) */ - li r0, 0 - stw r0, 0(r1) - - bl __eabi /* Set up EABI and SYSV environment */ - -/* enable dynamic power management(common for RAM/ROM startup) */ - bl PPC_HID0_rd /* Get the content of HID0 */ - - SETBITS r30, r29, HID0_DPM - bl PPC_HID0_wr /* Set DPM in HID0 */ - -/* clear arguments and do further init. in C (common for RAM/ROM startup) */ - - /* Clear cmdline */ - xor r3, r3, r3 - - bl SYM (boot_card) /* Call the first C routine */ - -twiddle: - b twiddle /* We don't expect to return from boot_card but if we do */ - /* wait here for watchdog to kick us into hard reset */ - -#if defined(NEED_LOW_LEVEL_INIT) -SDRAM_init: - mflr r12 - -#if defined(MPC5200_BOARD_BRS5L) - /* set GPIO_WKUP7 pin low for 66MHz buffering */ - /* or high for 133MHz registered buffering */ - LWI r30, 0x80000000 - - lwz r29, GPIOWE(r31) - or r29,r29,r30 /* set bit 0 in r29/GPIOWE */ - stw r29,GPIOWE(r31) - - lwz r29, GPIOWOD(r31) - andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */ - stw r29,GPIOWOD(r31) - - lwz r29, GPIOWDO(r31) - andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */ - stw r29,GPIOWDO(r31) - - lwz r29, GPIOWDD(r31) - or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */ - stw r29,GPIOWDD(r31) - - /* activate MEM_CS1 output */ - lwz r29, GPIOPCR(r31) - or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */ - stw r29,GPIOPCR(r31) - -#endif - - #define SDELAY_VAL 0x00000004 - -#if defined(MPC5200_BOARD_BRS6L) - #define CFG1_VAL 0x73722930 -#else - /* - * Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 - * Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 - */ - #define CFG1_VAL 0xC4222600 -#endif - -#if defined(MPC5200_BOARD_BRS6L) - #define CFG2_VAL 0x47770000 -#else - /* Refr.2No-Read delay=0x06, Write latency=0x0 */ - /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ - /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */ - #define CFG2_VAL 0xCCC70004 -#endif - -#if defined(MPC5200_BOARD_BRS5L) - /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ - /* Refresh counter=0xFFFF */ - #define CTRL_VAL 0xD1470000 -#elif defined(MPC5200_BOARD_BRS6L) - #define CTRL_VAL 0xF15F0F00 -#else - /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ - /* Refresh counter=0xFFFF */ - #define CTRL_VAL 0xD04F0000 -#endif - -#if defined(MPC5200_BOARD_BRS6L) - /* Enable DLL, normal drive strength */ - #define EMODE_VAL 0x40010000 -#endif - -#if defined(MPC5200_BOARD_BRS6L) - /* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation/reset DLL */ - #define MODE_VAL 0x058D0000 -#else - /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */ - #define MODE_VAL 0x008D0000 -#endif - -#if defined(MPC5200_BOARD_BRS6L) - /* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation */ - #define SECOND_MODE_VAL (MODE_VAL & ~0x04000000) -#endif - - /* SDRAM initialization according to application note AN3221 */ - - /* SDRAM controller setup */ - - LWI r3, SDELAY_VAL - stw r3, SDELAY(r31) - - LWI r3, CFG1_VAL - stw r3, CFG1(r31) - - LWI r3, CFG2_VAL - stw r3, CFG2(r31) - - LWI r11, CTRL_VAL - stw r11, CTRL(r31) - lwz r3, CTRL(r31) - - /* Perform a PRECHARGE ALL command */ - ori r3, r11, CTRL_PRECHARGE_ALL - stw r3, CTRL(r31) - lwz r3, CTRL(r31) - - /* Wait at least tRP time */ - li r3, 15 - bl ndelay - -#if defined(EMODE_VAL) - /* Write EMODE register */ - LWI r3, EMODE_VAL - stw r3, MOD(r31) - - /* Wait at least tMRD time */ - li r3, 10 - bl ndelay -#endif - - /* Write MODE register */ - LWI r3, MODE_VAL - stw r3, MOD(r31) - - /* Wait at least tMRD time */ - li r3, 10 - bl ndelay - - /* Perform a PRECHARGE ALL command */ - ori r3, r11, CTRL_PRECHARGE_ALL - stw r3, CTRL(r31) - lwz r3, CTRL(r31) - - /* Wait at least tRP time */ - li r3, 15 - bl ndelay - - /* Perform an AUTO REFRESH */ - ori r3, r11, CTRL_REFRESH - stw r3, CTRL(r31) - lwz r3, CTRL(r31) - - /* Wait at least tRFC time */ - li r3, 70 - bl ndelay - - /* Perform an AUTO REFRESH */ - ori r3, r11, CTRL_REFRESH - stw r3, CTRL(r31) - lwz r3, CTRL(r31) - - /* Wait at least tRFC time */ - li r3, 70 - bl ndelay - -#if defined(SECOND_MODE_VAL) - /* Write MODE register */ - LWI r3, SECOND_MODE_VAL - stw r3, MOD(r31) -#endif - - /* Disable MODE register access */ - lis r4, CTRL_MODE_EN@h - andc r3, r11, r4 - stw r3, CTRL(r31) - lwz r3, CTRL(r31) - - mtlr r12 - blr - -copy_image: - mr r27, r28 - srwi r28, r28, 2 - mtctr r28 - - - slwi r28, r28, 2 - sub r27, r27, r28 /* maybe some residual bytes */ - - -copy_image_word: - lswi r28, r30, 0x04 - - stswi r28, r29, 0x04 /* do word copy ROM -> RAM */ - - - addi r30, r30, 0x04 /* increment source pointer */ - addi r29, r29, 0x04 /* increment destination pointer */ - - bdnz copy_image_word /* decrement ctr and branch if not 0 */ - - cmpwi r27, 0x00 /* copy image finished ? */ - beq copy_image_end; - mtctr r27 /* reload counter for residual bytes */ -copy_image_byte: - lswi r28, r30, 0x01 - - stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ - - - addi r30, r30, 0x01 /* increment source pointer */ - addi r29, r29, 0x01 /* increment destination pointer */ - - bdnz copy_image_byte /* decrement ctr and branch if not 0 */ - -copy_image_end: - blr -#endif /* defined(NEED_LOW_LEVEL_INIT) */ - -FID_DCache: - mflr r26 - - bl PPC_HID0_rd - TSTBITS r30, r29, HID0_DCE - bne FID_DCache_exit /* If data cache is switched of, skip further actions */ - - li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ - LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */ - -FID_DCache_loop_1: - lwz r27, 0(r28) /* Load data at address */ - - addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */ - subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ - cmpwi r29, 0x0 - bne FID_DCache_loop_1 /* Loop until cache size is reached */ - - li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ - LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */ - xor r27, r27, r27 -FID_DCache_loop_2: - - dcbf r27, r28 /* Flush and invalidate cache */ - - addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */ - subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ - cmpwi r29, 0x0 - bne FID_DCache_loop_2 /* Loop around until cache size is reached */ - - bl PPC_HID0_rd /* Read HID0 */ - CLRBITS r30, r29, HID0_DCE - bl PPC_HID0_wr /* Clear DCE */ - -FID_DCache_exit: - mtlr r26 - blr - -IDUL_ICache: - mflr r26 - - bl PPC_HID0_rd - TSTBITS r30, r29, HID0_ICE - bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */ - - CLRBITS r30, r29, HID0_ICE - bl PPC_HID0_wr /* Disable ICE bit */ - - SETBITS r30, r29, HID0_ICFI - bl PPC_HID0_wr /* Invalidate instruction cache */ - - CLRBITS r30, r29, HID0_ICFI - bl PPC_HID0_wr /* Disable cache invalidate */ - - CLRBITS r30, r29, HID0_ILOCK - bl PPC_HID0_wr /* Disable instruction cache lock */ - -IDUL_ICache_exit: - mtlr r26 - blr - - -TLB_init: /* Initialize translation lookaside buffers (TLBs) */ - xor r30, r30, r30 - xor r29, r29, r29 - -TLB_init_loop: - tlbie r29 - tlbsync - addi r29, r29, 0x1000 - addi r30, r30, 0x01 - cmpli 0, 0, r30, 0x0080 - bne TLB_init_loop - blr - -FPU_init: - mfmsr r30 /* get content of MSR */ - - - SETBITS r30, r29, MSR_FP - mtmsr r30 /* enable FPU and FPU exceptions */ - sync - - lfd f0, 0(r29) - fmr f1, f0 - fmr f2, f0 - fmr f3, f0 - fmr f4, f0 - fmr f5, f0 - fmr f6, f0 - fmr f7, f0 - fmr f8, f0 - fmr f9, f0 - fmr f10, f0 - fmr f11, f0 - fmr f12, f0 - fmr f13, f0 - fmr f14, f0 - fmr f15, f0 - fmr f16, f0 - fmr f17, f0 - fmr f18, f0 - fmr f19, f0 - fmr f20, f0 - fmr f21, f0 - fmr f22, f0 - fmr f23, f0 - fmr f24, f0 - fmr f25, f0 - fmr f26, f0 - fmr f27, f0 - fmr f28, f0 - fmr f29, f0 - fmr f30, f0 - fmr f31, f0 - - - mtfsfi 0, 0 /* initialize bit positons in FPSCR */ - mtfsfi 1, 0 - mtfsfi 2, 0 - mtfsfi 3, 0 - mtfsfi 4, 0 - mtfsfi 5, 0 - mtfsfi 6, 0 - mtfsfi 7, 0 - - blr - -SPRG_init: /* initialize registers */ - xor r30, r30, r30 - - mtspr PPC_XER, r30 - mtspr PPC_CTR, r30 - mtspr DSISR, r30 - mtspr PPC_DAR, r30 - mtspr PPC_DEC, r30 - mtspr SDR1, r30 - mtspr SRR0, r30 - mtspr SRR1, r30 - mtspr CSSR0, r30 - mtspr CSSR1, r30 - mtspr SPRG0, r30 - mtspr SPRG1, r30 - mtspr SPRG2, r30 - mtspr SPRG3, r30 - mtspr SPRG4, r30 - mtspr SPRG5, r30 - mtspr SPRG6, r30 - mtspr SPRG7, r30 - mtspr PPC_EAR, r30 - mtspr TBWU, r30 - mtspr TBWL, r30 - mtspr IBAT0U, r30 - mtspr IBAT0L, r30 - mtspr IBAT1U, r30 - mtspr IBAT1L, r30 - mtspr IBAT2U, r30 - mtspr IBAT2L, r30 - mtspr IBAT3U, r30 - mtspr IBAT3L, r30 - mtspr IBAT4U, r30 - mtspr IBAT4L, r30 - mtspr IBAT5U, r30 - mtspr IBAT5L, r30 - mtspr IBAT6U, r30 - mtspr IBAT6L, r30 - mtspr IBAT7U, r30 - mtspr IBAT7L, r30 - mtspr DBAT0U, r30 - mtspr DBAT0L, r30 - mtspr DBAT1U, r30 - mtspr DBAT1L, r30 - mtspr DBAT2U, r30 - mtspr DBAT2L, r30 - mtspr DBAT3U, r30 - mtspr DBAT3L, r30 - mtspr DBAT4U, r30 - mtspr DBAT4L, r30 - mtspr DBAT5U, r30 - mtspr DBAT5L, r30 - mtspr DBAT6U, r30 - mtspr DBAT6L, r30 - mtspr DBAT7U, r30 - mtspr DBAT7L, r30 - mtspr DMISS, r30 - mtspr DCMP, r30 - mtspr HASH1, r30 - mtspr HASH2, r30 - mtspr IMISS, r30 - mtspr ICMP, r30 - mtspr PPC_RPA, r30 - mtsr PPC_SR0, r30 - mtsr PPC_SR1, r30 - mtsr PPC_SR2, r30 - mtsr PPC_SR3, r30 - mtsr PPC_SR4, r30 - mtsr PPC_SR5, r30 - mtsr PPC_SR6, r30 - mtsr PPC_SR7, r30 - mtsr PPC_SR8, r30 - mtsr PPC_SR9, r30 - mtsr PPC_SR10, r30 - mtsr PPC_SR12, r30 - mtsr PPC_SR13, r30 - mtsr PPC_SR14, r30 - mtsr PPC_SR15, r30 - - - - - - blr - -PPC_HID0_rd: /* get HID0 content to r30 */ - - - mfspr r30, HID0 - - blr - - -PPC_HID0_wr: /* put r30 content to HID0 */ - - - mtspr HID0, r30 - - blr - -clr_mem: - mr r28, r29 - srwi r29, r29, 2 - mtctr r29 /* set ctr reg */ - - - slwi r29, r29, 2 - sub r28, r28, r29 /* maybe some residual bytes */ - xor r29, r29, r29 - - -clr_mem_word: - stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */ - addi r30, r30, 0x04 /* increment r30 */ - - bdnz clr_mem_word /* dec counter and loop */ - - - cmpwi r28, 0x00 /* clear mem. finished ? */ - beq clr_mem_end; - mtctr r28 /* reload counter for residual bytes */ -clr_mem_byte: - stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */ - addi r30, r30, 0x01 /* update r30 */ - - bdnz clr_mem_byte /* dec counter and loop */ - -clr_mem_end: - blr /* return */ - -XLB_init: -/* init arbiter and stuff... */ - LWI r30, 0x8000a06e - stw r30, ARBCFG(r31) /* Set ARBCFG */ - - LWI r30, 0x000000ff - stw r30, ARBMPREN(r31) /* Set ARBMPREN */ - - LWI r30, 0x00001234 - stw r30, ARBMPRIO(r31) /* Set ARBPRIO */ - - LWI r30, 0x0000001e - stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */ - - LWI r30, 4096 - stw r30, ARBADRTO(r31) /* Set ARBADRTO */ - stw r30, ARBDATTO(r31) /* Set ARBDATTO */ - - blr - -ndelay: - /* - * The maximum core frequency is 396MHz. - * We have (396MHz * 1024) / 10**9 == 405. - */ - mulli r3, r3, 405 - srwi. r3, r3, 10 - - beqlr - - mtctr r3 - -ndelay_loop: - bdnz ndelay_loop - - blr diff --git a/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am b/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am index 25607537dc..c91db0bdae 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am @@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/gen83xx/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S deleted file mode 100644 index b48a26b7c3..0000000000 --- a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S +++ /dev/null @@ -1,529 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MPC83xx BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the startup assembly code | -\*===============================================================*/ - - -#include <libcpu/powerpc-utility.h> -#include <rtems/powerpc/cache.h> -#include <bsp.h> -#include <mpc83xx/mpc83xx.h> - -.macro SET_IMM_REGW base, reg2, offset, value - LA \reg2, \value - stw \reg2,\offset(\base) -.endm - -#define REP8(l) l ; l; l; l; l; l; l; l; - -.extern boot_card -.extern MBAR - -#if defined(RESET_CONF_WRD_L) -.section ".resconf","ax" -PUBLIC_VAR (reset_conf_words) -reset_conf_words: - REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff)) - REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff)) - REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff)) - REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff)) - - REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff)) - REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff)) - REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff)) - REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff)) -#endif - -.section ".vectors","ax" -PUBLIC_VAR (reset_vec) -reset_vec: - bl rom_entry - -.section ".bsp_start_text", "ax" -PUBLIC_VAR (_start) -_start: - /* Reset time base */ - li r0, 0 - mtspr TBWU, r0 - mtspr TBWL, r0 - -#ifdef HAS_UBOOT - mr r14, r3 -#endif /* HAS_UBOOT */ - - /* - * basic CPU setup: - * init MSR - */ - mfmsr r30 - SETBITS r30, r29, MSR_ME|MSR_RI - CLRBITS r30, r29, MSR_IP|MSR_EE - mtmsr r30 /* Set RI/ME, Clr EE in MSR */ - - b start_rom_skip - -PUBLIC_VAR (rom_entry) -rom_entry: - /* - * basic CPU setup: - * init MSR - */ - mfmsr r30 - SETBITS r30, r29, MSR_ME|MSR_RI - CLRBITS r30, r29, MSR_IP|MSR_EE - mtmsr r30 /* Set RI/ME, Clr EE in MSR */ - - /* - * ROM startup: remap IMMR to 0xE0000000 - * use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR" - */ - LWI r30,IMMRBAR_DEFAULT - LWI r31,IMMRBAR - lwz r29,0(r30) - stw r31,0(r30) -#if 0 - lwz r29,0(r28) /* read from ROM... */ -#endif - isync - lwz r29,0(r31) /* read from IMMRBAR... */ - isync - /* - * NOTE: now r31 points to onchip registers - */ - /* - * we start from 0x100, so ROM is currently mapped to - * 0x00000000.. - * in the next step, ROM will be remapped to its final location - * at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value) - * and we jump to that location. - * then we remove the ROM mapping to zero - */ -#ifdef LBLAWBAR0_VAL - SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL -#endif -#ifdef LBLAWAR0_VAL - SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL -#endif - - - /* - * ROM startup: jump to code final ROM location - */ - LA r20, bsp_rom_start /* ROM-RAM reloc in r20 */ - LA r29, start_code_in_rom /* get compile time addr of label */ - add r29,r20,r29 /* compute exec address */ - mtlr r29 - blr /* now further execution in upper ROM */ - -start_code_in_rom: - -#ifdef LBLAWBAR0_VAL - SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL -#endif -#ifdef LBLAWAR0_VAL - SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL -#endif - -/* - * Local access window 1 is a special case since we used it for a temporary - * mapping. If we do not use it then restore the reset value. - */ -#ifdef LBLAWBAR1_VAL - SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL -#else - SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,0 -#endif -#ifdef LBLAWAR1_VAL - SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR1_VAL -#else - SET_IMM_REGW r31,r30,LBLAWAR1_OFF,0 -#endif - -#ifdef LBLAWBAR2_VAL - SET_IMM_REGW r31,r30,LBLAWBAR2_OFF,LBLAWBAR2_VAL -#endif -#ifdef LBLAWAR2_VAL - SET_IMM_REGW r31,r30,LBLAWAR2_OFF,LBLAWAR2_VAL -#endif -#ifdef LBLAWBAR3_VAL - SET_IMM_REGW r31,r30,LBLAWBAR3_OFF,LBLAWBAR3_VAL -#endif -#ifdef LBLAWAR3_VAL - SET_IMM_REGW r31,r30,LBLAWAR3_OFF,LBLAWAR3_VAL -#endif - /* - * ROM startup: init bus system - */ -#ifdef BR0_VAL - SET_IMM_REGW r31,r30,BR0_OFF,BR0_VAL -#endif -#ifdef OR0_VAL - SET_IMM_REGW r31,r30,OR0_OFF,OR0_VAL -#endif -#ifdef BR1_VAL - SET_IMM_REGW r31,r30,BR1_OFF,BR1_VAL -#endif -#ifdef OR1_VAL - SET_IMM_REGW r31,r30,OR1_OFF,OR1_VAL -#endif -#ifdef BR2_VAL - SET_IMM_REGW r31,r30,BR2_OFF,BR2_VAL -#endif -#ifdef OR2_VAL - SET_IMM_REGW r31,r30,OR2_OFF,OR2_VAL -#endif -#ifdef BR3_VAL - SET_IMM_REGW r31,r30,BR3_OFF,BR3_VAL -#endif -#ifdef OR3_VAL - SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL -#endif -#ifdef BR4_VAL - SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL -#endif -#ifdef OR4_VAL - SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL -#endif -#ifdef BR5_VAL - SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL -#endif -#ifdef OR5_VAL - SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL -#endif - /* - * ROM startup: init SDRAM access window - */ -#ifdef DDRLAWBAR0_VAL - SET_IMM_REGW r31,r30,DDRLAWBAR0_OFF,DDRLAWBAR0_VAL -#endif -#ifdef DDRLAWAR0_VAL - SET_IMM_REGW r31,r30,DDRLAWAR0_OFF,DDRLAWAR0_VAL -#endif -#ifdef DDRLAWBAR1_VAL - SET_IMM_REGW r31,r30,DDRLAWBAR1_OFF,DDRLAWBAR1_VAL -#endif -#ifdef DDRLAWAR1_VAL - SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL -#endif - /* - * ROM startup: init refresh interval - */ -#ifdef MRPTR_VAL - SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL -#endif - /* - * ROM startup: init SDRAM - */ -#ifdef LSRT_VAL - SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL -#endif -#ifdef LSDMR_VAL - SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL -#endif -#ifdef CS0_BNDS_VAL - SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL -#endif -#ifdef CS1_BNDS_VAL - SET_IMM_REGW r31,r30,CS1_BNDS_OFF,CS1_BNDS_VAL -#endif -#ifdef CS2_BNDS_VAL - SET_IMM_REGW r31,r30,CS2_BNDS_OFF,CS2_BNDS_VAL -#endif -#ifdef CS3_BNDS_VAL - SET_IMM_REGW r31,r30,CS3_BNDS_OFF,CS3_BNDS_VAL -#endif -#ifdef CS0_CONFIG_VAL - SET_IMM_REGW r31,r30,CS0_CONFIG_OFF,CS0_CONFIG_VAL -#endif -#ifdef CS1_CONFIG_VAL - SET_IMM_REGW r31,r30,CS1_CONFIG_OFF,CS1_CONFIG_VAL -#endif -#ifdef CS2_CONFIG_VAL - SET_IMM_REGW r31,r30,CS2_CONFIG_OFF,CS2_CONFIG_VAL -#endif -#ifdef CS3_CONFIG_VAL - SET_IMM_REGW r31,r30,CS3_CONFIG_OFF,CS3_CONFIG_VAL -#endif -#ifdef TIMING_CFG_3_VAL - SET_IMM_REGW r31,r30,TIMING_CFG_3_OFF,TIMING_CFG_3_VAL -#endif -#ifdef TIMING_CFG_0_VAL - SET_IMM_REGW r31,r30,TIMING_CFG_0_OFF,TIMING_CFG_0_VAL -#endif -#ifdef TIMING_CFG_1_VAL - SET_IMM_REGW r31,r30,TIMING_CFG_1_OFF,TIMING_CFG_1_VAL -#endif -#ifdef TIMING_CFG_2_VAL - SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL -#endif -#ifdef DDRCDR_VAL - SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL -#endif -#ifdef DDR_SDRAM_CFG_2_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL -#endif -#ifdef DDR_SDRAM_MODE_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_OFF,DDR_SDRAM_MODE_VAL -#endif -#ifdef DDR_SDRAM_MODE_2_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_2_OFF,DDR_SDRAM_MODE_2_VAL -#endif -#ifdef DDR_SDRAM_MD_CNTL_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_MD_CNTL_OFF,DDR_SDRAM_MD_CNTL_VAL -#endif -#ifdef DDR_SDRAM_MD_ITVL_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_MD_ITVL_OFF,DDR_SDRAM_MD_ITVL_VAL -#endif -#ifdef DDR_SDRAM_CLK_CNTL_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL -#endif -#ifdef DDR_SDRAM_CFG_2_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT -#endif - -#ifdef DDR_ERR_DISABLE_VAL - /* - * disable detect of RAM errors - */ - SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL -#endif -#ifdef DDR_SDRAM_DATA_INIT_VAL - /* - * set this value to initialize memory - */ - SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL -#endif -#ifdef DDR_SDRAM_INIT_ADDR_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL -#endif -#ifdef DDR_SDRAM_CFG_VAL - /* - * config DDR SDRAM - */ - SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN - /* - * FIXME: wait 200us - */ - /* - * enable DDR SDRAM - */ - SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN - /* - * wait, until DDR_SDRAM_CFG_2_D_INIT is cleared - */ -1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31) - andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT - bne 1b -#endif -#ifdef DDR_ERR_DISABLE_VAL2 - /* - * enable detect of some RAM errors - */ - SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2 -#endif -#ifdef DDR_SDRAM_INTERVAL_VAL - /* - * set the refresh interval - */ - SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL -#endif -start_rom_skip: - /* - * determine current execution address offset - */ - bl start_rom_skip1 -start_rom_skip1: - mflr r20 - LA r30,start_rom_skip1 - sub. r20,r20,r30 - /* - * execution address offset == 0? - * then do not relocate code and data - */ - beq start_code_in_ram - /* - * ROM or relocatable startup: copy startup code to SDRAM - */ - /* get start address of start section in RAM */ - LA r29, bsp_section_start_begin - /* get start address of start section in ROM (add reloc offset) */ - add r30, r20, r29 - /* get size of startup code */ - LA r28, bsp_section_start_end - sub 28,r28,r29 - /* copy startup code from ROM to RAM location */ - bl copy_image - - /* - * ROM startup: jump to code copy in SDRAM - */ - /* get compile time address of label */ - LA r29, copy_rest_of_text - mtlr r29 - blr /* now further execution RAM */ -copy_rest_of_text: - LWI r31,IMMRBAR -#ifdef LCRR_VAL - SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL -#endif - /* - * ROM or relocatable startup: copy rest of code to SDRAM - */ - /* get start address of rest of loadable sections in RAM */ - LA r29, bsp_section_text_begin - /* get start address of loadable sections in ROM (add reloc offset) */ - add r30, r20, r29 - /* get size of rest of loadable sections */ - LA r28, bsp_section_data_end - sub r28,r28,r29 - bl copy_image /* copy text section from ROM to RAM location */ - -start_code_in_ram: - - /* - * ROM/RAM startup: clear bss in SDRAM - */ - LA r3, bsp_section_sbss_begin /* get start address of bss section */ - LA r4, bsp_section_bss_end /* get end address of bss section */ - sub r4, r4, r3 /* get size of bss section */ - bl mpc83xx_zero_4 /* Clear the bss section */ - -#ifdef HAS_UBOOT - mr r3, r14 - bl bsp_uboot_copy_board_info -#endif /* HAS_UBOOT */ - - /* Read-only small data */ - LA r2, _SDA2_BASE_ - - /* Read-write small data */ - LA r13, _SDA_BASE_ - - /* Clear cmdline */ - li r3, 0 - - /* Set start stack pointer */ - LA r1, start_stack_end - stwu r3, -4(r1) - stwu r3, -4(r1) - - /* Call the first C routine */ - bl SYM (boot_card) - -twiddle: - /* We don't expect to return from boot_card but if we do */ - /* wait here for watchdog to kick us into hard reset */ - b twiddle - -copy_image: - cmpwi r28, 0 - beqlr - - mr r27, r28 - srwi r28, r28, 2 - mtctr r28 - - slwi r28, r28, 2 - sub r27, r27, r28 /* maybe some residual bytes */ -copy_image_word: - lswi r28, r30, 0x04 - - stswi r28, r29, 0x04 /* do word copy ROM -> RAM */ - - - addi r30, r30, 0x04 /* increment source pointer */ - addi r29, r29, 0x04 /* increment destination pointer */ - - bdnz copy_image_word /* decrement ctr and branch if not 0 */ - - cmpwi r27, 0x00 /* copy image finished ? */ - beq copy_image_end; - mtctr r27 /* reload counter for residual bytes */ -copy_image_byte: - lswi r28, r30, 0x01 - - stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ - - - addi r30, r30, 0x01 /* increment source pointer */ - addi r29, r29, 0x01 /* increment destination pointer */ - - bdnz copy_image_byte /* decrement ctr and branch if not 0 */ - -copy_image_end: - blr - - -/** - * @fn int mpc83xx_zero_4( void *dest, size_t n) - * - * @brief Zero all @a n bytes starting at @a dest with 4 byte writes. - * - * The address @a dest has to be aligned on 4 byte boundaries. The size @a n - * must be evenly divisible by 4. - */ -GLOBAL_FUNCTION mpc83xx_zero_4 - /* Create zero */ - xor r0, r0, r0 - - /* Set offset */ - xor r5, r5, r5 - - /* Loop counter for the first bytes up to 16 bytes */ - rlwinm. r9, r4, 30, 30, 31 - beq mpc83xx_zero_4_more - mtctr r9 - -mpc83xx_zero_4_head: - - stwx r0, r3, r5 - addi r5, r5, 4 - bdnz mpc83xx_zero_4_head - -mpc83xx_zero_4_more: - - /* More than 16 bytes? */ - srwi. r9, r4, 4 - beqlr - mtctr r9 - - /* Set offsets */ - addi r6, r5, 4 - addi r7, r5, 8 - addi r8, r5, 12 - -mpc83xx_zero_4_tail: - - stwx r0, r3, r5 - addi r5, r5, 16 - stwx r0, r3, r6 - addi r6, r6, 16 - stwx r0, r3, r7 - addi r7, r7, 16 - stwx r0, r3, r8 - addi r8, r8, 16 - bdnz mpc83xx_zero_4_tail - - /* Return */ - blr - -.section ".bsp_rwextra", "aw", @nobits - - /* Start stack area */ -.align 4 -.space 4096 -start_stack_end: diff --git a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am index be8b8388ad..32c87428cf 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am +++ b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am b/c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am index 3ed73e63c2..496d8c418c 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am @@ -15,15 +15,15 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) -vectors_entry.$(OBJEXT): ../shared/start/vectors_entry.S +vectors_entry.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/vectors_entry.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += vectors_entry.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am index 9f6798c1bb..4db2f8ac1d 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am @@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/mpc55xxevb/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/start/start.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/start/start.S deleted file mode 100644 index 0a757e7ada..0000000000 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/start/start.S +++ /dev/null @@ -1,299 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx_asm - * - * @brief Boot and system start code. - */ - -/* - * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bspopts.h> -#include <bsp/linker-symbols.h> -#include <libcpu/powerpc-utility.h> - -#if MPC55XX_CHIP_FAMILY != 551 - #define HAS_SPE -#endif - -#if MPC55XX_CHIP_FAMILY == 564 - #define INIT_REGISTERS_FOR_LSM -#endif - -#ifdef HAS_SPE - #define ZERO_GPR(reg) evxor reg, reg, reg -#else - #define ZERO_GPR(reg) xor reg, reg, reg -#endif - - .extern __eabi - .extern boot_card - .extern bsp_ram_start - .extern mpc55xx_start_config_mmu_early - .extern mpc55xx_start_config_mmu_early_count - .extern mpc55xx_start_early - - .globl _start - .globl mpc55xx_start_load_section - .globl mpc55xx_start_mmu_apply_config - -#ifdef MPC55XX_BOOTFLAGS - .globl mpc55xx_bootflag_0 - .globl mpc55xx_bootflag_1 -#endif - - .section ".bsp_start_text", "ax" - - /* BAM: RCHW */ - .int 0x005a0000 - - /* BAM: Address of start instruction */ - .int _start - -#ifdef MPC55XX_BOOTFLAGS - /* - * We skip over the next two boot flag words to the next 64-bit - * aligned start address. It is 64-bit aligned to play well with - * FLASH programming. These boot flags can be set by debuggers - * and emulators to customize boot. Currently bit0 of - * bootflag_0 means to "skip setting up the MMU", allowing - * external MMU setup in a debugger before branching to 0x10. - * This can be used e.g., to map FLASH into RAM. - */ -mpc55xx_bootflag_0: - .int 0xffffffff -mpc55xx_bootflag_1: - .int 0xffffffff -#endif - -_start: - -#ifdef MPC55XX_ENABLE_START_PROLOGUE - bl mpc55xx_start_prologue -#endif - -#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT - - /* Enable SPE */ -#ifdef HAS_SPE - mfmsr r3 - oris r3, r3, MSR_SPE >> 16 - mtmsr r3 - isync -#endif - - /* - * Initialization of core registers according to "e200z4 Power - * Architecture Core Reference Manual" section 2.6 "Reset Settings" - * table 2-16 "Reset Settings of e200 Resources". This is necessary - * for lock step mode (LSM). - */ - ZERO_GPR(r0) -#ifdef INIT_REGISTERS_FOR_LSM - ZERO_GPR(r1) - ZERO_GPR(r2) - ZERO_GPR(r4) - ZERO_GPR(r5) - ZERO_GPR(r6) - ZERO_GPR(r7) - ZERO_GPR(r8) - ZERO_GPR(r9) - ZERO_GPR(r10) - ZERO_GPR(r11) - ZERO_GPR(r12) - ZERO_GPR(r13) - ZERO_GPR(r14) - ZERO_GPR(r15) - ZERO_GPR(r16) - ZERO_GPR(r17) - ZERO_GPR(r18) - ZERO_GPR(r19) - ZERO_GPR(r20) - ZERO_GPR(r21) - ZERO_GPR(r22) - ZERO_GPR(r23) - ZERO_GPR(r24) - ZERO_GPR(r25) - ZERO_GPR(r26) - ZERO_GPR(r27) - ZERO_GPR(r28) - ZERO_GPR(r29) - ZERO_GPR(r30) - ZERO_GPR(r31) - mtcrf 0xff, r0 - mtcsrr0 r0 - mtcsrr1 r0 - mtctr r0 - mtspr FSL_EIS_DBCNT, r0 - mtspr DEAR_BOOKE, r0 - mtdec r0 - mtspr BOOKE_DECAR, r0 - mtspr FSL_EIS_DSRR0, r0 - mtspr FSL_EIS_DSRR1, r0 - mtspr BOOKE_DVC1, r0 - mtspr BOOKE_DVC2, r0 - mtspr BOOKE_IVPR, r0 - mtlr r0 - mtspr FSL_EIS_MCAR, r0 - mtmcsrr0 r0 - mtmcsrr1 r0 - mtspr SPRG0, r0 - mtspr SPRG1, r0 - mtspr SPRG2, r0 - mtspr SPRG3, r0 - mtspr SPRG4, r0 - mtspr SPRG5, r0 - mtspr SPRG6, r0 - mtspr SPRG7, r0 - mtspr FSL_EIS_SPRG8, r0 - mtspr FSL_EIS_SPRG9, r0 - mtsrr0 r0 - mtsrr1 r0 - mtspr USPRG0, r0 -#ifdef HAS_SPE - evmra r0, r0 -#endif -#endif /* INIT_REGISTERS_FOR_LSM */ - mtspr TBWL, r0 - mtspr TBWU, r0 - - /* Enable time base */ - mfspr r3, HID0 - ori r3, r3, 0x4000 - mtspr HID0, r3 - - /* - * Enable branch prediction. - * - * Errata e4396: e200z7: Erroneous Address Fetch - * - * The propose workaround does not work. - */ -#if MPC55XX_CHIP_FAMILY != 567 - LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BALLOC_ALL | FSL_EIS_BUCSR_BPRED_NOT_TAKEN | FSL_EIS_BUCSR_BPEN - mtspr FSL_EIS_BUCSR, r3 -#endif - -#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ - - /* MMU early initialization */ - LA r3, mpc55xx_start_config_mmu_early - LW r4, mpc55xx_start_config_mmu_early_count - bl mpc55xx_start_mmu_apply_config - -#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT - - /* Initialize intermediate stack (ECC) */ - - LA r3, bsp_ram_start - addi r4, r3, MPC55XX_EARLY_STACK_SIZE - -zero_intermediate_stack_loop: - -#ifdef HAS_SPE - evstdd r0, 0(r3) - evstdd r0, 8(r3) - evstdd r0, 16(r3) - evstdd r0, 24(r3) -#else - stw r0, 0(r3) - stw r0, 4(r3) - stw r0, 8(r3) - stw r0, 12(r3) - stw r0, 16(r3) - stw r0, 20(r3) - stw r0, 24(r3) - stw r0, 28(r3) -#endif - addi r3, r3, 32 - cmpw cr7, r3, r4 - bne cr7, zero_intermediate_stack_loop - subi r1, r3, 16 - -#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ - - /* Next steps in C */ - bl mpc55xx_start_early - - /* Initialize start stack */ - LA r1, start_stack_end - subi r1, r1, 16 - li r0, 0 - stw r0, 0(r1) - - /* - * Load sections. This must be performed after the stack switch - * because it may overwrite the initial stack. - */ - LA r3, bsp_section_fast_text_begin - LA r4, bsp_section_fast_text_load_begin - LA r5, bsp_section_fast_text_size - bl mpc55xx_start_load_section - LA r3, bsp_section_fast_data_begin - LA r4, bsp_section_fast_data_load_begin - LA r5, bsp_section_fast_data_size - bl mpc55xx_start_load_section - LA r3, bsp_section_data_begin - LA r4, bsp_section_data_load_begin - LA r5, bsp_section_data_size - bl mpc55xx_start_load_section - - /* Set up EABI and SYSV environment */ - bl __eabi - - /* Clear command line */ - li r3, 0 - - /* Start RTEMS */ - bl boot_card - - /* Spin around */ -twiddle: - - b twiddle - -mpc55xx_start_mmu_apply_config: - - cmpwi cr7, r4, r0 - beqlr cr7 - mtctr r4 - -mmu_init_loop: - - lwz r4, 0(r3) - lwz r5, 4(r3) - lwz r6, 8(r3) - lwz r7, 12(r3) - mtspr FSL_EIS_MAS0, r4 - mtspr FSL_EIS_MAS1, r5 - mtspr FSL_EIS_MAS2, r6 - mtspr FSL_EIS_MAS3, r7 - tlbwe - addi r3, r3, 16 - bdnz mmu_init_loop - blr - -mpc55xx_start_load_section: - cmpw cr7, r3, r4 - beqlr cr7 - b memcpy - - /* Start stack area */ - - .section ".bsp_rwextra", "aw", @nobits - .align 4 - .space 4096 - -start_stack_end: diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am b/c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am index 621e61e350..03ef7c2ad8 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am @@ -8,13 +8,13 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/mpc8260ads/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) project_lib_DATA += linkcmds -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S b/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S deleted file mode 100644 index 4fdc21cea9..0000000000 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S +++ /dev/null @@ -1,168 +0,0 @@ -/* start.S - * - * Modified for the Motorola PQII ADS board by - * Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. - * Surrey Satellite Technology Limited - * - * I have a proprietary bootloader programmed into the flash - * on the board which initialises the SDRAM prior to calling - * this function. - * - * This file is based on the one by Jay Monkman (jmonkman@fracsa.com) - * which in turn was based on the dlentry.s file for the Papyrus BSP, - * written by: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - */ - -#include <rtems/asm.h> - -/* - * The initial stack is set to run BELOW the code base address. - * (between the vectors and text sections) - * - * The entry veneer has to clear the BSS and copy the read only - * version of the data segment to the correct location. - */ - - .section ".entry" /* This might have to be the first thing in the - * text section. At one time, it had to be - * first, but I don't believe it is true - * any more. */ - PUBLIC_VAR (start) -SYM(start): - bl .startup -base_addr: - -/* - * Parameters from linker - */ -toc_pointer: - .long s.got -bss_length: - .long bss.size -bss_addr: - .long bss.start - -PUBLIC_VAR (data_length ) -data_length: - .long data.size -PUBLIC_VAR (data_addr ) -data_addr: - .long data.start - -PUBLIC_VAR (text_addr) -text_addr: - .long text.start - -PUBLIC_VAR (text_length) -text_length: - .long text.size - -/* - * Initialization code - */ -.startup: - /* Get start address */ - mflr r1 - - /* -------------------------------------------------- - * Clear MSR[EE] to disable interrupts - * Clear MSR[IP] bit to put vectors at 0x00000000 - * Set MSR[FP] to enable FPU - not on my eval board! - * -------------------------------------------------- */ - mfmsr r5 - lis r13, 0xFFFF - ori r13, r13, 0x7FBF - and r5, r5, r13 /* Clear EE and IP */ -#if 1 - ori r5, r5, 0x2000 /* Enable FPU */ -#endif - mtmsr r5 - -#ifdef ENABLE_CACHE - /* Enable caches */ - mfspr r5, 1008 - ori r5, r5, 0x8000 - isync - mtspr 1008, r5 - -/* Leave D-cache disabled for now */ -#if 0 - ori r5, r5, 0x4000 - sync - mtspr 1008, r5 -#endif -#endif - - /*-------------------------------------------------- - * Set up the power management modes - * The 8260 has a dynamic power management mode that - * is automatically invoked if the unit is idle. - * We invoke the NAP mode in the RTEMS idle task. - *-------------------------------------------------- */ - - lis r13, 0x0050 /* set nap mode and DPM */ - or r5, r5, r13 - mtspr 1008, r5 - - /*-------------------------------------------------- - * - *-------------------------------------------------- */ - - /* clear the bss section */ - bl bssclr - -/* - * C_setup. - */ - - /* set toc */ - lwz r2, toc_pointer-base_addr(r1) - - /* Set up stack pointer = beginning of text section - 56 */ - addi r1, r1, -56-4 - - /* Clear cmdline */ - xor r3, r3, r3 - - .extern SYM (boot_card) - bl SYM (boot_card) /* call the first C routine */ - - /* we don't expect to return from boot_card but if we do */ - /* wait here for watchdog to kick us into hard reset */ - -twiddle: - b twiddle - -/* - * bssclr - zero out bss - */ -bssclr: - lwz r4, bss_addr-base_addr(r1) /* Start of bss */ - lwz r5, bss_length-base_addr(r1) /* Length of bss */ - - rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r5 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r4,0x4 /* store r6 */ - addi r4,r4,0x4 /* update r2 */ - - bdnz clear_bss /* dec counter and loop */ - blr /* return */ diff --git a/c/src/lib/libbsp/powerpc/mvme3100/Makefile.am b/c/src/lib/libbsp/powerpc/mvme3100/Makefile.am index 6491639c3f..a94f30f667 100644 --- a/c/src/lib/libbsp/powerpc/mvme3100/Makefile.am +++ b/c/src/lib/libbsp/powerpc/mvme3100/Makefile.am @@ -11,13 +11,13 @@ noinst_PROGRAMS = project_lib_DATA = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/mvme3100/start/start.S $(CPPASCOMPILE) -o $@ -c $< -preload.$(OBJEXT): ../shared/start/preload.S +preload.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/preload.S $(CPPASCOMPILE) -DASM -o $@ -c $< -vectors_entry.$(OBJEXT): ../shared/start/vectors_entry.S +vectors_entry.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/vectors_entry.S $(CPPASCOMPILE) -o $@ -c $< motld_start.$(OBJEXT): preload.$(OBJEXT) vectors_entry.$(OBJEXT) \ @@ -26,7 +26,7 @@ motld_start.$(OBJEXT): preload.$(OBJEXT) vectors_entry.$(OBJEXT) \ project_lib_DATA += motld_start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/mvme3100/start/start.S b/c/src/lib/libbsp/powerpc/mvme3100/start/start.S deleted file mode 100644 index 493720e0c7..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme3100/start/start.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * start.S : RTEMS entry point - * - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified for mvme3100 by T. Straumann, 2007. - * - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> -#include <rtems/powerpc/powerpc.h> - -#include <bspopts.h> - -#define SYNC \ - sync; \ - isync - -#define KERNELBASE 0x0 - -/* cannot include <bsp.h> from assembly :-( */ -#ifndef BSP_8540_CCSR_BASE -#define BSP_8540_CCSR_BASE 0xe1000000 -#endif - -#define ERR_DISABLE_REG (BSP_8540_CCSR_BASE + 0x2e44) - - .text - .globl __rtems_entry_point - .type __rtems_entry_point,@function -__rtems_entry_point: - mr r31,r3 - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - /* disable checking for memory-select errors; motload has all TLBs - * mapping a possible larger area as memory (not-guarded, caching-enabled) - * than actual physical memory is available. - * In case of speculative loads this may cause 'memory-select' errors - * which seem to raise 'core_fault_in' (found no description in - * the manual but I experienced this problem). - * Such errors (if HID1[RFXE] is clear) may *stall* execution - * leading to mysterious 'hangs'. - * Note: enabling HID1[RFXE] at this point makes no sense since - * exceptions are not configured yet. Therefore we disable - * memory-select errors. - * Eventually (bspstart.c) we want to delete TLB entries for - * which no physical memory is present. - */ - lis r3, ERR_DISABLE_REG@ha - lwz r4, ERR_DISABLE_REG@l(r3) - /* disable memory-select errors */ - ori r4, r4, 1 - stw r4, ERR_DISABLE_REG@l(r3) - - /* Use MotLoad's TLB setup for now; caches are on already */ - bl __eabi /* setup EABI and SYSV environment */ - bl zero_bss - /* - * restore original args - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl save_boot_params - addis r9,r0, (__stack-PPC_MINIMUM_STACK_FRAME_SIZE)@ha - addi r9,r9, (__stack-PPC_MINIMUM_STACK_FRAME_SIZE)@l - /* align down to 16-bytes */ - li r5, (CPU_STACK_ALIGNMENT - 1) - andc r1, r9, r5 - - /* NULL ptr to back chain */ - li r0, 0 - stw r0, 0(r1) - - /* - * We are now in a environment that is totally independent from - * bootloader setup. - */ - /* pass result of 'save_boot_params' to 'boot_card' in R3 */ - bl boot_card - /* point of no return: reset board here ? */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am b/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am index 6873db182f..6bc09151ff 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am +++ b/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am @@ -48,7 +48,7 @@ librtemsbsp_a_SOURCES += tod/todcfg.c # vectors librtemsbsp_a_SOURCES += vectors/exceptionhandler.c -librtemsbsp_a_SOURCES += ../shared/start/vectors_entry.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/start/vectors_entry.S # GT64260 librtemsbsp_a_SOURCES += GT64260/GT64260TWSI.c @@ -60,12 +60,12 @@ librtemsbsp_a_SOURCES += network/if_1GHz/if_wm.c librtemsbsp_a_SOURCES += network/if_1GHz/pci_map.c endif -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = rtems_crti.$(OBJEXT) noinst_PROGRAMS += mvme5500start.$(OBJEXT) -mvme5500start___OBJEXT__SOURCES = ../shared/start/preload.S start/start.S +mvme5500start___OBJEXT__SOURCES = ../../../../../../bsps/powerpc/shared/start/preload.S ../../../../../../bsps/powerpc/mvme5500/start/start.S mvme5500start___OBJEXT__CPPFLAGS = $(AM_CPPFLAGS) mvme5500start___OBJEXT__LDFLAGS = $(RTEMS_RELLDFLAGS) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/start/start.S b/c/src/lib/libbsp/powerpc/mvme5500/start/start.S deleted file mode 100644 index 5990c7e2d4..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/start/start.S +++ /dev/null @@ -1,208 +0,0 @@ -/* - * start.S : RTEMS entry point - * - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * S. Kate Feng <feng1@bnl.gov>, April 2004 - * Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> -#include <rtems/powerpc/powerpc.h> - -#include <libcpu/io.h> -#include <libcpu/bat.h> -#include <bspopts.h> - -#define SYNC \ - sync; \ - isync - -#define KERNELBASE 0x0 -#define MEM256MB 0x10000000 - -#define MONITOR_ENTER \ - mfmsr r10 ; \ - ori r10,r10,MSR_IP ; \ - mtmsr r10 ; \ - li r10,0x63 ; \ - sc - - .text - .globl __rtems_entry_point - .type __rtems_entry_point,@function -__rtems_entry_point: -#ifdef DEBUG_EARLY_START - MONITOR_ENTER -#endif - -/* - * PREP - * This is jumped to on prep systems right after the kernel is relocated - * to its proper place in memory by the boot loader. The expected layout - * of the regs is: - * r3: ptr to residual data - * r4: initrd_start or if no initrd then 0 - * r5: initrd_end - unused if r4 is 0 - * r6: Start of command line string - * r7: End of command line string - * - * The Prep boot loader insure that the MMU is currently off... - * - */ - - mr r31,r3 /* save parameters */ - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - -#ifdef __ALTIVEC__ - /* enable altivec; gcc may use it! */ - mfmsr r0 - oris r0, r0, (1<<(31-16-6)) - mtmsr r0 - isync - /* - * set vscr and vrsave to known values - */ - li r0, 0 - mtvrsave r0 - vxor 0,0,0 - mtvscr 0 -#endif - - /* - * Make sure we have nothing in BATS and TLB - */ - bl CPU_clear_bats_early - bl flush_tlbs -/* - * Use the first pair of BAT registers to map the 1st 256MB - * of RAM to KERNELBASE. - */ - lis r11,KERNELBASE@h -/* set up BAT registers for 604 */ - ori r11,r11,0x1ffe - li r8,2 /* R/W access */ - isync - mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ - mtspr DBAT0U,r11 /* bit in upper BAT register */ - mtspr IBAT0L,r8 - mtspr IBAT0U,r11 - isync -/* - * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB - * of RAM to 0x10000000. - */ - lis r11,MEM256MB@h - ori r11,r11,0x1ffe /* set up BAT1 registers for 604+ */ - lis r8,MEM256MB@h - ori r8,r8,2 - isync - mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */ - mtspr DBAT1U,r11 /* bit in upper BAT register */ - mtspr IBAT1L,r8 - mtspr IBAT1U,r11 - isync - -/* - * we now have the two 256M of ram mapped with the bats. We are still - * running on the bootloader stack and cannot switch to an RTEMS allocated - * init stack before copying the residual data that may have been set just - * after rtems_end address. This bug has been experienced on MVME2304. Thank - * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and - * suggesting the appropriate code. - */ - -enter_C_code: - bl MMUon - bl __eabi /* setup EABI and SYSV environment */ - bl zero_bss - /* - * restore prep boot params - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl save_boot_params - /* - * stack = &__rtems_end + 4096 - */ - addis r9,r0, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@ha - addi r9,r9, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@l - /* - * align initial stack - * (we hope that the bootloader stack was 16-byte aligned - * or we haven't used altivec yet...) - */ - li r0, (CPU_STACK_ALIGNMENT-1) - andc r1, r9, r0 - /* - * NULL ptr to back chain - */ - li r0, 0 - stw r0, 0(r1) - - /* - * We are now in a environment that is totally independent from - * bootloader setup. - */ - /* pass result of 'save_boot_params' to 'boot_card' in R3 */ - bl boot_card - bl _return_to_ppcbug - - .globl MMUon - .type MMUon,@function -MMUon: - mfmsr r0 - ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP -#if (PPC_HAS_FPU == 0) - xori r0, r0, MSR_EE | MSR_IP | MSR_FP -#else - xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 -#endif - mflr r11 - mtsrr0 r11 - mtsrr1 r0 - SYNC - rfi - - .globl MMUoff - .type MMUoff,@function -MMUoff: - mfmsr r0 - ori r0,r0,MSR_IR| MSR_DR | MSR_IP - mflr r11 - xori r0,r0,MSR_IR|MSR_DR - mtsrr0 r11 - mtsrr1 r0 - SYNC - rfi - - .globl _return_to_ppcbug - .type _return_to_ppcbug,@function - -_return_to_ppcbug: - mflr r30 - bl MMUoff - MONITOR_ENTER - bl MMUon - mtctr r30 - bctr - -flush_tlbs: - lis r20, 0x1000 -1: addic. r20, r20, -0x1000 - tlbie r20 - bgt 1b - sync - blr diff --git a/c/src/lib/libbsp/powerpc/psim/Makefile.am b/c/src/lib/libbsp/powerpc/psim/Makefile.am index 5b7e65463e..575d939f2a 100644 --- a/c/src/lib/libbsp/powerpc/psim/Makefile.am +++ b/c/src/lib/libbsp/powerpc/psim/Makefile.am @@ -7,11 +7,11 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/psim/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/psim/start/start.S b/c/src/lib/libbsp/powerpc/psim/start/start.S deleted file mode 100644 index 918321af5f..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/start/start.S +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> -#include <libcpu/io.h> -#include "ppc-asm.h" - - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long bsp_section_sbss_begin - -.Lend = .-.LCTOC1 - .long bsp_section_bss_end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl __rtems_entry_point - .type __rtems_entry_point,@function -__rtems_entry_point: -#if 1 - .globl _start - .type _start,@function -_start: -#endif - bl .Laddr /* get current address */ -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: -#ifdef __ALTIVEC__ - /* enable altivec; this requires the ALTIVEC user - * extension to be installed in the user extension - * slot 0! - */ - mfmsr r0 - oris r0, r0, (1<<(31-16-6)) - mtmsr r0 - isync - /* - * set vscr and vrsave to known values - */ - li r0, 0 - mtvrsave r0 - vxor 0,0,0 - mtvscr 0 -#endif - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - /* align */ - li r3, CPU_STACK_ALIGNMENT-1 - andc sp, sp, r3 - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-CPU_STACK_ALIGNMENT(sp) /* push another stack frame */ - bl FUNC_NAME(__eabi) - - /* Let her rip */ - li r3, 0 /* command line */ - bl FUNC_NAME(boot_card) - - .globl FUNC_NAME(bsp_reset) -FUNC_NAME(bsp_reset): - li 10,99 /* 0x63 */ - sc - -.Lstart: - .size _start,.Lstart-_start - - /* Start stack area */ -.section ".bsp_rwextra", "aw", @nobits -.align 4 -.space 4096 -__stack: diff --git a/c/src/lib/libbsp/powerpc/qemuppc/Makefile.am b/c/src/lib/libbsp/powerpc/qemuppc/Makefile.am index 9a3099377a..b918506e3b 100644 --- a/c/src/lib/libbsp/powerpc/qemuppc/Makefile.am +++ b/c/src/lib/libbsp/powerpc/qemuppc/Makefile.am @@ -8,11 +8,11 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/qemuppc/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/qemuppc/start/start.S b/c/src/lib/libbsp/powerpc/qemuppc/start/start.S deleted file mode 100644 index 1ef7a3a02a..0000000000 --- a/c/src/lib/libbsp/powerpc/qemuppc/start/start.S +++ /dev/null @@ -1,52 +0,0 @@ -#include <rtems/score/cpu.h> -#include <rtems/powerpc/powerpc.h> - -#include <bspopts.h> - - .global bsp_interrupt_stack_start - .global bsp_interrupt_stack_end - .global _start - - .section .bsp_start_text,"awx",@progbits - -_start: - lis %r1,bsp_interrupt_stack_start@h - ori %r1,%r1,bsp_interrupt_stack_start@l - /* Make sure stack is properly aligned */ - li %r3, CPU_STACK_ALIGNMENT - 1 - andc %r1, %r1, %r3 - /* NULL ptr to back chain */ - li %r3, 0 - stw %r3, 0(%r1) - - li %r3,8192 - mtmsr %r3 - - /* Read-only small data */ - lis %r2, _SDA2_BASE_@h - ori %r2, %r2,_SDA2_BASE_@l - - /* Read-write small data */ - lis %r13, _SDA_BASE_@h - ori %r13, %r13,_SDA_BASE_@l - - bl cmain - .size _start, . - _start - - .global __eabi -__eabi: - blr - .size __eabi, . - __eabi - - .section ".reset","ax" -_reset: - b _start - .size _reset, . - _reset - - /* Start stack area */ - .section ".bsp_rwextra", "aw", @nobits - .align 4 - .space 4096 -bsp_interrupt_stack_start: - .space 32768 -bsp_interrupt_stack_end: diff --git a/c/src/lib/libbsp/powerpc/qoriq/Makefile.am b/c/src/lib/libbsp/powerpc/qoriq/Makefile.am index 770df931c6..a182369171 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/Makefile.am +++ b/c/src/lib/libbsp/powerpc/qoriq/Makefile.am @@ -10,15 +10,15 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/qoriq/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) -rtems_crtn.$(OBJEXT): ../shared/start/rtems_crtn.S +rtems_crtn.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crtn.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crtn.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S deleted file mode 100644 index 02505a6262..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S +++ /dev/null @@ -1,548 +0,0 @@ -/** - * @file - * - * @ingroup qoriq - * - * @brief BSP start. - */ - -/* - * Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/score/percpu.h> - -#include <bsp.h> - -#include <libcpu/powerpc-utility.h> - -#include <bsp/vectors.h> - -#if (QORIQ_INITIAL_MSR & MSR_FP) != 0 -#define INITIALIZE_FPU -#endif - -#define FIRST_TLB 0 -#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1 -#define INITIAL_MSR r14 -#define START_STACK r15 -#define SAVED_LINK_REGISTER r16 -#define FDT_REGISTER r17 - - .globl _start -#ifdef RTEMS_SMP -#if QORIQ_THREAD_COUNT > 1 - .globl _start_thread -#endif - .globl _start_secondary_processor -#endif - .globl bsp_exc_vector_base - - .section ".bsp_start_text", "ax" - -_start: - mr FDT_REGISTER, r3 - bl .Linitearly - - /* Get start stack */ - LA START_STACK, start_stack_end - - bl .Linitmore - - /* Copy fast text */ - LA r3, bsp_section_fast_text_begin - LA r4, bsp_section_fast_text_load_begin - LA r5, bsp_section_fast_text_size - bl .Lcopy - LA r3, bsp_section_fast_text_begin - LA r4, bsp_section_fast_text_size - bl rtems_cache_flush_multiple_data_lines - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - /* Copy read-only data */ - LA r3, bsp_section_rodata_begin - LA r4, bsp_section_rodata_load_begin - LA r5, bsp_section_rodata_size - bl .Lcopy - - /* Copy FDT into read-only data */ - mr r3, FDT_REGISTER - bl bsp_fdt_copy - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - /* Flush read-only data */ - LA r3, bsp_section_rodata_begin - LA r4, bsp_section_rodata_size - bl rtems_cache_flush_multiple_data_lines - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - /* Copy fast data */ - LA r3, bsp_section_fast_data_begin - LA r4, bsp_section_fast_data_load_begin - LA r5, bsp_section_fast_data_size - bl .Lcopy - - /* Copy data */ - LA r3, bsp_section_data_begin - LA r4, bsp_section_data_load_begin - LA r5, bsp_section_data_size - bl .Lcopy - - /* NULL pointer access protection (only core 0 has to do this) */ - mfspr r3, BOOKE_PIR - cmpwi r3, 0 - bne .Lnull_area_setup_done - LA r3, bsp_section_start_begin - srawi r3, r3, 2 - mtctr r3 - li r3, -4 - LWI r4, 0x44000002 -.Lnull_area_setup_loop: - stwu r4, 4(r3) - bdnz .Lnull_area_setup_loop -.Lnull_area_setup_done: - - li r3, 1 - bl .Linitmmu - - /* Clear SBSS */ - LA r3, bsp_section_sbss_begin - LA r4, bsp_section_sbss_size - bl bsp_start_zero - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - /* Clear BSS */ - LA r3, bsp_section_bss_begin - LA r4, bsp_section_bss_size - bl bsp_start_zero - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - -#ifndef __powerpc64__ - /* Set up EABI and SYSV environment */ - bl __eabi -#endif - - /* Clear command line */ - li r3, 0 - - bl boot_card - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - -.Lcopy: - PPC_REG_CMP r3, r4 - beqlr - b memcpy - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - -.Linitearly: -#ifdef __powerpc64__ - /* Enable 64-bit computation mode for exceptions */ - mfspr r0, BOOKE_EPCR - oris r0, r0, BOOKE_EPCR_ICM >> 16 - mtspr BOOKE_EPCR, r0 - - /* Enable 64-bit computation mode */ - mfmsr r0 - oris r0, r0, MSR_CM >> 16 - mtmsr r0 - isync -#endif - - /* Disable decrementer */ - mfspr r0, BOOKE_TCR - LWI r4, BOOKE_TCR_DIE - andc r0, r0, r4 - mtspr BOOKE_TCR, r0 - -#ifdef QORIQ_INITIAL_SPEFSCR - /* SPEFSCR initialization */ - LWI r0, QORIQ_INITIAL_SPEFSCR - mtspr FSL_EIS_SPEFSCR, r0 -#endif - -#ifdef QORIQ_INITIAL_BUCSR - /* BUCSR initialization */ - LWI r0, QORIQ_INITIAL_BUCSR - mtspr FSL_EIS_BUCSR, r0 - isync -#endif - -#if defined(QORIQ_INITIAL_HID0) && !defined(QORIQ_IS_HYPERVISOR_GUEST) - /* HID0 initialization */ - LWI r0, QORIQ_INITIAL_HID0 - mtspr HID0, r0 -#endif - -#ifdef __powerpc64__ - LA32 r2, .TOC. -#else - /* Invalidate TLS anchor */ - li r2, 0 - - /* Set small-data anchor */ - LA r13, _SDA_BASE_ -#endif - - SET_SELF_CPU_CONTROL r4, r5 - - blr - -.Linitmore: - mflr SAVED_LINK_REGISTER - - /* Invalidate all TS1 MMU entries */ - li r3, 1 - bl qoriq_tlb1_invalidate_all_by_ts - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - /* Add TS1 entry for the first 4GiB of RAM */ - li r3, SCRATCH_TLB - li r4, FSL_EIS_MAS1_TS - li r5, FSL_EIS_MAS2_M - li r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX - li r7, 0 - li r8, 0 - li r9, 11 - bl qoriq_tlb1_write - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - /* MSR initialization and use TS1 for address translation */ - LWI INITIAL_MSR, QORIQ_INITIAL_MSR - ori r0, INITIAL_MSR, MSR_IS | MSR_DS -#ifdef QORIQ_IS_HYPERVISOR_GUEST - oris r0, r0, MSR_GS >> 16 -#endif - mtmsr r0 - isync - - /* - * Initialize start stack. Make sure that we do not share a cache line - * with the heap block management, since initial stacks for the - * secondary processors are allocated from the workspace. - */ - subi r1, START_STACK, 2 * PPC_DEFAULT_CACHE_LINE_SIZE - clrrwi r1, r1, PPC_DEFAULT_CACHE_LINE_POWER - li r0, 0 - PPC_REG_STORE r0, 0(r1) - -#ifdef INITIALIZE_FPU - bl .Linitfpu -#endif - - mtlr SAVED_LINK_REGISTER - blr - -.Linitmmu: - mflr SAVED_LINK_REGISTER - - /* Configure MMU */ - li r4, FIRST_TLB - li r5, SCRATCH_TLB - bl qoriq_mmu_config - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - mtmsr INITIAL_MSR - isync - li r3, SCRATCH_TLB - bl qoriq_tlb1_invalidate - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE - - mtlr SAVED_LINK_REGISTER - blr - -#ifdef INITIALIZE_FPU - /* - * Write a value to the FPRs to initialize the hidden tag bits. See - * also "Core Software Initialization Requirements" of the e500mc - * reference manual for example. - */ -.Linitfpu: - li r0, 0 - stw r0, 0(r1) - stw r0, 4(r1) - lfd f0, 0(r1) - fmr f1, f0 - fmr f2, f0 - fmr f3, f0 - fmr f4, f0 - fmr f5, f0 - fmr f6, f0 - fmr f7, f0 - fmr f8, f0 - fmr f9, f0 - fmr f10, f0 - fmr f11, f0 - fmr f12, f0 - fmr f13, f0 - fmr f14, f0 - fmr f15, f0 - fmr f16, f0 - fmr f17, f0 - fmr f18, f0 - fmr f19, f0 - fmr f20, f0 - fmr f21, f0 - fmr f22, f0 - fmr f23, f0 - fmr f24, f0 - fmr f25, f0 - fmr f26, f0 - fmr f27, f0 - fmr f28, f0 - fmr f29, f0 - fmr f30, f0 - fmr f31, f0 - blr -#endif - -#ifdef RTEMS_SMP -#if QORIQ_THREAD_COUNT > 1 -_start_thread: - /* Adjust PIR */ - mfspr r0, BOOKE_PIR - srawi r0, r0, 2 - ori r0, r0, 1 - mtspr BOOKE_PIR, r0 - - bl .Linitearly - - /* Initialize start stack */ - GET_SELF_CPU_CONTROL r3 - PPC_REG_LOAD r3, PER_CPU_INTERRUPT_STACK_HIGH(r3) - subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE - clrrwi r1, r1, PPC_STACK_ALIGN_POWER - li r0, 0 - PPC_REG_STORE r0, 0(r1) - -#ifdef INITIALIZE_FPU - bl .Linitfpu -#endif - - b qoriq_start_thread - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif -_start_secondary_processor: - bl .Linitearly - - /* Get start stack */ - mr START_STACK, r3 - - bl .Linitmore - li r3, 0 - bl .Linitmmu - b bsp_start_on_secondary_processor - PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif /* RTEMS_SMP */ - -#ifdef __powerpc64__ -#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop; nop; nop; nop -#else -#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - - /* Exception vector prologues area */ - .section ".bsp_start_text", "ax" - .align 4 -bsp_exc_vector_base: - /* Critical input */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 0 - b ppc_exc_fatal_critical - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Machine check */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 1 - b ppc_exc_fatal_machine_check - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Data storage */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 2 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Instruction storage */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 3 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* External input */ - PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) - li r3, 4 - b ppc_exc_interrupt - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Alignment */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 5 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Program */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 6 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#ifdef __PPC_CPU_E6500__ - /* Floating-point unavailable */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 7 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - /* System call */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 8 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#ifdef __PPC_CPU_E6500__ - /* APU unavailable */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 9 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - /* Decrementer */ -#ifdef QORIQ_IS_HYPERVISOR_GUEST - PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) - li r3, 10 - b ppc_exc_interrupt -#else - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 10 - b ppc_exc_fatal_normal -#endif - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Fixed-interval timer interrupt */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 11 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Watchdog timer interrupt */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 12 - b ppc_exc_fatal_critical - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Data TLB error */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 13 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Instruction TLB error */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 14 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Debug */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 15 - b ppc_exc_fatal_debug - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* SPE APU unavailable or AltiVec unavailable */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 32 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* SPE floating-point data exception or AltiVec assist */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 33 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#ifndef __PPC_CPU_E6500__ - /* SPE floating-point round exception */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 34 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - /* Performance monitor */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 35 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#ifdef __PPC_CPU_E6500__ - /* Processor doorbell interrupt */ -#if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP) - PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) - li r3, 36 - b ppc_exc_interrupt -#else - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 36 - b ppc_exc_fatal_normal -#endif - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Processor doorbell critical interrupt */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 37 - b ppc_exc_fatal_critical - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Guest processor doorbell */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 38 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Guest processor doorbell critical and machine check */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 39 - b ppc_exc_fatal_critical - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Hypervisor system call */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 40 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* Hypervisor privilege */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 41 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE - /* LRAT error */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 42 - b ppc_exc_fatal_normal - START_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - -/* Symbol provided for debugging and tracing */ -bsp_exc_vector_end: - - /* Start stack area */ - .section ".bsp_rwextra", "aw", @nobits - .align 4 - .space 4096 -start_stack_end: diff --git a/c/src/lib/libbsp/powerpc/shared/start/preload.S b/c/src/lib/libbsp/powerpc/shared/start/preload.S deleted file mode 100644 index d8b47dfd2d..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/start/preload.S +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Mini-loader for the SVGM BSP. - * - * Author: Till Straumann, 10/2001 <strauman@slac.stanford.edu> - * - * Some ideas are borrowed from the powerpc/shared/bootloader - * by - * Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The SMON firmware is unable to load the RTEMS image below - * 0x2000 (I believe their stack is growing below 0x1000). - * - * The code provided by this file is responsible for the performing - * the following steps: - * - * 1) Save commandline parameters to an area that is - * a) not covered by the downloaded image - * b) will not be overwritten by the moved image - * nor the final BSS segment (rtems clears BSS - * before saving the command line). - * 2) Move the entire image (including this very file) to - * its final location starting at 0x0000. - * It is important to note that _NO_STACK_ is available - * during this step. Also, there is probably no return to - * SMON because relocating RTEMS will destroy vital SMON - * data (such as its stack). - * 3) Flush the cache to make sure the relocated image is actually - * in memory. - * 4) setup RTEMS environment (initial register values), most - * notably an initial STACK. The initial stack may be small and - * is used by RTEMS only at a very early stage. - * A safe place for the stack seems to be the 00..0x7f area. - * NOTE: we should respect the MAILBOX area 0x80..0xff! - * 5) switch the MMU off (because that's what RTEMS is expecting - * it to be at startup). - * 6) fire up rtems... - * - * - * Calling convention: - * R1: SMON SP - * R3: command line string start - * R4: command line string end + 1 - * R5: where SMON put the image - * if R5 is 0, the preloader will use its entry point - * as the image starting address. - * See NOTE below. - * R6: end of the image (i.e. R6-R5 is the image length) - * if R6 is 0, _edata will be used as the image length - * See NOTE below. - * - * NOTE: if the symbol DONT_USE_R5_ENTRY is defined, - * R5/R6 are never used and the necessary parameters are - * determined at runtime (R5) / linkage (R6) [_edata] - * - * ASSUMPTIONS: - * The code RELIES on the assumption that the image will be - * moved DOWNWARDS in memory and that the this loader is - * prepended to the image, i.e. it is safe to do - * codemove(codemove,0,codemove_end - codemove); - * (*0)(codemove_end, codemove_end-codemove, __rtems_end-codemove_end); - * where codemove(from, to, nbytes) is defined as - * codemove(from, to, nbytes) { while (nbytes--) *(to++)=*(from++); } - * Implicit to these assumptions is the assumption that the destination - * address is cache block aligned. - * Furthermore, the byte count is assumed to be a multiple - * of four - * - */ -#if 0 -#include <rtems/score/powerpc.h> -#else -#ifndef PPC_CACHE_ALIGNMENT -#define PPC_CACHE_ALIGNMENT 32 -#endif -#endif - -#include <rtems/score/cpu.h> -#include <rtems/asm.h> - -/* Note that major modifications may be needed - * if DESTINATION_ADDR is not 0 - */ -#define KERNELBASE 0x0 -#define INITIAL_STACK 0x70 /* 16-byte aligned */ -#define CACHE_LINE_SIZE PPC_CACHE_ALIGNMENT /* autodetect doesn't work, see below */ -#define ASSUME_RTEMS_INSTALLS_VECTORS /* assume we need not load vectors */ -#define DONT_USE_R5_ENTRY /* always dynamically determine the address we're running from */ - - /* put this into its own section which we want to - * be loaded at the very beginning. We should probably - * not use more than 255 bytes. - */ - PUBLIC_VAR(__rtems_start) - PUBLIC_VAR(__rtems_entry_point) - PUBLIC_VAR(__rtems_end) - .section .entry_point_section,"awx",@progbits -preload: - /* find out where we are */ - bl here -here: - xor r0,r0,r0 - mtmsr r0 /* clear MSR to known state */ - mflr r5 - addi r5,r5,-(here-preload) - lis r27,_edata@h - ori r27,r27,_edata@l - - /* at this point the register contents are - * R3: command line start - * R4: R3 + command line length - * R5: address we are running from / loaded to - * R27: image end - */ - - /* save command line start */ - mr r6, r3 - /* save the command line parameters if they are to be overwritten */ - sub. r17, r4, r3 /* string length */ - ble leaveparms /* <=0 -> no parameters */ - /* copy has to be out of the way of the bss; therefore we must - * put the string out of the way of both, the current end of - * the image (without bss) AND the end of the loaded image - * (including bss): - * |......image.........| downloaded image - * |image_bss...........| loaded image with bss appended - * - * ^ safe place for string - * - * the alternative scenario looks like this: - * |..image.............| downloaded image - * |image_bss...........| loaded image with bss appended - * ^ safe place for string - */ - lis r18, __rtems_end+0x10000@h /* round up, save one instruction */ - add r16, r5, r27 /* image end + 1 */ - cmpw r16, r18 - bge ishighenough - mr r16,r18 /* __rtems_end is higher than the image end - * (without bss) - */ -ishighenough: - cmpw r16, r3 /* destination start > current string start ? */ - ble leaveparms /* string already after dst, leave it */ - /* copy string from the last byte downwards */ - add r6, r16, r17 /* last byte of destination + 1 */ - mtctr r17 -1: - lbzu r3, -1(r4) - stbu r3, -1(r6) - bdnz 1b -leaveparms: - add r7, r6, r17 /* destination + strlen */ - -#ifndef CACHE_LINE_SIZE - /* Oh well, SMON has inhibited the cache, so this - * nice routine doesn't work... - */ - /* figure out the cache line size */ - li r16, 0x80 - cmpw r5, r16 /* 'from' must be > 0x80 */ - blt panic - -1: /* store some arbitrary, nonzero stuff in 0..0x7c */ - stwu r16,-4(r16) - cmpwi r16,0 - bne 1b - dcbz 0,r16 /* zero out one cache line */ - subi r16,r16,4 -2: lwzu r0,4(r16) /* search for a non-zero word */ - cmpwi r0,0 - beq 2b - /* OK, r16 now hold the size of a cache line in bytes */ -#else - li r16,CACHE_LINE_SIZE -#endif - - lis r3,preload@h - ori r3,r3,preload@l - mr r4,r5 /* from-addr */ - li r5,_preload_size/* this is never > 16k */ - /* now move ourselves to the link address ('preload'). - * We set up the LR, so domove() 'returns' to the - * relocated copy - */ - lis r0,return_here@h - ori r0,r0,return_here@l - mtlr r0 - b domove /* move the preloader itself */ -return_here: - /* now we move the entire rest of the image */ -#ifdef ASSUME_RTEMS_INSTALLS_VECTORS - lis r3,__rtems_start@h - ori r3,r3,__rtems_start@l - lis r0,preload@h /* calculate/adjust from address */ - ori r0,r0,preload@l - sub r0,r3,r0 - add r4,r4,r0 - sub r5,r27,r3 -#else - add r3,r3,r5 /* add preloader size to destination */ - add r4,r4,r5 /* and source addresses */ - sub r5,r27,r5 /* length of the remaining rest */ -#endif - bl domove - /* OK, now everything should be in place. - * we are ready to start... - */ - - /* setup initial stack for rtems early boot */ - li r1,INITIAL_STACK - /* tag TOS with a NULL pointer (for stack trace) */ - li r0, 0 - stw r0, 0(r1) - /* disable the MMU and fire up rtems */ - mfmsr r0 - ori r0,r0,MSR_IR|MSR_DR|MSR_IP|MSR_ME - xori r0,r0,MSR_IR|MSR_DR - mtsrr1 r0 - lis r0,__rtems_entry_point@h - ori r0,r0,__rtems_entry_point@l - mtsrr0 r0 - /* R6: start of command line */ - /* R7: end of command line +1 */ - rfi - - /* domove(to, from, nbytes): - * - * move a R5 bytes from R4 to R3 and flush - * the caches for the destination memory - * region. R16 provides the cache line size. - * DESTROYS: R0, R17, R18, CTR, CR - */ -domove: - addi r0,r5,3 /* convert to word count */ - srwi. r0,r0,2 - beq 3f /* nothing to do */ - cmpw r3,r4 /* from == to ? */ - beq 3f - mtctr r0 - la r18,-4(r4) - la r17,-4(r3) -1: lwzu r0,4(r18) - stwu r0,4(r17) - bdnz 1b /* move data */ - /* now, we must flush the destination cache region */ -#ifndef CACHE_LINE_SIZE - cmpwi r16,0 - beq 3f /* nothing to do */ -#endif -#if defined(CACHE_LINE_SIZE) && CACHE_LINE_SIZE > 0 - add r17,r3,r5 /* target end pointer */ - subi r0,r16,1 - add r17,r17,r0 - andc r17,r17,r0 /* cache aligned target end pointer */ - mr r18,r3 -2: cmpw r18,r17 - dcbst 0,r18 /* write out data cache line */ - icbi 0,r18 /* invalidate corresponding i-cache line */ - add r18,r18,r16 - blt 2b - sync /* make sure data is written back */ - isync /* invalidate possibly preloaded instructions */ -#endif -3: - blr - -#if !defined(CACHE_LINE_SIZE) -panic: - li r10,0x63 - mfmsr r0 - ori r0,r0,MSR_IP - mtmsr r0 - sc -#endif - -/* DONT PUT ANY CODE BELOW HERE */ -_preload_size = . - preload diff --git a/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S b/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S deleted file mode 100644 index a664ae2522..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2017 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* rtems_crti.S */ -#include <rtems/asm.h> -#include <rtems/score/cpu.h> - -#if defined(__powerpc64__) - .section ".init","ax" - .align 2 - .globl _init - .type _init,@function -_init: - mflr r0 - std r0,16(1) - stdu r1,-96(1) - - .section ".fini","ax" - .align 2 - .globl _fini - .type _fini,@function -_fini: - mflr r0 - std r0,16(r1) - stdu r1,-96(r1) -#else - /* terminate the __init() function and create - * a new head '_init' for use by RTEMS to - * invoke C++ global constructors - * NOTE: it is essential that this snippet - * is hooked between ecrti and crtbegin - * - * ecrti has the following .init section: - * __init: - * stwu r1,-16(r1) - * mflr r0 - * stw r0,20(r1) - * - * The reason for this is that we want to call - * __eabi() at an early stage but prevent __eabi() - * from branching to __init (C++ exception init - * and global CTORs). Hence we make __init a no-op - * and create a new entry point: - */ - .section ".init","ax" - .align 2 - lwz r0,r20(r1) - mtlr r0 - addi r1,r1,16 - blr - .globl _init - .type _init,@function -_init: - stwu r1,-16(r1) - mflr r0 - stw r0,20(r1) -#endif diff --git a/c/src/lib/libbsp/powerpc/shared/start/rtems_crtn.S b/c/src/lib/libbsp/powerpc/shared/start/rtems_crtn.S deleted file mode 100644 index 747d83dbce..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/start/rtems_crtn.S +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#if defined(__powerpc64__) - .section ".init","ax" - addi 1,1,96 - ld 0,16(1) - mtlr 0 - blr - - .section ".fini","ax" - addi 1,1,96 - ld 0,16(1) - mtlr 0 - blr -#endif diff --git a/c/src/lib/libbsp/powerpc/shared/start/start.S b/c/src/lib/libbsp/powerpc/shared/start/start.S deleted file mode 100644 index 354b9a967e..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/start/start.S +++ /dev/null @@ -1,207 +0,0 @@ -/* - * start.S : RTEMS entry point - * - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> -#include <rtems/powerpc/powerpc.h> - -#include <libcpu/io.h> -#include <libcpu/bat.h> -#include <bspopts.h> - -#define SYNC \ - sync; \ - isync - -#define KERNELBASE 0x0 - -#define MONITOR_ENTER \ - mfmsr r10 ; \ - ori r10,r10,MSR_IP ; \ - mtmsr r10 ; \ - li r10,0x63 ; \ - sc - - .text - .globl __rtems_entry_point - .type __rtems_entry_point,@function -__rtems_entry_point: -#ifdef DEBUG_EARLY_START - MONITOR_ENTER -#endif - -/* - * PREP - * This is jumped to on prep systems right after the kernel is relocated - * to its proper place in memory by the boot loader. The expected layout - * of the regs is: - * r3: ptr to residual data - * r4: initrd_start or if no initrd then 0 - * r5: initrd_end - unused if r4 is 0 - * r6: Start of command line string - * r7: End of command line string - * - * The Prep boot loader insure that the MMU is currently off... - * - */ - - mr r31,r3 /* save parameters */ - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - -#ifdef __ALTIVEC__ - /* enable altivec; gcc may use it! */ - mfmsr r0 - oris r0, r0, (1<<(31-16-6)) - mtmsr r0 - isync - /* - * set vscr and vrsave to known values - */ - li r0, 0 - mtvrsave r0 - vxor 0,0,0 - mtvscr 0 -#endif - - /* - * Make sure we have nothing in BATS and TLB - */ - bl CPU_clear_bats_early - bl flush_tlbs -/* - * Use the first pair of BAT registers to map the 1st 256MB - * of RAM to KERNELBASE. - */ - lis r11,KERNELBASE@h -/* set up BAT registers for 604 */ - ori r11,r11,0x1ffe - li r8,2 /* R/W access */ - isync - mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ - mtspr DBAT0U,r11 /* bit in upper BAT register */ - mtspr IBAT0L,r8 - mtspr IBAT0U,r11 - isync -/* Map section where residual is located if outside - * the first 256Mb of RAM. This is to support cases - * where the available system memory is larger than - * 256Mb of RAM. - */ - mr r9, r1 /* Get where residual was mapped */ - lis r12,0xf0000000@h - and r9,r9,r12 - cmpi 0,1,r9, 0 - beq enter_C_code - isync - ori r11,r9,0x1ffe - mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */ - mtspr DBAT1U,r11 /* bit in upper BAT register */ - mtspr IBAT1L,r8 - mtspr IBAT1U,r11 - isync - -/* - * we now have the 1st 256M of ram mapped with the bats. We are still - * running on the bootloader stack and cannot switch to an RTEMS allocated - * init stack before copying the residual data that may have been set just after - * rtems_end address. This bug has been experienced on MVME2304. Thank to - * Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and suggesting - * the appropriate code. - */ - -enter_C_code: - bl MMUon - bl __eabi /* setup EABI and SYSV environment */ - bl zero_bss - /* - * restore prep boot params - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl save_boot_params - /* - * stack = &__rtems_end + 4096 - */ - addis r9,r0, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@ha - addi r9,r9, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@l - /* - * align initial stack - * (we hope that the bootloader stack was 16-byte aligned - * or we haven't used altivec yet...) - */ - li r0, (CPU_STACK_ALIGNMENT-1) - andc r1, r9, r0 - /* - * Tag TOS with a NULL (terminator for stack dump) - */ - li r0, 0 - stw r0, 0(r1) - - /* - * We are now in a environment that is totally independent from - * bootloader setup. - */ - /* pass result of 'save_boot_params' to 'boot_card' in R3 */ - bl boot_card - bl _return_to_ppcbug - - .globl MMUon - .type MMUon,@function -MMUon: - mfmsr r0 - ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP -#if (PPC_HAS_FPU == 0) - xori r0, r0, MSR_EE | MSR_IP | MSR_FP -#else - xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 -#endif - mflr r11 - mtsrr0 r11 - mtsrr1 r0 - SYNC - rfi - - .globl MMUoff - .type MMUoff,@function -MMUoff: - mfmsr r0 - ori r0,r0,MSR_IR| MSR_DR | MSR_IP - mflr r11 - xori r0,r0,MSR_IR|MSR_DR - mtsrr0 r11 - mtsrr1 r0 - SYNC - rfi - - .globl _return_to_ppcbug - .type _return_to_ppcbug,@function - -_return_to_ppcbug: - mflr r30 - bl MMUoff - MONITOR_ENTER - bl MMUon - mtctr r30 - bctr - -flush_tlbs: - lis r20, 0x1000 -1: addic. r20, r20, -0x1000 - tlbie r20 - bgt 1b - sync - blr diff --git a/c/src/lib/libbsp/powerpc/shared/start/vectors_entry.S b/c/src/lib/libbsp/powerpc/shared/start/vectors_entry.S deleted file mode 100644 index 07b17a48af..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/start/vectors_entry.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (c) 2007, Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> - * - * - * This file contains the entry point vector needed by some bootloaders - * derived from "vectors.S" - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> - - PUBLIC_VAR (__rtems_start) - .section .entry_point_section,"awx",@progbits -/* - * Entry point information used by bootloader code - */ -SYM (__rtems_start): - .long __rtems_entry_point - - /* - * end of special Entry point section - */ diff --git a/c/src/lib/libbsp/powerpc/ss555/Makefile.am b/c/src/lib/libbsp/powerpc/ss555/Makefile.am index a9b5397c9f..94d1e18bd8 100644 --- a/c/src/lib/libbsp/powerpc/ss555/Makefile.am +++ b/c/src/lib/libbsp/powerpc/ss555/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = rtems_crti.$(OBJEXT) @@ -26,7 +26,7 @@ librtemsbsp_a_SOURCES += startup/bspstart.c librtemsbsp_a_SOURCES += startup/iss555.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/getentropy/getentropy-cpucounter.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/sbrk.c -librtemsbsp_a_SOURCES += start/start.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/ss555/start/start.S librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-default.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspreset-empty.c # tm27supp diff --git a/c/src/lib/libbsp/powerpc/ss555/start/start.S b/c/src/lib/libbsp/powerpc/ss555/start/start.S deleted file mode 100644 index 6a8ef85afc..0000000000 --- a/c/src/lib/libbsp/powerpc/ss555/start/start.S +++ /dev/null @@ -1,411 +0,0 @@ -/* - * This file contains the entry veneer for RTEMS programs on the Intec - * SS555 board. It jumps to the BSP which is responsible for performing - * all remaining initialization. - */ - -/* - * This file is based on several others: - * - * (1) start360.s from the gen68360 BSP by - * W. Eric Norum (eric@skatter.usask.ca) - * with the following copyright and license: - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * (2) start.s for the eth_comm port by - * Jay Monkman (jmonkman@fracsa.com), - * which itself is based on the - * - * (3) dlentry.s for the Papyrus BSP, written by: - * Andrew Bray <andy@i-cubed.co.uk> - * with the following copyright and license: - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * (4) start860.S for the MBX821/MBX860, written by: - * Darlene A. Stewart <darlene.stewart@iit.nrc.ca> - * Copyright (c) 1999, National Research Council of Canada - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * (5) Modifications (for MBX8xx) of respective RTEMS files: - * Copyright (c) 1999, National Research Council of Canada - * - * SS555 port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - */ - -#include <rtems/asm.h> -#include <rtems/powerpc/registers.h> - -#include <bsp.h> - -/* - * The initial stack is set to the top of the internal RAM. - * - * All the entry veneer has to do is to clear the .bss section and copy the - * initializers into the .data section. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Play compiler and provide some DWARF information. - * - * CHANGE TO SUIT YOUR SETUP! - */ - - .section .entry,"ax",@progbits -.L_text_b: -.L_LC1: - .previous - -.section .debug_sfnames -.L_sfnames_b: - .byte "rtems/c/src/lib/libbsp/powerpc/ss555/startup/" - .byte 0 -.L_F0: - .byte "start.S" - .byte 0 - .previous - -.section .line -.L_line_b: - .4byte .L_line_e-.L_line_b - .4byte .L_text_b -.L_LE1: -.L_line_last: - .4byte 0x0 - .2byte 0xffff - .4byte .L_text_e-.L_text_b -.L_line_e: - .previous - -.section .debug_srcinfo -.L_srcinfo_b: - .4byte .L_line_b - .4byte .L_sfnames_b - .4byte .L_text_b - .4byte .L_text_e - .4byte 0xffffffff - .4byte .L_LE1-.L_line_b - .4byte .L_F0-.L_sfnames_b - .4byte .L_line_last-.L_line_b - .4byte 0xffffffff - .previous - -.section .debug_pubnames - .4byte .L_debug_b - .4byte .L_P0 - .byte "start" - .byte 0 - .4byte 0x0 - .byte 0 - .previous - -.section .debug_aranges - .4byte .L_debug_b - .4byte .L_text_b - .4byte .L_text_e-.L_text_b - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0x0 - .4byte 0x0 - .previous - -.section .debug -.L_debug_b: -.L_D1: - .4byte .L_D1_e-.L_D1 - .2byte 0x11 /* TAG_compile_unit */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D2 - .2byte 0x38 /* AT_name */ - .byte "start.S" - .byte 0 - .2byte 0x258 /* AT_producer */ - .byte "GAS 2.5.2" - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x106 /* AT_stmt_list */ - .4byte .L_line_b - .2byte 0x1b8 /* AT_comp_dir */ - .byte "rtems/c/src/lib/libbsp/powerpc/ss555/startup/" - .byte 0 - .2byte 0x8006 /* AT_sf_names */ - .4byte .L_sfnames_b - .2byte 0x8016 /* AT_src_info */ - .4byte .L_srcinfo_b -.L_D1_e: -.L_P0: -.L_D3: - .4byte .L_D3_e-.L_D3 - .2byte 0x6 /* TAG_global_subroutine */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D4 - .2byte 0x38 /* AT_name */ - .byte "start" - .byte 0 - .2byte 0x278 /* AT_prototyped */ - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x8041 /* AT_body_begin */ - .4byte .L_text_b - .2byte 0x8051 /* AT_body_end */ - .4byte .L_text_e -.L_D3_e: - -.L_D4: - .4byte .L_D4_e-.L_D4 - .align 2 -.L_D4_e: -.L_D2: - .previous - -/* - * Tell C's eabi-ctor's that we have an atexit function, - * and that it is to register __do_global_dtors. - */ - EXTERN_PROC(atexit) - PUBLIC_VAR(__atexit) - .section ".sdata","aw" - .align 2 -SYM(__atexit): - EXT_PROC_REF(atexit)@fixup - .previous - - .section ".fixup","aw" - .align 2 - EXT_SYM_REF(__atexit) - .previous - -/* That should do it */ - -/* - * Put the entry point in its own section. That way, we can guarantee - * to put it first in the .text section in the linker script. - */ - .section .entry - - PUBLIC_VAR (start) -SYM(start): - bl .startup /* or bl .spin */ -base_addr: - -/* - * Parameters from linker - */ -stack_top: - .long initStackPtr - -toc_pointer: - .long __GOT_START__ - -bss_length: - .long bss.size -bss_addr: - .long bss.start - -data_length: - .long data.size -data_addr: - .long data.start -contents_addr: - .long data.contents.start - -PUBLIC_VAR (text_addr) -text_addr: - .long text.start - -PUBLIC_VAR (text_length) -text_length: - .long text.size - -/* - * Spin, if necessary, to acquire control from debugger (CodeWarrior). - */ -spin: - .long 0x0001 -.spin: - lis r3, spin@ha - lwz r3, spin@l(r3) - cmpwi r3, 0x1 - beq .spin - -/* - * Initialization code - */ -.startup: - /* Capture address of linker parameters. */ - mflr r3 - - /* Set initial stack pointer to end of internal RAM - 56. */ - lwz r1, stack_top-base_addr(r3) - addi r1, r1, -56 - - /* Initialize essential registers. */ - bl initregs - - /* Set TOC pointer */ - lwz r2, toc_pointer-base_addr(r3) - - /* Initialize the memory mapped MPC555 registers (done in C). */ - EXTERN_PROC (_InitSS555) - bl PROC (_InitSS555) - - /* Clear the .bss section. */ - bl bssclr - - /* Copy initializers into the .data section */ - bl datacopy - - /* Enable floating point, since gcc sometimes uses the floating - * point registers for data moves, even if the C source code doesn't - * include floating point operations. - */ - mfmsr r0 - ori r0, r0, MSR_FP - mtmsr r0 - - /* Start system. */ - li r3, 0 /* command line */ - EXTERN_PROC (boot_card) - bl PROC (boot_card) /* call the first C routine */ - - /* We should never return from boot_card, but in case we do ... */ - /* The next instructions are dependent on your runtime environment. */ - -stop_here: - b stop_here - -/* - * datacopy - copy initializers into .data section - */ -datacopy: - lis r3, base_addr@ha /* point to linker data */ - addi r3, r3, base_addr@l - - lwz r4, contents_addr-base_addr(r3) /* .data contents in ROM */ - lwz r5, data_addr-base_addr(r3) /* .data section in RAM */ - lwz r6, data_length-base_addr(r3) /* length of .data */ - - rlwinm. r6, r6, 30, 0x3FFFFFFF /* form length / 4 */ - beqlr /* no .data - return */ - - mtctr r6 /* set ctr reg */ -dc1: - lwz r6, 0(r4) /* get word */ - stw r6, 0(r5) /* store word */ - addi r4, r4, 0x4 /* next source */ - addi r5, r5, 0x4 /* next target */ - bdnz dc1 /* dec counter and loop */ - - blr /* return */ - -/* - * bssclr - zero out bss - */ -bssclr: - lis r3, base_addr@ha /* point to linker data */ - addi r3, r3, base_addr@l - - lwz r4, bss_addr-base_addr(r3) /* Start of bss */ - lwz r5, bss_length-base_addr(r3) /* Length of bss */ - - rlwinm. r5, r5, 30, 0x3FFFFFFF /* form length/4 */ - beqlr /* no bss - return */ - - mtctr r5 /* set ctr reg */ - li r5, 0x0000 /* r5 = 0 */ -clear_bss: - stw r5, 0(r4) /* store r6 */ - addi r4, r4, 0x4 /* update r4 */ - bdnz clear_bss /* dec counter and loop */ - - blr /* return */ - -/* - * initregs - * Initialize the MSR and basic core PowerPC registers - * - * Register usage: - * r0 - scratch - */ -initregs: - /* - * Set the processor for big-endian mode, exceptions vectored to - * 0x000n_nnnn, no execution tracing, machine check exceptions - * enabled, floating-point not available, supervisor priviledge - * level, external interrupts disabled, power management disabled - * (normal operation mode). - */ - li r0, 0x1000 /* MSR_ME */ - mtmsr r0 /* Context-synchronizing */ - isync - - /* - * Clear the exception handling registers. - */ - li r0, 0x0000 - mtdar r0 - mtspr sprg0, r0 - mtspr sprg1, r0 - mtspr sprg2, r0 - mtspr sprg3, r0 - mtspr srr0, r0 - mtspr srr1, r0 - - mr r6, r0 - mr r7, r0 - mr r8, r0 - mr r9, r0 - mr r10, r0 - mr r11, r0 - mr r12, r0 - mr r13, r0 - mr r14, r0 - mr r15, r0 - mr r16, r0 - mr r17, r0 - mr r18, r0 - mr r19, r0 - mr r20, r0 - mr r21, r0 - mr r22, r0 - mr r23, r0 - mr r24, r0 - mr r25, r0 - mr r26, r0 - mr r27, r0 - mr r28, r0 - mr r29, r0 - mr r30, r0 - mr r31, r0 - - blr /* return */ - -.L_text_e: diff --git a/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am b/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am index 5590cf9fcf..97917a78da 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am +++ b/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am @@ -10,11 +10,11 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/t32mppc/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S deleted file mode 100644 index 7c32343f3d..0000000000 --- a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bspopts.h> - -#include <rtems/score/percpu.h> -#include <libcpu/powerpc-utility.h> -#include <bsp/vectors.h> - - .globl _start - .globl bsp_exc_vector_base - - .section ".bsp_start_text", "ax" - - /* Primitive NULL pointer protection */ -.rept 1024 - sc -.endr - -_start: - /* Enable time base */ - li r0, 0x4000 - mtspr HID0, r0 - - /* Initialize start stack */ - LWI r1, start_stack_end - subi r1, r1, 16 - li r0, 0 - stw r0, 0(r1) - - SET_SELF_CPU_CONTROL r3, r4 - - /* Copy fast text */ - LWI r3, bsp_section_fast_text_begin - LWI r4, bsp_section_fast_text_load_begin - LWI r5, bsp_section_fast_text_size - bl copy - - /* Copy read-only data */ - LWI r3, bsp_section_rodata_begin - LWI r4, bsp_section_rodata_load_begin - LWI r5, bsp_section_rodata_size - bl copy - - /* Copy fast data */ - LWI r3, bsp_section_fast_data_begin - LWI r4, bsp_section_fast_data_load_begin - LWI r5, bsp_section_fast_data_size - bl copy - - /* Copy data */ - LWI r3, bsp_section_data_begin - LWI r4, bsp_section_data_load_begin - LWI r5, bsp_section_data_size - bl copy - - /* Clear SBSS */ - LWI r3, bsp_section_sbss_begin - LWI r4, bsp_section_sbss_size - bl bsp_start_zero - - /* Clear BSS */ - LWI r3, bsp_section_bss_begin - LWI r4, bsp_section_bss_size - bl bsp_start_zero - - /* Set up EABI and SYSV environment */ - bl __eabi - - /* Clear command line */ - li r3, 0 - - bl boot_card - -twiddle: - b twiddle - -copy: - cmpw r3, r4 - beqlr - b memcpy - - /* Exception vector prologues area */ - .section ".bsp_start_text", "ax" - .align 4 -bsp_exc_vector_base: - /* Critical input */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 0 - b ppc_exc_fatal_critical - /* Machine check */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 1 - b ppc_exc_fatal_machine_check - /* Data storage */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 2 - b ppc_exc_fatal_normal - /* Instruction storage */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 3 - b ppc_exc_fatal_normal - /* External input */ - PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 4 - b ppc_exc_interrupt - /* Alignment */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 5 - b ppc_exc_fatal_normal - /* Program */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 6 - b ppc_exc_fatal_normal - /* Floating-point unavailable */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 7 - b ppc_exc_fatal_normal - /* System call */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 8 - b ppc_exc_fatal_normal - /* APU unavailable */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 9 - b ppc_exc_fatal_normal - /* Decrementer */ - PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) - li r3, 10 - b ppc_exc_interrupt - /* Fixed-interval timer interrupt */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 11 - b ppc_exc_fatal_normal - /* Watchdog timer interrupt */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 12 - b ppc_exc_fatal_critical - /* Data TLB error */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 13 - b ppc_exc_fatal_normal - /* Instruction TLB error */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 14 - b ppc_exc_fatal_normal - /* Debug */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 15 - b ppc_exc_fatal_debug - /* SPE APU unavailable or AltiVec unavailable */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 32 - b ppc_exc_fatal_normal - /* SPE floating-point data exception or AltiVec assist */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 33 - b ppc_exc_fatal_normal - /* SPE floating-point round exception */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 34 - b ppc_exc_fatal_normal - /* Performance monitor */ - PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) - li r3, 35 - b ppc_exc_fatal_normal - - /* Start stack area */ - .section ".bsp_rwextra", "aw", @nobits - .align 4 - .space 4096 -start_stack_end: diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am b/c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am index 1c0dfe5da3..e447672b8e 100644 --- a/c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am +++ b/c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am @@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/tqm8xx/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/start/start.S b/c/src/lib/libbsp/powerpc/tqm8xx/start/start.S deleted file mode 100644 index 92bda3fd6d..0000000000 --- a/c/src/lib/libbsp/powerpc/tqm8xx/start/start.S +++ /dev/null @@ -1,294 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic TQM8xx BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2008 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the startup assembly code | -| it is based on the gen83xx BSP | -\*===============================================================*/ - -#include <libcpu/powerpc-utility.h> -#include <rtems/powerpc/cache.h> -#include <bsp.h> -#include <mpc8xx.h> - -.extern boot_card - -PUBLIC_VAR (_start) -PUBLIC_VAR (bsp_interrupt_stack_start) -PUBLIC_VAR (bsp_interrupt_stack_end) - -.section ".bsp_start_text", "ax" -_start: - - /* - * basic CPU setup: - * init MSR - */ - mfmsr r30 - SETBITS r30, r29, MSR_ME|MSR_RI - CLRBITS r30, r29, MSR_IP|MSR_EE - mtmsr r30 /* Set RI/ME, Clr EE in MSR */ - /* - * init IMMR - */ - LA r30,m8xx - mtspr immr,r30 - /* - * determine current execution address offset - */ - bl start_1 -start_1: - mflr r20 - LA r30,start_1 - sub. r20,r20,r30 - /* - * execution address offset == 0? - * then do not relocate code and data - */ - beq start_code_in_ram - /* - * ROM or relocatable startup: copy startup code to SDRAM - */ - /* get start address of text section in RAM */ - LA r29, bsp_section_text_begin - /* get start address of text section in ROM (add reloc offset) */ - add r30, r20, r29 - /* get size of startup code */ - LA r28, end_reloc_startup - LA r31, bsp_section_text_begin - sub 28,r28,r31 - /* copy startup code from ROM to RAM location */ - bl copy_image - - /* - * jump to code copy in SDRAM - */ - /* get compile time address of label */ - LA r29, copy_rest_of_text - mtlr r29 - blr /* now further execution RAM */ -copy_rest_of_text: - /* - * ROM or relocatable startup: copy rest of code to SDRAM - */ - /* get start address of rest of code in RAM */ - LA r29, end_reloc_startup - /* get start address of text section in ROM (add reloc offset) */ - add r30, r20, r29 - /* get size of rest of code */ - LA r28, bsp_section_text_begin - LA r31, bsp_section_text_size - add r28,r28,r31 - sub r28,r28,r29 - bl copy_image /* copy text section from ROM to RAM location */ - - /* - * ROM or relocatable startup: copy data to SDRAM - */ - /* get start address of data section in RAM */ - LA r29, bsp_section_data_begin - /* get start address of data section in ROM (add reloc offset) */ - add r30, r20, r29 - /* get size of RAM image */ - LA r28, bsp_section_data_size - /* copy initialized data section from ROM to RAM location */ - bl copy_image - -start_code_in_ram: - - /* - * ROM/RAM startup: clear bss in SDRAM - */ - LA r3, bsp_section_bss_begin /* get start address of bss section */ - LWI r4, bsp_section_bss_size /* get size of bss section */ - bl mpc8xx_zero_4 /* Clear the bss section */ - /* - * call boot_card - */ - - /* Set stack pointer (common for RAM/ROM startup) */ - LA r1, bsp_section_text_begin - addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ - - /* Create NULL */ - li r0, 0 - - /* Return address */ - stw r0, 4(r1) - - /* Back chain */ - stw r0, 0(r1) - - /* Read-only small data */ - LA r2, _SDA2_BASE_ - - /* Read-write small data */ - LA r13, _SDA_BASE_ - - /* - * init some CPU stuff - */ - bl SYM (_InitTQM8xx) - -/* clear arguments and do further init. in C (common for RAM/ROM startup) */ - - /* Clear cmdline */ - xor r3, r3, r3 - - bl SYM (boot_card) /* Call the first C routine */ - -twiddle: - /* We don't expect to return from boot_card but if we do */ - /* wait here for watchdog to kick us into hard reset */ - b twiddle - -copy_with_watchdog: - addi r5,r5,16 - rlwinm. r5,r5,28,4,31 - mtctr r5 - -copy_loop: - lwz r6,0(r3) - lwz r7,4(r3) - lwz r8,8(r3) - lwz r9,12(r3) - stw r6,0(r4) - stw r7,4(r4) - stw r8,8(r4) - stw r9,12(r4) - addi r3,r3,16 - addi r4,r4,16 - sth r28,14(r30) - sth r29,14(r30) - bdnz+ copy_loop - blr - -copy_image: - /* - * watchdog: - * r26 = immr - * r25 = watchdog magic 1 - * r24 = watchdog magic 2 - */ - mfimmr r26 - rlwinm. r26,r26,0,0,15 - li r25,0x556c - li r24,0xffffaa39 - - mr r27, r28 /* determine number of 4word chunks */ - srwi r28, r28, 4 - mtctr r28 - - slwi r28, r28, 4 - sub r27, r27, r28 /* determine residual bytes */ -copy_image_4word: - lwz r20, 0(r30) /* fetch data */ - lwz r21, 4(r30) - lwz r22, 8(r30) - lwz r23,12(r30) - stw r20, 0(r29) /* store data */ - stw r21, 4(r29) - stw r22, 8(r29) - stw r23,12(r29) - - addi r30, r30, 0x10 /* increment source pointer */ - addi r29, r29, 0x10 /* increment destination pointer */ - /* - * trigger watchdog - */ - sth r25,14(r26) - sth r24,14(r26) - - bdnz copy_image_4word /* decrement ctr and branch if not 0 */ - - cmpwi r27, 0x00 /* copy image finished ? */ - beq copy_image_end; - mtctr r27 /* reload counter for residual bytes */ -copy_image_byte: - lswi r28, r30, 0x01 - - stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ - - - addi r30, r30, 0x01 /* increment source pointer */ - addi r29, r29, 0x01 /* increment destination pointer */ - - bdnz copy_image_byte /* decrement ctr and branch if not 0 */ - -copy_image_end: - blr - - -/** - * @fn int mpc8xx_zero_4( void *dest, size_t n) - * - * @brief Zero all @a n bytes starting at @a dest with 4 byte writes. - * - * The address @a dest has to be aligned on 4 byte boundaries. The size @a n - * must be evenly divisible by 4. - */ -GLOBAL_FUNCTION mpc8xx_zero_4 - /* Create zero */ - xor r0, r0, r0 - - /* Set offset */ - xor r5, r5, r5 - - /* Loop counter for the first bytes up to 16 bytes */ - rlwinm. r9, r4, 30, 30, 31 - beq mpc8xx_zero_4_more - mtctr r9 - -mpc8xx_zero_4_head: - - stwx r0, r3, r5 - addi r5, r5, 4 - bdnz mpc8xx_zero_4_head - -mpc8xx_zero_4_more: - - /* More than 16 bytes? */ - srwi. r9, r4, 4 - beqlr - mtctr r9 - - /* Set offsets */ - addi r6, r5, 4 - addi r7, r5, 8 - addi r8, r5, 12 - -mpc8xx_zero_4_tail: - - stwx r0, r3, r5 - addi r5, r5, 16 - stwx r0, r3, r6 - addi r6, r6, 16 - stwx r0, r3, r7 - addi r7, r7, 16 - stwx r0, r3, r8 - addi r8, r8, 16 - bdnz mpc8xx_zero_4_tail - - /* Return */ - blr - -end_reloc_startup: - - /* Interrupt stack */ - .section ".bsp_rwextra", "aw", @nobits - .align 4 -bsp_interrupt_stack_start: - .space 32768 -bsp_interrupt_stack_end: diff --git a/c/src/lib/libbsp/powerpc/virtex/Makefile.am b/c/src/lib/libbsp/powerpc/virtex/Makefile.am index f9c98b5ec4..fe4c8d4ac4 100644 --- a/c/src/lib/libbsp/powerpc/virtex/Makefile.am +++ b/c/src/lib/libbsp/powerpc/virtex/Makefile.am @@ -12,11 +12,11 @@ endif noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/powerpc/virtex/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libbsp/powerpc/virtex/start/start.S b/c/src/lib/libbsp/powerpc/virtex/start/start.S deleted file mode 100644 index 725b09954f..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex/start/start.S +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - -#include <bspopts.h> - -#include <libcpu/powerpc-utility.h> - - .globl _start - .globl virtex_exc_vector_base - - .section ".bsp_start_text", "ax" - -virtex_exc_vector_base: - - b _start - - /* Critical Input 0x0100 */ - /* Machine Check 0x0200 */ - /* Data Storage 0x0300 */ - /* Instruction Storage 0x0400 */ - /* External 0x0500 */ - /* Alignment 0x0600 */ - /* Program 0x0700 */ - /* FPU Unavailable 0x0800 */ - /* System Call 0x0C00 */ - /* APU Unavailable 0x0F20 */ - /* Programmable-Interval Timer 0x1000 */ - /* Fixed-Interval Timer 0x1010 */ - /* Watchdog Timer 0x1020 */ - /* Data TLB Miss 0x1100 */ - /* Instruction TLB Miss 0x1200 */ - /* Debug 0x2000 */ -.rept 0x2000 / 4 - 1 - b twiddle -.endr - - /* Start stack area */ -.rept BSP_START_STACK_SIZE / 4 - b twiddle -.endr - -_start: - - /* Reset time base */ - li r0, 0 - mtspr TBWU, r0 - mtspr TBWL, r0 - - /* Initialize start stack */ - LWI r1, _start - stwu r0, -4(r1) - stwu r0, -4(r1) - - /* Copy fast text */ - LWI r3, bsp_section_fast_text_begin - LWI r4, bsp_section_fast_text_load_begin - LWI r5, bsp_section_fast_text_size - bl copy - - /* Copy fast data */ - LWI r3, bsp_section_fast_data_begin - LWI r4, bsp_section_fast_data_load_begin - LWI r5, bsp_section_fast_data_size - bl copy - - /* Clear SBSS */ - LWI r3, bsp_section_sbss_begin - LWI r4, bsp_section_sbss_size - bl bsp_start_zero - - /* Clear BSS */ - LWI r3, bsp_section_bss_begin - LWI r4, bsp_section_bss_size - bl bsp_start_zero - - /* Set up EABI and SYSV environment */ - bl __eabi - - /* Clear command line */ - li r3, 0 - - bl boot_card - -twiddle: - - bl bsp_reset - b twiddle - -copy: - - cmpw r3, r4 - beqlr - b memcpy - - /* Reset entry */ - .section ".virtex_reset", "ax" - -jump_to_start: - - LWI r3, _start - mtctr r3 - bctr - b jump_to_start diff --git a/c/src/lib/libbsp/powerpc/virtex4/Makefile.am b/c/src/lib/libbsp/powerpc/virtex4/Makefile.am index e8584ac178..60a179740c 100644 --- a/c/src/lib/libbsp/powerpc/virtex4/Makefile.am +++ b/c/src/lib/libbsp/powerpc/virtex4/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs # include # start -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = rtems_crti.$(OBJEXT) @@ -28,7 +28,7 @@ librtemsbsp_a_SOURCES += ../shared/src/memcpy.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspreset-empty.c # start -librtemsbsp_a_SOURCES += start/start.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/virtex4/start/start.S # console librtemsbsp_a_SOURCES += startup/dummy_console.c diff --git a/c/src/lib/libbsp/powerpc/virtex4/start/start.S b/c/src/lib/libbsp/powerpc/virtex4/start/start.S deleted file mode 100644 index 21948409bf..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex4/start/start.S +++ /dev/null @@ -1,330 +0,0 @@ -/*!@file start.S -* -* @brief Initialization code to set up the CPU and call boot_card() -* -* This "BSP" targets the Xilinx Virtex XC4VFX60 and related parts. This -* BSP makes no assumptions on what firmware is loaded into the FPGA. -* -* Provides the .entry section code. This is the first code to run in -* the PPC after download to RAM. Excecution in this case starts at -* 'download_entry'. -* -* The entrypoint 'start' is provided for the case where a bootloader has -* initialized the CPU, and all that remains to do is to set up a C -* environment and call boot_card. -* -* Derived from virtex dlentry and others. -* -* IBM refers to the version of the processor as PPC405F5. -* The processor version register returns 0x20011470. -* References: -* PowerPC Processor Reference Guide UG011 (v1.3) -* http://www.xilinx.com/support/documentation/user_guides/ug011.pdf -* -* PowerPC Block Reference Guide -* http://www.xilinx.com/support/documentation/user_guides/ug018.pdf -* -* PowerPC errata -* ftp://ftp.xilinx.com/pub/documentation/misc/ppc405f6v5_2_0.pdf -* -* PowerPC 405-S Embedded Processor Core User's Manual (Version 1.2) -* https://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_405_Embedded_Cores -* -* @author Richard Claus <claus@SLAC.Stanford.edu> -* -* @date March 4, 2011 -- Created -* -* $Revision: 674 $ -* -* @verbatim Copyright 2011 -* by -* The Board of Trustees of the -* Leland Stanford Junior University. -* All rights reserved. -* -* Work supported by the U.S. Department of Energy under contract -* DE-AC03-76SF00515. -* -* Disclaimer Notice -* -* The items furnished herewith were developed under the sponsorship -* of the U.S. Government. Neither the U.S., nor the U.S. D.O.E., nor the -* Leland Stanford Junior University, nor their employees, makes any war- -* ranty, express or implied, or assumes any liability or responsibility -* for accuracy, completeness or usefulness of any information, apparatus, -* product or process disclosed, or represents that its use will not in- -* fringe privately-owned rights. Mention of any product, its manufactur- -* er, or suppliers shall not, nor is it intended to, imply approval, dis- -* approval, or fitness for any particular use. The U.S. and the Univer- -* sity at all times retain the right to use and disseminate the furnished -* items for any purpose whatsoever. Notice 91 02 01 -* -* @endverbatim -*/ - -#include <rtems/asm.h> -#include <rtems/powerpc/powerpc.h> - -/* - * The virtex ELF link scripts support some special sections: - * .entry The actual entry point - * .vectors The section containing the interrupt entry veneers. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .text - * .data - * .bss - * see linker command file for section placement - * - * The initial stack is set to __stack_base. - * - */ - - .section .entry - - PUBLIC_VAR (download_entry) - PUBLIC_VAR (__rtems_entry_point) -SYM(download_entry): -SYM(__rtems_entry_point): - b startupDow /* Entry point used by xmd dow command */ - - PUBLIC_VAR (start) -SYM(start): - b startupBL /* Entry point used by bootLoader */ - -base_addr: - /*------------------------------------------------------------------- - * Parameters from linker - *-----------------------------------------------------------------*/ -toc_pointer: - .long __got_start -bss_length: - .long __bss_size -bss_addr: - .long __bss_start -stack_top: - .long __stack_base -dccr_contents: - .long __dccr -iccr_contents: - .long __iccr -sgr_contents: - .long __sgr - - /*------------------------------------------------------------------- - * Setup iccr, sgr, msr, cccr0, dcwr, dccr and clear bss - *-----------------------------------------------------------------*/ - -startupDow: - /*------------------------------------------------------------------- - * Load the parameter table base address - *------------------------------------------------------------------*/ - lis r1, base_addr@h - ori r1,r1,base_addr@l - - /* ------------------------------------------------------------------- - * Clear the Machine State Register's Critical and External - * interrupt enables. - *------------------------------------------------------------------*/ - mfmsr r3 - lis r0, 0x00028000@h - ori r0,r0,0x00028000@l - andc r3,r3,r0 - mtmsr r3 - sync - - /* ------------------------------------------------------------------- - * Initialize the memory system. - *------------------------------------------------------------------*/ - li r0,0 - - /* Set the Storage Guarded Register. */ - lwz r2,sgr_contents-base_addr(r1) - mtsgr r2 - - /* Configure endianness, compression */ - lis r0,0x00000000@h // Endianess value - mtsler r0 - lis r0,0x00000000@h // Compression value - mtsu0r r0 - - /* Invalidate the entire instruction cache. */ - iccci r0,r0 - - /* Set the Instruction Cache Cacheability Register. */ - lwz r2,iccr_contents-base_addr(r1) - mticcr r2 - isync - - /*------------------------------------------------------------------- - * Tell the processor where the exception vector table will be. - *------------------------------------------------------------------*/ - .extern SYM(__vectors) - lis r2, __vectors@h /* set EVPR exc. vector prefix */ - mtevpr r2 - - /*------------------------------------------------------------------- - * Set up the debug register to freeze timers on debug events. - *------------------------------------------------------------------*/ - mfdbcr0 r2 - ori r2,r2,0x0001 - mtdbcr0 r2 - isync - - /* Select whether APU, Wait Enable, interrupts/exceptions and address - translation should be enabled when application starts */ - lis r0,0x00000000@h /* SRR1 value */ - mtsrr1 r0 /* Potentially: 0x80000000 >> 6 is APU */ - - /* Configure timer facilities */ - mttbl r0 /* Clear Timebase to prevent Fixed Interval.. */ - mttbu r0 /* ..timer and Watchdog Timer exceptions */ - mtpit r0 /* Programmable interval timer */ - li r2,-1 /* -1 to clear TSR */ - mttsr r2 /* Timer status register */ - - /* Clear out stale values in certain registers to avoid confusion */ - mtcrf 0xff,r0 /* Need for simulation */ - mtctr r0 /* Counter register */ - mtxer r0 /* Fixed-point exception register */ - mtesr r0 /* Exception syndrome register */ - mtdear r0 /* Data exception address register */ - mtmcsr r0 /* Machine check syndrome register */ - - /* Invalidate the data cache */ - li r2,0 /* Start address */ - li r3,0x100 /* Number of cache lines */ - mtctr r3 /* Transfer data cache congruence class count to CTR */ -1: dccci 0,r2 /* Invalidate this congruence class */ - addi r2,r2,0x20 /* Point to next congruence class */ - bdnz 1b /* Decrement counter and loop whilst not zero */ - - /* ------------------------------------------------------------------- - * Set Core Configuration Register 0 as follows: - * sum: 0x02700E00 - * bit 1 off: as told by ppc405 errata to avoid CPU_213 ppc bug - * bit 3 off: as told by ppc405 errata to avoid CPU_213 ppc bug - (Note added later: PPC405F6 is not subject to CPU_213.) - * bit 1 on: Xilinx: CR 203746 Patch for PPC405 errata (RiC 12/8/11) - * bit 2 on: Xilinx: CR 203746 Patch for PPC405 errata (RiC 12/8/11) - * bit 6 on: load word as line - * bit 7 off: load misses allocate cache line - * bit 8 off: store misses allocate cache line - * bit 9-11 on: default settings to do with plb priority - * bit 20 on: prefetching for cacheable regions - * bit 21 on: prefetching for non-cacheable regions - * bit 22 on: request size of non-cacheable inst fetches is 8 words - * bit 23 off: fetch misses allocate cache line - *------------------------------------------------------------------*/ - lis r5, 0x52700E00@h - ori r5,r5,0x52700E00@l - - /* ------------------------------------------------------------------- - * To change CCR0 we make sure the code writing to it is - * running from the I-cache. This is needed because changing some - * CCR0 fields will cause a hang if the processor is trying to - * access memory at the same time. - *------------------------------------------------------------------*/ - lis r4, 2f@h - ori r4,r4,2f@l - icbt r0,r4 - b 2f - - .align 5 /* New cache line (32 bytes each) */ -2: - icbt r0,r4 /* Put this line into the I-cache. */ - isync - mtccr0 r5 - isync - b 3f - - .align 5 -3: - /* Set the Data Cache Write-Through Register for no write-through, i.e., for write-back. */ - li r0,0 - mtdcwr r0 - - /* Set the Data Cache Cacheablility Register. */ - lwz r0,dccr_contents-base_addr(r1) - mtdccr r0 - isync - - /* Fall through */ - - - /* ------------------------------------------------------------------- - * If a bootloader has run that has already performed some - * initialization, which among other things has loaded - * this code into memory and jumped to start above, the initialization - * above does not need to be done. Execution thus resumes here. - *------------------------------------------------------------------*/ - -startupBL: - /* ------------------------------------------------------------------- - * Note that some initialization has already been performed by the - * bootloader code in Block RAM, which among other things has loaded - * this code into memory and jumped to start above. - *------------------------------------------------------------------*/ - - /*------------------------------------------------------------------- - * Load the parameter table base address - *------------------------------------------------------------------*/ - lis r1, base_addr@h - ori r1,r1,base_addr@l - - /*------------------------------------------------------------------- - * Setup stack for RTEMS and call boot_card(). From this - * point forward registers will be used in accordance with the - * PowerPC EABI. - * - * boot_card() supervises the initialization of RTEMS and the C - * library. It calls bsp_start(), etc. - *------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - - /* Align as required by ABI */ - li r3,PPC_STACK_ALIGNMENT-1 - andc r1,r1,r3 - - /*------------------------------------------------------------------- - * Set up r2 and r13. Upon entry r1 must have a nonzero value - * as it will be stored in an "init done" flag. Stupid but true. - * r1 must also be set up as a stack pointer as __eabi() jumps - * to __init() which has a standard function prolog. - *------------------------------------------------------------------*/ - bl __eabi - - /*------------------------------------------------------------------- - * Zero the .bss, .sbss and .sbss2 sections. - * Must have r2 and r13 properly set. - *------------------------------------------------------------------*/ - bl zero_bss - - /*------------------------------------------------------------------- - * Create a minimal stack frame for this code, the caller of boot_card(). - *------------------------------------------------------------------*/ - addi r1,r1, -PPC_MINIMUM_STACK_FRAME_SIZE - - xor r3,r3,r3 - stw r3,0(r1) /* Terminate the chain of stack frames. */ - stw r3,4(r1) - stw r3,8(r1) - stw r3,12(r1) - lis r5,environ@ha - la r5,environ@l(r5) /* environp */ - - /*------------------------------------------------------------------- - * Call boot_card() with its arguments, the command-line pointer and - * the argument count, set to NULL. - *------------------------------------------------------------------*/ - li r4,0 /* argv */ - li r3,0 /* argc */ - .extern SYM (boot_card) - b SYM (boot_card) diff --git a/c/src/lib/libbsp/powerpc/virtex5/Makefile.am b/c/src/lib/libbsp/powerpc/virtex5/Makefile.am index 45a5da547d..81f78e198e 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/Makefile.am +++ b/c/src/lib/libbsp/powerpc/virtex5/Makefile.am @@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs # include # start -rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = rtems_crti.$(OBJEXT) @@ -27,7 +27,7 @@ librtemsbsp_a_SOURCES += ../shared/src/memcpy.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspreset-empty.c # start -librtemsbsp_a_SOURCES += start/start.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/virtex5/start/start.S # clock & timer librtemsbsp_a_SOURCES +=../../../../../../bsps/powerpc/shared/clock/p_clock.c diff --git a/c/src/lib/libbsp/powerpc/virtex5/start/start.S b/c/src/lib/libbsp/powerpc/virtex5/start/start.S deleted file mode 100644 index 2b12c18c89..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex5/start/start.S +++ /dev/null @@ -1,455 +0,0 @@ -/*!@file start.S -* -* @brief Initialization code to set up the CPU and call boot_card() -* -* This "BSP" targets the Xilinx Virtex XC5VFX70T and related parts. This -* BSP makes no assumptions on what firmware is loaded into the FPGA. -* -* Provides the .entry section code. This is the first code to run in -* the PPC after download to RAM. Excecution in this case starts at -* 'download_entry'. -* -* The entrypoint 'start' is provided for the case where a bootloader has -* initialized the CPU, and all that remains to do is to set up a C -* environment and call boot_card. -* -* Derived from virtex dlentry and others. -* -* Some portions of this code follow section 3.4 of the PPC440x5 CPU Core User's -* Manual v7.1 from IBM. Other parts were derived from examples provided -* by Xilinx in their ML510 Reference Designs, e.g., ml510_bsb1_design_ppc440. -* See boot.S in standalone/, for example. -* -* References: -* Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG200 (v1.8) -* http://www.xilinx.com/support/documentation/user_guides/ug200.pdf -* -* PowerPC 440x5 Embedded Processor Core User's Manual (Version 7.1) -* https://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_440_Embedded_Core -* -* @author Richard Claus <claus@SLAC.Stanford.edu> -* -* @date March 4, 2011 -- Created -* -* $Revision: 675 $ -* -* @verbatim Copyright 2011 -* by -* The Board of Trustees of the -* Leland Stanford Junior University. -* All rights reserved. -* -* Work supported by the U.S. Department of Energy under contract -* DE-AC03-76SF00515. -* -* Disclaimer Notice -* -* The items furnished herewith were developed under the sponsorship -* of the U.S. Government. Neither the U.S., nor the U.S. D.O.E., nor the -* Leland Stanford Junior University, nor their employees, makes any war- -* ranty, express or implied, or assumes any liability or responsibility -* for accuracy, completeness or usefulness of any information, apparatus, -* product or process disclosed, or represents that its use will not in- -* fringe privately-owned rights. Mention of any product, its manufactur- -* er, or suppliers shall not, nor is it intended to, imply approval, dis- -* approval, or fitness for any particular use. The U.S. and the Univer- -* sity at all times retain the right to use and disseminate the furnished -* items for any purpose whatsoever. Notice 91 02 01 -* -* @endverbatim -*/ - -#include <rtems/asm.h> -#include <rtems/powerpc/powerpc.h> -#include <rtems/powerpc/registers.h> - -#define V_TS_SZ_I 0x0290 // V,TS=0(Inst),SIZE=9,TID=0 -#define V_TS_SZ_D 0x0390 // V,TS=1(Data),SIZE=9,TID=0 -#define WIMG_U_S_0 0x043F // !(U0-3),!W, I,!M,!G,!E,UX,UW,UR,SX,SW,SR -#define WIMG_U_S_1 0x003F // !(U0-3),!W,!I,!M,!G,!E,UX,UW,UR,SX,SW,SR -#define PAGE_SZ 0x10000000 // 256 MB - -/* - * The virtex ELF link scripts support some special sections: - * .entry The actual entry point - * .vectors The section containing the interrupt entry veneers. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .text - * .data - * .bss - * see linker command file for section placement - * - * The initial stack is set to __stack_base - * - * All the entry veneer has to do is to clear the BSS. - */ - - .section .entry - - PUBLIC_VAR(download_entry) - PUBLIC_VAR(__rtems_entry_point) -SYM(download_entry): -SYM(__rtems_entry_point): - b startupDL /* Entry point used by xmd dow command */ - - PUBLIC_VAR (start) -SYM(start): - b startupBL /* Entry point used by bootLoader */ - -base_addr: - /*------------------------------------------------------------------- - * Parameters from linker - *-----------------------------------------------------------------*/ -toc_pointer: - .long __got_start -bss_length: - .long __bss_size -bss_addr: - .long __bss_start -stack_top: - .long __stack_base - - - .eject - - /*------------------------------------------------------------------ - * This code follows section 3.4 of the PPC440x5 CPU Core User's - * Manual. The numbers in the comments refer to the step numbers - * therein. Some of the implementation comes from examples provided - * by Xilinx in their ML510 Reference Designs, e.g., - * ml510_bsb1_design_ppc440. See boot.S in standalone/. - *------------------------------------------------------------------*/ - /*------------------------------------------------------------------ - * This code is designed to accomodate warm restarts, in which the - * application software triggers the restart of the system by branching - * to the following code (either boot or boot1) without causing - * one of the hardware resets: core, chip, system or JTAG (section - * 3.2,3 in the Power PC 440-S Embedded Processor Core User's Manual). - *-----------------------------------------------------------------*/ - - /* ----------------------------------------------------------------- - * Setup CPU - *-----------------------------------------------------------------*/ -first: li r0,0 // Clear r0 - - /* ----------------------------------------------------------------- - * Initialize the memory system. - *------------------------------------------------------------------*/ - iccci r0,r0 // 2. Invalidate instruction cache - dccci r0,r0 // 3. Invalidate data cache - msync // 4. Force in-progress data PLB ops to complete - - mfdbcr0 r2 // 5. Disable all debug events - lis r3,0x8100 - and r2,r2,r3 // Ignore EDM,TRAP to allow XMD use - mtdbcr0 r2 - li r2,-1 - mtdbsr r2 // 6. Initialize all debug event status - - /*------------------------------------------------------------------ - * Set Core Configuration Register 0 as follows: - * sum: 0x00206000 - * bit 1 off Parity Recovery Enable - * bit 4 off Cache Read Parity Enable - * bit 10 on Disable Store Gathering - * bit 11 off Disable APU Instruction Broadcast - * bit 16 off Disable Trace Broadcast - * bit 17:18 on Specifies behaviour of icbt,dcbt/dcbtst insts - * bit 23 off Force Load/Store Alignment - * bit 28:29 off Instruction Cache Speculative Line Count - * bit 30:31 off Instruction Cache Speculative Line Threshold - * NB: UG200/pg 21: Spec. prefetching must be disabled - *------------------------------------------------------------------*/ - - lis r2, 0x00206000@h // 7. Set CCR0: DSTG - ori r2,r2,0x00206000@l // Set CCR0: GDCBT, GICBT - mtccr0 r2 // Configure CCR0 - - mtspr PPC440_CCR1,r0 // 8. Clear CCR1 - - /*------------------------------------------------------------------ - * 9. Configure cache regions - *------------------------------------------------------------------*/ - mtspr PPC440_INV0,r0 - mtspr PPC440_INV1,r0 - mtspr PPC440_INV2,r0 - mtspr PPC440_INV3,r0 - mtspr PPC440_DNV0,r0 - mtspr PPC440_DNV1,r0 - mtspr PPC440_DNV2,r0 - mtspr PPC440_DNV3,r0 - mtspr PPC440_ITV0,r0 - mtspr PPC440_ITV1,r0 - mtspr PPC440_ITV2,r0 - mtspr PPC440_ITV3,r0 - mtspr PPC440_DTV0,r0 - mtspr PPC440_DTV1,r0 - mtspr PPC440_DTV2,r0 - mtspr PPC440_DTV3,r0 - - /*------------------------------------------------------------------ - * Cache victim limits - * floors 0, ceiling max to use the entire cache -- nothing locked - *------------------------------------------------------------------*/ - lis r2, 0x0001f800@h - ori r2,r2,0x0001f800@l - mtspr PPC440_IVLIM,r2 - mtspr PPC440_DVLIM,r2 - - /*------------------------------------------------------------------ - * Configure instruction and data cache regions: - * Set up register constants (r6,r7), page index (r5), address - * variable (r4), EPN_V_TS bits (r3) - * - * Word 0 bits: 0xX0000290, 0xX0000390 - * Bits Field Inst Data Description - * 0:21 EPN 0-15 0-15 Effective Page Number - * 22 V 1 1 Valid - * 23 TS 0 1 Translation Address Space - * 24:27 SIZE 9 9 Page Size (9 = 256 MB) - * 38:31 TPAR 0 0 Tag Parity - * 32:39 TID 0 0 Translation ID (in the MMUCR) - * - * Word 1 bits: 0x00000000, 0x00000000 - * Bits Field Inst Data Description - * 0:21 RPN 0 0 Real Page Number - * 22:23 PAR1 0 0 Parity for TLB word 1 - * 28:31 ERPN 0 0 Extended Real Page Number - * - * Word 2 bits: 0x0000043f, 0x00000c3f - * Bits Field Inst Data Description - * 0: 1 PAR2 0 0 Parity for TLB word 2 - * 16 U0 0 0 User-Defineable Storage Attribute 0 - * 17 U1 0 0 User-Defineable Storage Attribute 1 - * 18 U2 0 0 User-Defineable Storage Attribute 2 - * 19 U3 0 0 User-Defineable Storage Attribute 3 - * 20 W 0 0 Write-Through - * 21 I 1 1 Caching Inhibited - * 22 M 0 0 Memory Coherence Required - * 23 G 0 0 Guarded - * 24 E 0 0 Endian - * 26 UX 1 1 User State Execute Enable - * 27 UW 1 1 User State Write Enable - * 28 UR 1 1 User State Read Enable - * 29 SX 1 1 Supervisor State Execute Enable - * 30 SW 1 1 Supervisor State Write Enable - * 31 SR 1 1 Supervisor State Read Enable - *------------------------------------------------------------------*/ - - mtspr PPC440_MMUCR,r0 // 10a. Clear MMUCR - li r7,WIMG_U_S_1 // Word 2: Pages are NOT cache inhibited - lis r6, PAGE_SZ@h // Page size constant - ori r6,r6,PAGE_SZ@l - mr r5,r0 // TLB entry index - mr r4,r0 // Initialize RPN to zero - mflr r28 // Save return address - bl tlbSetup // 10b. Set up the TLBs - mtlr r28 // Restore return address - - /*------------------------------------------------------------------ - * Select whether Wait Enable, interrupts/exceptions and which address - * spaces should be enabled when application starts - *------------------------------------------------------------------*/ - lis r3, 0x00000000@h // 10d. MSR[IS]=0 MSR[DS]=0 - ori r3,r3,0x00000000@l - mtsrr1 r3 - mtsrr0 r28 // Return address - rfi // Context synchronize to invalidate shadow TLB contents - - - /*------------------------------------------------------------------- - * Entry point used when downloaded, e.g. through XMD - *------------------------------------------------------------------*/ -startupDL: - /*------------------------------------------------------------------- - * Do initialization up to the point where a context sync is required - *------------------------------------------------------------------*/ - bl first // Do first things first - - /*------------------------------------------------------------------- - * 11. Tell the processor where the exception vector table will be - *------------------------------------------------------------------*/ - .extern SYM(__vectors) - lis r1, __vectors@h /* set EVPR exc. vector prefix */ - mtspr BOOKE_IVPR,r1 - - /*------------------------------------------------------------------ - * Set up default exception and interrupt vectors - *------------------------------------------------------------------*/ - li r1,0 - mtivor0 r1 - addi r1,r1,0x10 - mtivor1 r1 - addi r1,r1,0x10 - mtivor2 r1 - addi r1,r1,0x10 - mtivor3 r1 - addi r1,r1,0x10 - mtivor4 r1 - addi r1,r1,0x10 - mtivor5 r1 - addi r1,r1,0x10 - mtivor6 r1 - addi r1,r1,0x10 - mtivor7 r1 - addi r1,r1,0x10 - mtivor8 r1 - addi r1,r1,0x10 - mtivor9 r1 - addi r1,r1,0x10 - mtivor10 r1 - addi r1,r1,0x10 - mtivor11 r1 - addi r1,r1,0x10 - mtivor12 r1 - addi r1,r1,0x10 - mtivor13 r1 - addi r1,r1,0x10 - mtivor14 r1 - addi r1,r1,0x10 - mtivor15 r1 - - /*------------------------------------------------------------------ - * 12. Configure debug facilities - *------------------------------------------------------------------*/ - mtdbcr1 r0 - mtdbcr2 r0 - mtiac1 r0 - mtiac2 r0 - mtiac3 r0 - mtiac4 r0 - mtdac1 r0 - mtdac2 r0 - mtdvc1 r0 - mtdvc2 r0 - mfdbcr0 r2 // Freeze timers on debug events - ori r2,r2,0x0001 - mtdbcr0 r2 - isync - - /*------------------------------------------------------------------- - * 13. Configure timer facilities - *------------------------------------------------------------------*/ - mtdec r0 // Clear Decrementer to prevent exception - mttbl r0 // Clear Timebase to prevent Fixed Interval.. - mttbu r0 // ..timer and Watchdog Timer exceptions - mtpit r0 // Programmable interval timer - li r2,-1 // -1 to clear TSR - mttsr r2 // Timer status register - - /*------------------------------------------------------------------- - * Clear out stale values in certain registers to avoid confusion - *------------------------------------------------------------------*/ - mtcrf 0xff,r0 // Need for simulation - mtctr r0 // Counter register - mtxer r0 // Fixed-point exception register - mtesr r0 // Exception syndrome register - mtdear r0 // Data exception address register - mtmcsr r0 // Machine check syndrome register - - /* Fall through */ - - /* ------------------------------------------------------------------- - * If a bootloader has run that has already initialized the CPU, - * which among other things has loaded this code into memory and - * jumped to start above, the initialization above does not need - * to be redone. Execution thus resumes here. - *------------------------------------------------------------------*/ - -startupBL: - /*------------------------------------------------------------------- - * Load the parameter table base address - *------------------------------------------------------------------*/ - lis r1, base_addr@h - ori r1,r1,base_addr@l - - /*------------------------------------------------------------------- - * Setup stack for RTEMS and call boot_card(). From this - * point forward registers will be used in accordance with the - * PowerPC EABI. - * - * boot_card() supervises the initialization of RTEMS and the C - * library. It calls bsp_start(), bsp_predriver_hook(), etc. - *------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - - /* Align as required by ABI */ - li r3,PPC_STACK_ALIGNMENT-1 - andc r1,r1,r3 - - /*------------------------------------------------------------------- - * Set up r2 and r13. Upon entry r1 must have a nonzero value - * as it will be stored in an "init done" flag. Stupid but true. - * r1 must also be set up as a stack pointer as __eabi() jumps - * to __init() which has a standard function prolog. - *------------------------------------------------------------------*/ - bl __eabi /* setup EABI and SYSV environment */ - - /*------------------------------------------------------------------- - * Zero the .bss, .sbss and .sbss2 sections. - * Must have r2 and r13 properly set. - *------------------------------------------------------------------*/ - bl zero_bss /* Assume Bank regs set up..., cache etc. */ - - /*------------------------------------------------------------------- - * Create a minimal stack frame for this code, the caller of boot_card(). - *------------------------------------------------------------------*/ - addi r1,r1,-PPC_MINIMUM_STACK_FRAME_SIZE - - xor r3,r3,r3 /* Clear r3 */ - stw r3,0(r1) /* Clear stack chain */ - stw r3,4(r1) - stw r3,8(r1) - stw r3,12(r1) - lis r5,environ@ha - la r5,environ@l(r5) /* environp */ - - /*------------------------------------------------------------------- - * Call boot_card() with its arguments, the command-line pointer and - * the argument count, set to NULL. - *------------------------------------------------------------------*/ - li r4,0 /* argv */ - li r3,0 /* argc */ - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - - - .eject - - /*------------------------------------------------------------------ - * Set up TLB entries: 2 entries are needed for the same 256MB page - * one for instruction memory and the other for data memory. - * (TS bit=0 for instructions) - *------------------------------------------------------------------*/ -tlbSetup: -1: ori r3,r4,V_TS_SZ_I // Fold V_TS_SZ in with EPN=RPN - tlbwe r3,r5,0 // Word 0: EPN_V_TS_SZ (Instructions) - tlbwe r4,r5,1 // Word 1: RPN_ERPN - tlbwe r7,r5,2 // Word 2: WIMG_U_S - ori r3,r4,V_TS_SZ_D // Fold V_TS_SZ in with EPN=RPN - addi r5,r5,1 // Next TLB entry - tlbwe r3,r5,0 // Word 0: EPN_V_TS_SZ (Data) - tlbwe r4,r5,1 // Word 1: RPN_ERPN - tlbwe r7,r5,2 // Word 2: WIMG_U_S - add r4,r4,r6 // Increment RPN to next 256MB block - addi r5,r5,1 // Next TLB entry - cmpwi r5,32 // Done yet? - bne 1b - li r0,0 -2: // Zero out index 32-63 TLB entries - tlbwe r0,r5,0 - tlbwe r0,r5,1 - tlbwe r0,r5,2 - addi r5,r5,1 - cmpwi r5,64 - bne 2b - - blr diff --git a/c/src/lib/libbsp/riscv/riscv_generic/Makefile.am b/c/src/lib/libbsp/riscv/riscv_generic/Makefile.am index 48b6634192..0d9e406111 100644 --- a/c/src/lib/libbsp/riscv/riscv_generic/Makefile.am +++ b/c/src/lib/libbsp/riscv/riscv_generic/Makefile.am @@ -18,7 +18,7 @@ dist_project_lib_DATA = startup/bsp_specs # Data # ############################################################################### -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/riscv/riscv_generic/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/riscv/riscv_generic/start/start.S b/c/src/lib/libbsp/riscv/riscv_generic/start/start.S deleted file mode 100644 index ccefb818bd..0000000000 --- a/c/src/lib/libbsp/riscv/riscv_generic/start/start.S +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham Almatary <hesham@alumni.york.ac.uk> - * - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include <bsp/linker-symbols.h> -#include <rtems/score/riscv-utility.h> -#include <rtems/score/cpu.h> -#include <rtems/asm.h> - -EXTERN(bsp_section_bss_begin) -EXTERN(bsp_section_bss_end) -EXTERN(ISR_Handler) -EXTERN(bsp_start_vector_table_size) -EXTERN(bsp_vector_table_size) -EXTERN(bsp_section_stack_begin) - -PUBLIC(bsp_start_vector_table_begin) -PUBLIC(bsp_start_vector_table_end) -PUBLIC(_start) - -.section .start, "wax" -TYPE_FUNC(_start) -SYM(_start): - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - la t0, ISR_Handler - csrw mtvec, t0 - - /* load stack and frame pointers */ - la sp, bsp_section_stack_begin - - /* Clearing .bss */ - la t0, bsp_section_bss_begin - la t1, bsp_section_bss_end - -_loop_clear_bss: - bge t0, t1, _end_clear_bss - SREG x0, 0(t0) - addi t0, t0, CPU_SIZEOF_POINTER - j _loop_clear_bss -_end_clear_bss: - - /* Init FPU unit if it's there */ - li t0, MSTATUS_FS - csrs mstatus, t0 - - j boot_card - - .align 4 -bsp_start_vector_table_begin: - .word _RISCV_Exception_default /* User int */ - .word _RISCV_Exception_default /* Supervisor int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine int */ - .word _RISCV_Exception_default /* User timer int */ - .word _RISCV_Exception_default /* Supervisor Timer int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine Timer int */ - .word _RISCV_Exception_default /* User external int */ - .word _RISCV_Exception_default /* Supervisor external int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine external int */ - .word _RISCV_Exception_default - .word _RISCV_Exception_default - .word _RISCV_Exception_default - .word _RISCV_Exception_default -bsp_start_vector_table_end: diff --git a/c/src/lib/libbsp/sh/gensh1/Makefile.am b/c/src/lib/libbsp/sh/gensh1/Makefile.am index f128180cbb..11a14693a0 100644 --- a/c/src/lib/libbsp/sh/gensh1/Makefile.am +++ b/c/src/lib/libbsp/sh/gensh1/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/sh/gensh1/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sh/gensh1/start/start.S b/c/src/lib/libbsp/sh/gensh1/start/start.S deleted file mode 100644 index 66b1c4e091..0000000000 --- a/c/src/lib/libbsp/sh/gensh1/start/start.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - - BEGIN_CODE - PUBLIC(start) -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - - mov.l vects_k,r0 ! update vbr to point to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! command line - mov.l main_k,r0 - jsr @r0 - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - END_CODE - - .align 2 -stack_k: - .long SYM(stack) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .stack,"aw" -#else - .section .stack -#endif -SYM(stack): - .long 0xdeaddead diff --git a/c/src/lib/libbsp/sh/gensh2/Makefile.am b/c/src/lib/libbsp/sh/gensh2/Makefile.am index 9a67271b6d..bcac43ec8a 100644 --- a/c/src/lib/libbsp/sh/gensh2/Makefile.am +++ b/c/src/lib/libbsp/sh/gensh2/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/sh/gensh2/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sh/gensh2/start/start.S b/c/src/lib/libbsp/sh/gensh2/start/start.S deleted file mode 100644 index cba17af740..0000000000 --- a/c/src/lib/libbsp/sh/gensh2/start/start.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Modified to reflect Hitachi EDK SH7045F: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * COPYRIGHT (c) 1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> - - BEGIN_CODE - PUBLIC(start) - -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ - ! Initialize minimal hardware - mov.l hw_init_k, r0 - jsr @r0 - nop !dead slot -#endif /* START_HW_INIT */ - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - -#ifndef STANDALONE_EVB - ! overlay monitor vectors onto RTEMS table template - ! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s" - mova vects_k,r0 - mov.l @r0, r1 ! Shadow vect tbl addr - stc vbr, r2 ! Original vect tbl addr - and #0, r0 - mov r0, r4 ! 0 in r4 and r0 - -!trapa #32 - or #0x80, r0 - mov.l @(r0,r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!cpu addr err - or #0x24, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill slot - or #0x18, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill inst - or #0x10, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!nmi - or #0x2c, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!User brk - or #0x30, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!sci0 err - or #0x80, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 -!sci rx - or #0x81, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - - stc vbr,r3 ! capture copy of monitor vbr - mov.l vbrtemp_k,r0 - mov.l r3, @r0 - mov.l vects_k,r0 ! point vbr to vectab - ldc r0,vbr -#endif /* ! STANDALONE_EVB */ - - ! call the mainline - mov #0,r4 ! command line - mov.l main_k,r0 - jsr @r0 - nop - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - mov.l vbrtemp_k,r0 ! restore original vbr - mov.l @r0,r3 - ldc r3, vbr - trapa #13 ! UBR capture by monitor - nop !debug dead-slot target - - END_CODE - - .align 2 -stack_k: - .long SYM(stack) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ -hw_init_k: - .long SYM(early_hw_init) -#endif /* START_HW_INIT */ -vbrtemp_k: - .long SYM(vbrtemp) -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .stack,"aw" -#else - .section .stack -#endif -SYM(stack): - .long 0xdeaddead - -#ifdef __ELF__ - .section .bss,"aw" -#else - .section .bss -#endif -SYM(vbrtemp): - .long 0x0 diff --git a/c/src/lib/libbsp/sh/gensh2/start/start.ram b/c/src/lib/libbsp/sh/gensh2/start/start.ram deleted file mode 100644 index 04e68238a6..0000000000 --- a/c/src/lib/libbsp/sh/gensh2/start/start.ram +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect Hitachi EDK SH7045F: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#include "asm.h" - - BEGIN_CODE - PUBLIC(start) - -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ - ! Initialize minimal hardware - mov.l hw_init_k, r0 - jsr @r0 - nop !debug dead-slot target -#endif /* START_HW_INIT */ - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - nop !debug dead-slot target - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - nop !debug dead-slot target - - ! overlay monitor vectors onto RTEMS table template - ! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s" - mova vects_k,r0 - mov.l @r0, r1 ! Shadow vect tbl addr - stc vbr, r2 ! Original vect tbl addr - and #0, r0 - mov r0, r4 ! 0 in r4 and r0 - -!trapa #32 - or #0x80, r0 - mov.l @(r0,r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!cpu addr err - or #0x24, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill slot - or #0x18, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill inst - or #0x10, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!nmi - or #0x2c, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!User brk - or #0x30, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!sci0 err - or #0x80, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 -!sci rx - or #0x81, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - - stc vbr,r3 ! capture copy of monitor vbr - mov.l vbrtemp_k,r0 - mov.l r3, @r0 - mov.l vects_k,r0 ! point vbr to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! argc - mov #0,r5 ! argv - can place in dead slot - mov.l main_k,r0 - jsr @r0 - nop !debug dead-slot target - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - or r0,r0 - jsr @r0 - nop !debug dead-slot target - - mov.l vbrtemp_k,r0 ! restore original vbr - mov.l @r0,r3 - ldc r3, vbr - trapa #13 ! UBR capture by monitor - nop !debug dead-slot target - - END_CODE - - .align 2 -stack_k: - .long SYM(stack) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ -hw_init_k: - .long SYM(hw_initialize) -#endif /* START_HW_INIT */ -vbrtemp_k: - .long SYM(vbrtemp) -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .stack,"aw" -#else - .section .stack -#endif -SYM(stack): - .long 0xdeaddead - -#ifdef __ELF__ - .section .bss,"aw" -#else - .section .bss -#endif -SYM(vbrtemp): - .long 0x0 - diff --git a/c/src/lib/libbsp/sh/gensh2/start/start.rom b/c/src/lib/libbsp/sh/gensh2/start/start.rom deleted file mode 100644 index 87fadd50f3..0000000000 --- a/c/src/lib/libbsp/sh/gensh2/start/start.rom +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include "asm.h" - - BEGIN_CODE - PUBLIC(start) -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 | number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - - mov.l vects_k,r0 ! update vbr to point to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! argc - mov.l main_k,r0 - jsr @r0 - mov #0,r5 ! argv - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - END_CODE - - .align 2 -stack_k: - .long SYM(stack) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .stack,"aw" -#else - .section .stack -#endif -SYM(stack): - .long 0xdeaddead diff --git a/c/src/lib/libbsp/sh/gensh4/Makefile.am b/c/src/lib/libbsp/sh/gensh4/Makefile.am index 92a9cdf6e7..97cea6de1a 100644 --- a/c/src/lib/libbsp/sh/gensh4/Makefile.am +++ b/c/src/lib/libbsp/sh/gensh4/Makefile.am @@ -6,7 +6,7 @@ include $(top_srcdir)/../../bsp.am dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/sh/gensh4/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sh/gensh4/start/start.S b/c/src/lib/libbsp/sh/gensh4/start/start.S deleted file mode 100644 index a695daaf8a..0000000000 --- a/c/src/lib/libbsp/sh/gensh4/start/start.S +++ /dev/null @@ -1,278 +0,0 @@ -/* - * start.S -- Initialization code for SH7750 generic BSP - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * Based on work: - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Modified to reflect Hitachi EDK SH7045F: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * COPYRIGHT (c) 1999-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include "rtems/score/sh4_regs.h" -#include "rtems/score/sh7750_regs.h" - - BEGIN_CODE - PUBLIC(start) - -/* - * Algorithm of the first part of the start(): - * - * 1. Initialize stack - * 2. Are we from reset or from gdb? Set value for boot_mode in r9. - * 3. Initialize hardware if we are from reset. Cache is off. - * 4. Copy data from flash to ram; set up boot mode and jump to real address. - * 5. Zero out bss. - * 6. Turn memory cach on. - */ - -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - mov.l initial_sr_k,r0 - ldc r0,ssr - ldc r0,sr - - ! let us see if we are from gdb stub or from power-on reset - bsr fake_func - nop -fake_func: - - sts pr, r0 - shlr8 r0 - mov.l reset_pc_value_shift_8_k, r1 - cmp/eq r0, r1 - movt r9 ! r9 == ! boot_mode - neg r9, r9 - add #1, r9 ! r9 == boot_mode - - ! what is in boot_mode? - cmp/pl r9 ! r9 > 0 -> T = 1 - - ! if boot_mode != SH4_BOOT_MODE_FLASH - bt hw_init_end - nop - -#if START_HW_INIT /* from $RTEMS_BSP.cfg */ - ! Initialize minimal hardware - ! to run hw_init we need to calculate its address - ! as it is before data copying - mov.l hw_init_k, r0 - mov.l copy_start_k, r1 - mov.l copy_end_k, r2 - cmp/ge r0, r1 - bt 0f - cmp/ge r0, r2 - bf 0f - ! if copy_start <= hw_init <= copy_end then - neg r1, r1 - mov.l copy_start_in_rom_k, r3 - add r1,r0 - add r3, r0 -0: - jsr @r0 - nop !delay slot -#endif /* START_HW_INIT */ -hw_init_end: - -#if COPY_DATA_FROM_ROM - ! copy data from rom to ram - mov.l copy_start_k, r0 - mov.l copy_end_k, r1 - mov.l copy_start_in_rom_k, r2 - - ! if copy_from == copy_to do not copy anything - cmp/eq r0, r2 - bt real_address - nop - -copy_data_cycle: - cmp/ge r1, r0 - bt end_of_copy_data_cycle - nop - mov.l @r2+, r3 - mov.l r3, @r0 - add #4, r0 - bra copy_data_cycle - nop - -end_of_copy_data_cycle: -#endif - ! go to 0x8....... adresses - mov.l real_address_k, r0 - lds r0, pr - rts - nop -real_address: - ! write boot_mode to ram - mov.l boot_mode_k, r5 - mov.l r9, @r5 - -zero_bss: - ! zero out bss - mov.l __bss_start_k,r0 - mov.l __bss_end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - nop - - ! Turn cache on - mov.l cache_on_k, r0 - jsr @r0 - nop !delay slot - - ! Save old value of VBR register. We will need it to allow - ! debugger agent hook exceptions. - mov.l __VBR_Saved_k,r0 - stc vbr,r5 - mov.l r5,@r0 - ! Set up VBR register - mov.l _vbr_base_k,r0 - ldc r0,vbr - - ! initialise fpscr for gcc - mov.l set_fpscr_k, r1 - jsr @r1 - nop - - ! Set FPSCR register - mov.l initial_fpscr_k,r0 - lds r0,fpscr - - ! call the mainline - mov #0,r4 ! argc - mov.l main_k,r0 - jsr @r0 - nop - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - .global _stop -_stop: - mov #11,r0 - mov #0,r4 - trapa #0x3f - nop -__stop: - bra __stop - nop - - END_CODE - - .align 2 -#if START_HW_INIT -copy_start_k: - .long copy_start -copy_end_k: - .long copy_end -#endif -#if COPY_DATA_FROM_ROM -copy_start_in_rom_k: - .long copy_start_in_rom -#endif - -real_address_k: - .long real_address -set_fpscr_k: - .long ___set_fpscr -_vbr_base_k: - .long SYM(_vbr_base) -__VBR_Saved_k: - .long SYM(_VBR_Saved) -stack_k: - .long SYM(stack) -__bss_start_k: - .long __bss_start -__bss_end_k: - .LONG __bss_end -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(_exit) - -#if START_HW_INIT /* from $RTEMS_BSP.cfg */ -hw_init_k: - .long SYM(early_hw_init) -#endif /* START_HW_INIT */ - -cache_on_k: - .long SYM(bsp_cache_on) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - - .align 2 -initial_sr_k: - .long SH4_SR_MD | SH4_SR_IMASK -initial_fpscr_k: -#ifdef __SH4__ - .long SH4_FPSCR_DN | SH4_FPSCR_PR | SH4_FPSCR_RM -#else - .long SH4_FPSCR_DN | SH4_FPSCR_RM -#endif - -reset_pc_value_shift_8_k: - .long 0xa00000 - -boot_mode_k: - .long _boot_mode - -#ifdef __ELF__ - .section .stack,"aw" -#else - .section .stack -#endif -SYM(stack): - .long 0xdeaddead - -#ifdef __ELF__ - .section .bss,"aw" -#else - .section .bss -#endif - - .global __sh4sim_dummy_register -__sh4sim_dummy_register: - .long 0 - - .section .data - .global _boot_mode -_boot_mode: - .long 0 diff --git a/c/src/lib/libbsp/sh/shsim/Makefile.am b/c/src/lib/libbsp/sh/shsim/Makefile.am index edd911aaad..94659c1be4 100644 --- a/c/src/lib/libbsp/sh/shsim/Makefile.am +++ b/c/src/lib/libbsp/sh/shsim/Makefile.am @@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/sh/shsim/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sh/shsim/start/start.S b/c/src/lib/libbsp/sh/shsim/start/start.S deleted file mode 100644 index cc4727b9ff..0000000000 --- a/c/src/lib/libbsp/sh/shsim/start/start.S +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include <bsp.h> - - BEGIN_CODE - PUBLIC(start) -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - - mov.l vects_k,r0 ! update vbr to point to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! command line - mov.l main_k,r0 - jsr @r0 - - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - END_CODE - - .align 2 -stack_k: - .long SYM(stack) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(_sys_exit) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .stack,"aw" -#else - .section .stack -#endif -SYM(stack): - .long 0xdeaddead -monvects_k: - .long SYM(monvects) diff --git a/c/src/lib/libbsp/sparc/erc32/Makefile.am b/c/src/lib/libbsp/sparc/erc32/Makefile.am index 489772f892..df9aefa8bb 100644 --- a/c/src/lib/libbsp/sparc/erc32/Makefile.am +++ b/c/src/lib/libbsp/sparc/erc32/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/sparc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sparc/leon2/Makefile.am b/c/src/lib/libbsp/sparc/leon2/Makefile.am index a20cd32605..1b15b0249f 100644 --- a/c/src/lib/libbsp/sparc/leon2/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon2/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/sparc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am index 7c76d726f0..a94dfd2c56 100644 --- a/c/src/lib/libbsp/sparc/leon3/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am @@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/sparc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/sparc/shared/start/start.S b/c/src/lib/libbsp/sparc/shared/start/start.S deleted file mode 100644 index 64498c6110..0000000000 --- a/c/src/lib/libbsp/sparc/shared/start/start.S +++ /dev/null @@ -1,374 +0,0 @@ -/** - * Common start code for SPARC. - * - * This is based on the file srt0.s provided with the binary - * distribution of the SPARC Instruction Simulator (SIS) found - * at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include <rtems/score/percpu.h> -#include <bspopts.h> - -#if defined(RTEMS_SMP) && defined(BSP_LEON3_SMP) - #define START_LEON3_ENABLE_SMP -#endif - -/* - * Unexpected trap will halt the processor by forcing it to error state - */ -#define BAD_TRAP \ - ta 0; \ - nop; \ - nop; \ - nop; - -/* - * System call optimized trap table entry - */ -#define FPDIS_TRAP(_handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - sethi %hi(SPARC_PSR_EF_MASK), %l3 - -/* - * System call optimized trap table entry - */ -#define IRQDIS_TRAP(_handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - or %l0, 0x0f00, %l3; ! Set PIL=0xf to disable IRQ - -/* - * System call optimized trap table entry - */ -#define IRQEN_TRAP(_handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - andn %l0, 0xf00, %l3; ! Set PIL=0 to Enable IRQ - -/* - * Window Overflow optimized trap table entry - */ -#define WOTRAP(_vector, _handler) \ - sethi %hi(_handler), %l4; \ - jmp %l4+%lo(_handler); \ - save; \ - nop - -/* - * Window Underflow optimized trap table entry - */ -#define WUTRAP(_vector, _handler) \ - mov %wim, %l3 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - sll %l3, 1, %l4 ! l4 = WIM << 1 - -/* - * Software trap. Treat as BAD_TRAP for the time being... - */ - -#define SOFT_TRAP BAD_TRAP - - .section ".text" - PUBLIC(start) - .global start, __bsp_mem_init - -SYM(start): -#if SYM(start) != start -start: -#endif - -/* - * The trap table has to be the first code in a boot PROM. But because - * the Memory Configuration comes up thinking we only have 4K of PROM, we - * cannot have a full trap table and still have room left over to - * reprogram the Memory Configuration register correctly. This file - * uses an abbreviated trap which has every entry which might be used - * before RTEMS installs its own trap table. - */ - - PUBLIC(trap_table) -SYM(trap_table): - - RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap - BAD_TRAP; ! 01 instruction access - ! exception - BAD_TRAP; ! 02 illegal instruction - BAD_TRAP; ! 03 privileged instruction -#if defined(SPARC_USE_LAZY_FP_SWITCH) - FPDIS_TRAP(SYM(syscall_lazy_fp_switch)); ! 04 fp disabled -#else - BAD_TRAP; ! 04 fp disabled -#endif - WOTRAP(5, SYM(window_overflow_trap_handler)); ! 05 window overflow - WUTRAP(6, SYM(window_underflow_trap_handler));! 06 window underflow - BAD_TRAP; ! 07 memory address not aligned - BAD_TRAP; ! 08 fp exception - BAD_TRAP; ! 09 data access exception - BAD_TRAP; ! 0A tag overflow - BAD_TRAP; ! 0B undefined - BAD_TRAP; ! 0C undefined - BAD_TRAP; ! 0D undefined - BAD_TRAP; ! 0E undefined - BAD_TRAP; ! 0F undefined - BAD_TRAP; ! 10 undefined - - /* - * ERC32 defined traps - */ - - BAD_TRAP; ! 11 masked errors - BAD_TRAP; ! 12 external 1 - BAD_TRAP; ! 13 external 2 - BAD_TRAP; ! 14 UART A RX/TX - BAD_TRAP; ! 15 UART B RX/TX - BAD_TRAP; ! 16 correctable memory error - BAD_TRAP; ! 17 UART error - BAD_TRAP; ! 18 DMA access error - BAD_TRAP; ! 19 DMA timeout - BAD_TRAP; ! 1A external 3 - BAD_TRAP; ! 1B external 4 - BAD_TRAP; ! 1C general purpose timer - BAD_TRAP; ! 1D real time clock - BAD_TRAP; ! 1E external 5 - BAD_TRAP; ! 1F watchdog timeout - - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined - BAD_TRAP; ! 24 cp_disabled - BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined - BAD_TRAP; ! 28 cp_exception - BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined - -/* - This is a sad patch to make sure that we know where the - MEC timer control register mirror is so we can stop the timers - from an external debugger. It is needed because the control - register is write-only. Trap 0x7C cannot occure in ERC32... - - We also use this location to store the last location of the - usable RAM in order not to overwrite the remote debugger with - the RTEMS work-space area. - -*/ - - .global SYM(_ERC32_MEC_Timer_Control_Mirror), SYM(rdb_start), SYM(CLOCK_SPEED) - -SYM(rdb_start): -SYM(_ERC32_MEC_Timer_Control_Mirror): - - BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined - -SYM(CLOCK_SPEED): - - .word 0x0a, 0, 0, 0 ! 7E (10 MHz default) - - BAD_TRAP; ! 7F undefined - - /* - * Software traps - * - * NOTE: At the risk of being redundant... this is not a full - * table. The setjmp on the SPARC requires a window flush trap - * handler and RTEMS will preserve the entries that were - * installed before. - */ - - TRAP( 0x80, SYM(syscall) ); ! 80 halt syscall SW trap - SOFT_TRAP; SOFT_TRAP; ! 81 - 82 - TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap - - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 - SOFT_TRAP; ! 88 - - /* - * SW Trap 9-15 Reserved for Operating System - * - * SPARC_SWTRAP_IRQDIS - * SPARC_SWTRAP_IRQEN - */ - IRQDIS_TRAP(SYM(syscall_irqdis)); ! 89 IRQ Disable syscall trap - IRQEN_TRAP(SYM(syscall_irqen)); ! 8A IRQ Enable syscall trap -#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH) - IRQDIS_TRAP(SYM(syscall_irqdis_fp)); ! 8B IRQ disable - ! and set PSR[EF] syscall trap -#else - SOFT_TRAP; ! 8B -#endif - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F - - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF - -/* - * This is the hard reset code. - */ - -#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ -#define WIM_INIT 2 -#define STACK_SIZE 16 * 1024 - - PUBLIC(hard_reset) -SYM(hard_reset): - -/* Common initialisation */ - - set SYM(trap_table), %g1 ! Initialize TBR - mov %g1, %tbr - - mov %psr, %g1 ! Initialize WIM - add %g1, 1, %g2 - and %g2, 0x7, %g2 - set 1, %g3 - sll %g3, %g2, %g3 - mov %g3, %wim - - or %g1, 0xf20, %g1 - wr %g1, %psr ! enable traps and disable ints - - nop - nop - nop - - sethi %hi(_Per_CPU_Information), %g6 ! get per-CPU control - add %g6, %lo(_Per_CPU_Information), %g6 - -#if defined(START_LEON3_ENABLE_SMP) - rd %asr17, %o0 ! get CPU identifier - srl %o0, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, %o0 - - sll %o0, PER_CPU_CONTROL_SIZE_LOG2, %l0 - add %g6, %l0, %g6 - - /* If LEON3_Boot_Cpu < 0 then assign us as boot CPU and continue. */ - set SYM(LEON3_Boot_Cpu), %o1 - ld [%o1], %o2 - tst %o2 - bneg .Lbootcpu - nop - - ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp ! set stack pointer - sub %sp, 4, %sp ! stack starts at end of area - 4 - andn %sp, 0x0f, %sp ! align stack on 16-byte boundary - mov %sp, %fp ! set frame pointer - - call SYM(bsp_start_on_secondary_processor) ! does not return - sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp -.Lbootcpu: - st %o0, [%o1] -#endif - - set (SYM(rdb_start)), %g5 ! End of RAM - st %sp, [%g5] - sub %sp, 4, %sp ! stack starts at end of RAM - 4 - andn %sp, 0x0f, %sp ! align stack on 16-byte boundary - mov %sp, %fp ! Set frame pointer - nop - - /* - * Copy the initialized data to RAM - * - * FROM: _data_load_start - * TO: _data_start - * LENGTH: (__bss_start - _data_start) bytes - */ - - sethi %hi(_data_load_start),%g1 ! g1 = start of initialized data in ROM - or %g1,%lo(_data_load_start),%g1 - - sethi %hi(_data_start),%g3 ! g3 = start of initialized data in RAM - or %g3,%lo(_data_start),%g3 - - sethi %hi(__bss_start), %g2 ! g2 = end of initialized data in RAM - or %g2,%lo(__bss_start),%g2 - - cmp %g1, %g3 - be 1f - nop - -copy_data: - ldd [%g1], %g4 - std %g4 , [%g3] ! copy this double word - add %g3, 8, %g3 ! bump the destination pointer - add %g1, 8, %g1 ! bump the source pointer - cmp %g3, %g2 ! Is the pointer past the end of dest? - bl copy_data - nop - - /* clear the bss */ -1: - - sethi %hi(_end),%g3 - or %g3,%lo(_end),%g3 ! g3 = end of bss - mov %g0,%g1 ! so std has two zeros -zerobss: - std %g0,[%g2] - add %g2,8,%g2 - cmp %g2,%g3 - bleu,a zerobss - nop - - mov %g0, %o0 ! command line - call SYM(boot_card) ! does not return - sub %sp, 0x60, %sp ! room for boot_card to save args - -/* end of file */ diff --git a/c/src/lib/libbsp/sparc64/niagara/Makefile.am b/c/src/lib/libbsp/sparc64/niagara/Makefile.am index a0614da7ba..c9489bdccc 100644 --- a/c/src/lib/libbsp/sparc64/niagara/Makefile.am +++ b/c/src/lib/libbsp/sparc64/niagara/Makefile.am @@ -9,7 +9,7 @@ noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/sparc64/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) @@ -32,7 +32,7 @@ librtemsbsp_a_SOURCES += ../shared/helenos/boot/generic/string.c librtemsbsp_a_SOURCES += ../shared/helenos/boot/sparc64/loader/ofwarch.c librtemsbsp_a_SOURCES += ../shared/helenos/boot/sparc64/loader/main.c librtemsbsp_a_SOURCES += ../shared/helenos/boot/sparc64/loader/ofwasm.S -librtemsbsp_a_SOURCES += start/bspinit.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/sparc64/niagara/start/bspinit.S librtemsbsp_a_SOURCES += ../shared/asm/asm.S librtemsbsp_a_SOURCES +=../../../../../../bsps/sparc64/shared/clock/ckinit.c diff --git a/c/src/lib/libbsp/sparc64/niagara/start/bspinit.S b/c/src/lib/libbsp/sparc64/niagara/start/bspinit.S deleted file mode 100644 index 70ddd0ff6e..0000000000 --- a/c/src/lib/libbsp/sparc64/niagara/start/bspinit.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * bspinit.S - * - * COPYRIGHT (c) 2010 Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * - * BSP specific initialization for Sparc64 RTEMS -- sun4v BSP - * - * This code defines start code specific to the sun4v BSP - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> - -#define STACK_WINDOW_SAVE_AREA_SIZE (16*8) - -.section .text - -PUBLIC(_BSP_init) - .global _BSP_init - SYM(_BSP_init): - - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - - - - ret - restore - diff --git a/c/src/lib/libbsp/sparc64/shared/start/start.S b/c/src/lib/libbsp/sparc64/shared/start/start.S deleted file mode 100644 index 92c2177c1e..0000000000 --- a/c/src/lib/libbsp/sparc64/shared/start/start.S +++ /dev/null @@ -1,151 +0,0 @@ -# -# Copyright (c) 2006 Martin Decky -# Copyright (c) 2006 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -/* - * start.S - * - * Start code for Sparc64 RTEMS - * - * This is based on the boot.S file of the HelenOS sparc64 architecture. - * http://www.helenos.org/ - * ${helenos}/boot/arch/sparc64/loader/boot.S - * - * Modifications for the RTEMS executive are - * COPYRIGHT (c) 2010 Gedare Bloom. - * COPYRIGHT (c) 2010 Eugen Leontie. - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> - -#define PSTATE_PRIV_BIT 4 - -.register %g2, #scratch -.register %g3, #scratch -.register %g6, #scratch -.register %g7, #scratch - -.section BOOTSTRAP, "ax" - -PUBLIC(_start) - .global _start - SYM(_start): - start: - b 1f - nop - - /* - * This header forces SILO to load the image at 0x4000. - * More precisely, SILO will think this is an old version of Linux. - */ - .ascii "HdrS" - .word 0 - .half 0 - .half 0 - .half 0 - .half 0 - .global silo_ramdisk_image - silo_ramdisk_image: - .word 0 - .global silo_ramdisk_size - silo_ramdisk_size: - .word 0 - - .align 8 - 1: - /* - * Disable interrupts and disable address masking. - */ - wrpr %g0, PSTATE_PRIV_BIT, %pstate - - wrpr %g0, SPARC_NUMBER_OF_REGISTER_WINDOWS - 2, %cansave ! set maximum saveable windows - wrpr %g0, 0, %canrestore ! get rid of windows we will never need again - wrpr %g0, 0, %otherwin ! make sure the window state is consistent - wrpr %g0, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel - - /* g4 needs to be cleared for gcc */ - mov %g0, %g4 - - /* Clear the bss */ - setx SYM(bss_start), %l0, %g2 ! g2 = start of bss - setx SYM(_end), %l0, %g3 ! g3 = end of bss -zerobss: - stx %g0, [%g2] - add %g2, 8, %g2 - cmp %g2, %g3 - bleu,a zerobss - nop - - /* Install stack */ -setstack: - set SYM(StackStart), %sp - add %sp, -STACK_BIAS, %sp - - /* BSP-specific pre-bootcard initializations */ - call SYM(_BSP_init) - nop - - setx ofw_cif, %l0, %l1 - - call ofw_init ! initialize OpenFirmware - stx %o4, [%l1] - - call bootstrap - nop - - - /* Set up ISR handler for interrupt enable/disable */ - setx SYM(syscall), %l0, %o1 - setx param_space, %l0, %o2 - call SYM(_CPU_ISR_install_raw_handler) - mov 0x100, %o0 - - /* Don't need to copy initialized data to RAM--link puts all in RAM already */ - - mov %g0, %o0 ! clear command line passed to main - call SYM(boot_card) - sub %sp, 0x60, %sp ! make room on stack (necessary?) - - call SYM(halt) - nop - -halted: nop - b SYM(halted) - -.section BOOTSTRAP - .align CPU_ALIGNMENT - .space 32768 - SPARC64_MINIMUM_STACK_FRAME_SIZE ! 32K boot stack grows down - .global StackStart - StackStart: - .space SPARC64_MINIMUM_STACK_FRAME_SIZE ! initial stack frame - -.section BOOTSTRAP - .align CPU_ALIGNMENT - param_space: - .space 8 diff --git a/c/src/lib/libbsp/sparc64/shared/start/trap_table.S b/c/src/lib/libbsp/sparc64/shared/start/trap_table.S deleted file mode 100644 index dbfccdf99e..0000000000 --- a/c/src/lib/libbsp/sparc64/shared/start/trap_table.S +++ /dev/null @@ -1,155 +0,0 @@ -/* - * trap_table.S - * - * trap code for Sparc64 RTEMS. - * - * COPYRIGHT (c) 2010 Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This code defines the space for the trap table used by sun4u. - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> -#include <traptable.h> - -.register %g2, #scratch - -.macro JUMP_TO_TRAP offset - sethi %hi(real_trap_table), %g1; - sethi %hi(\offset), %g2; - or %g1, %lo(real_trap_table), %g1; - or %g2, %lo(\offset), %g2; ! g2 = offset - ldx [%g1], %g1; ! g1 = real_trap_table - add %g1, %g2, %g1; ! g1 = real_trap_table[offset] - jmpl %g1, %g0; - nop; -.endm - -! space to save a pointer to the real trap table -.section .data - .align 8 - .global real_trap_table - SYM(real_trap_table): - .space 8 - -.section .text - .align (TABLE_SIZE) -PUBLIC(trap_table) - SYM(trap_table): - - .irp idx, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, \ - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, \ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, \ - 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, \ - 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, \ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, \ - 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, \ - 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, \ - 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, \ - 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, \ - 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \ - 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, \ - 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, \ - 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ - 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, \ - 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, \ - 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, \ - 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, \ - 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, \ - 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, \ - 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, \ - 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, \ - 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, \ - 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, \ - 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, \ - 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, \ - 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, \ - 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, \ - 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, \ - 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, \ - 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, \ - 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, \ - 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, \ - 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, \ - 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, \ - 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, \ - 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, \ - 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, \ - 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, \ - 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, \ - 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, \ - 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, \ - 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, \ - 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, \ - 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, \ - 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, \ - 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, \ - 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, \ - 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, \ - 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, \ - 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 - - .org trap_table + ((\idx)*32) - JUMP_TO_TRAP( ((\idx)*32) ); - .endr - - .irp idx, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, \ - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, \ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, \ - 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, \ - 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, \ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, \ - 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, \ - 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, \ - 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, \ - 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, \ - 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \ - 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, \ - 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, \ - 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ - 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, \ - 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, \ - 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, \ - 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, \ - 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, \ - 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, \ - 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, \ - 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, \ - 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, \ - 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, \ - 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, \ - 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, \ - 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, \ - 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, \ - 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, \ - 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, \ - 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, \ - 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, \ - 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, \ - 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, \ - 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, \ - 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, \ - 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, \ - 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, \ - 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, \ - 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, \ - 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, \ - 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, \ - 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, \ - 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, \ - 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, \ - 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, \ - 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, \ - 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, \ - 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, \ - 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, \ - 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 - - .org trap_table + 512*32 + ((\idx)*32) - JUMP_TO_TRAP( 512*32 + ((\idx)*32) ); - .endr - diff --git a/c/src/lib/libbsp/sparc64/usiii/Makefile.am b/c/src/lib/libbsp/sparc64/usiii/Makefile.am index e693732c05..ee7f4957f5 100644 --- a/c/src/lib/libbsp/sparc64/usiii/Makefile.am +++ b/c/src/lib/libbsp/sparc64/usiii/Makefile.am @@ -17,7 +17,7 @@ noinst_PROGRAMS = -start.$(OBJEXT): ../shared/start/start.S +start.$(OBJEXT): ../../../../../../bsps/sparc64/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) @@ -40,11 +40,11 @@ librtemsbsp_a_SOURCES += ../shared/helenos/boot/sparc64/loader/ofwarch.c librtemsbsp_a_SOURCES += ../shared/helenos/boot/sparc64/loader/main.c librtemsbsp_a_SOURCES += ../shared/helenos/boot/sparc64/loader/ofwasm.S librtemsbsp_a_SOURCES += ../shared/asm/asm.S -librtemsbsp_a_SOURCES += start/bspinit.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/sparc64/usiii/start/bspinit.S librtemsbsp_a_SOURCES += ../shared/helenos/kernel/sparc64/src/cache.S librtemsbsp_a_SOURCES += ../shared/helenos/kernel/sparc64/src/sun4u/takemmu.S -librtemsbsp_a_SOURCES += ../shared/start/trap_table.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/sparc64/shared/start/trap_table.S librtemsbsp_a_SOURCES +=../../../../../../bsps/sparc64/shared/clock/ckinit.c diff --git a/c/src/lib/libbsp/sparc64/usiii/start/bspinit.S b/c/src/lib/libbsp/sparc64/usiii/start/bspinit.S deleted file mode 100644 index 8da1d95eab..0000000000 --- a/c/src/lib/libbsp/sparc64/usiii/start/bspinit.S +++ /dev/null @@ -1,53 +0,0 @@ -/* - * BSP specific initialization for Sparc64 RTEMS -- sun4u BSP - * - * This code defines start code specific to the sun4u BSP - */ - -/* - * COPYRIGHT (c) 2010 Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include <rtems/score/cpu.h> - -#include <traptable.h> - -#define LSU_CR_IM_MASK (0x0004) /* bit 2 */ -#define LSU_CR_DM_MASK (0x0008) /* bit 3 */ - -#define STACK_WINDOW_SAVE_AREA_SIZE (16*8) - -.register %g2, #scratch -.register %g3, #scratch - -.section .text - -PUBLIC(_BSP_init) -.global _BSP_init - SYM(_BSP_init): - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - - ! copy the tba - sethi %hi(real_trap_table), %o0 - rdpr %tba, %o2 - stx %o2, [%o0 + %lo(real_trap_table)] - -! /* copy firmware trap table so that RTEMS can install ISR handlers */ -! setx SYM(trap_table), %l0, %o0 -! rdpr %tba, %o1 -! set TABLE_SIZE, %o2 -! call memcpy -! nop - - mov %g0, %o0 - call _take_mmu - nop - - ret - restore - diff --git a/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am b/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am index 367f838c5d..fdd6cab5b5 100644 --- a/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am +++ b/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am @@ -11,7 +11,7 @@ dist_project_lib_DATA = startup/bsp_specs noinst_PROGRAMS = -start.$(OBJEXT): start/start.S +start.$(OBJEXT): ../../../../../../bsps/v850/gdbv850sim/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) diff --git a/c/src/lib/libbsp/v850/gdbv850sim/start/start.S b/c/src/lib/libbsp/v850/gdbv850sim/start/start.S deleted file mode 100644 index 419e635393..0000000000 --- a/c/src/lib/libbsp/v850/gdbv850sim/start/start.S +++ /dev/null @@ -1,78 +0,0 @@ -# NEC V850 startup code - - .section .text - .global _start - -_start: - -#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) - - movea 255, r0, r20 - mov 65535, r21 - mov hilo(_stack), sp - mov hilo(__ep), ep - mov hilo(__gp), gp - mov hilo(__ctbp), r6 - ldsr r6, ctbp - mov hilo(_edata), r6 - mov hilo(_end), r7 -.L0: - st.w r0, 0[r6] - addi 4, r6, r6 - cmp r7, r6 - bl .L0 -.L1: - jarl ___main, r31 - addi -16, sp, sp - mov 0, r6 - mov 0, r7 - mov 0, r8 - /* jarl _main, r31 */ - jarl _boot_card, r31 - mov r10, r6 - jarl _exit, r31 - -# else - movea 255, r0, r20 - mov r0, r21 - ori 65535, r0, r21 - movhi hi(_stack), r0, sp - movea lo(_stack), sp, sp - movhi hi(__ep), r0, ep - movea lo(__ep), ep, ep - movhi hi(__gp), r0, gp - movea lo(__gp), gp, gp - - movhi hi(_edata), r0, r6 - movea lo(_edata), r6, r6 - movhi hi(_end), r0, r7 - movea lo(_end), r7, r7 -.L0: - st.b r0, 0[r6] - addi 1, r6, r6 - cmp r7, r6 - bl .L0 -.L1: - /* jarl ___main, r31 */ - addi -16, sp, sp - mov 0, r6 - mov 0, r7 - mov 0, r8 - /* jarl _main, r31 */ - jarl _boot_card, r31 - mov r10, r6 -.L2: - br .L2 - /* jarl _exit, r31 */ -# endif - -#if 0 - .section .stack -_stack: .long 1 -#endif - - .section .data - .global ___dso_handle - .weak ___dso_handle -___dso_handle: - .long 0 |