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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-06-19 14:24:36 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-06-19 14:24:36 +0000 |
| commit | b7dac386bfbe57e375c422d0e72095e15b816e8e (patch) | |
| tree | e94ab201f6547350afdeb5de623597727e77f6de /c/src/lib/libbsp | |
| parent | 2001-06-19 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-b7dac386bfbe57e375c422d0e72095e15b816e8e.tar.bz2 | |
2001-06-19 Joel Sherrill <joel@OARcorp.com>
* start/start.S: Reverse sense of conditional compilation so the
code will compile for a cpu32.
Diffstat (limited to 'c/src/lib/libbsp')
| -rw-r--r-- | c/src/lib/libbsp/m68k/sim68000/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/sim68000/start/start.S | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/m68k/sim68000/ChangeLog b/c/src/lib/libbsp/m68k/sim68000/ChangeLog index a0eef986b4..ba00585aa3 100644 --- a/c/src/lib/libbsp/m68k/sim68000/ChangeLog +++ b/c/src/lib/libbsp/m68k/sim68000/ChangeLog @@ -1,3 +1,8 @@ +2001-06-19 Joel Sherrill <joel@OARcorp.com> + + * start/start.S: Reverse sense of conditional compilation so the + code will compile for a cpu32. + 2001-05-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * configure.in: Add bspopts.h. diff --git a/c/src/lib/libbsp/m68k/sim68000/start/start.S b/c/src/lib/libbsp/m68k/sim68000/start/start.S index ebf56d063c..805ce93218 100644 --- a/c/src/lib/libbsp/m68k/sim68000/start/start.S +++ b/c/src/lib/libbsp/m68k/sim68000/start/start.S @@ -55,7 +55,7 @@ V____IPC: .long start - V___ISSP | Lots of macros, how-ever it creates a simple ROM vector table | -#if defined(mcpu32) +#if !defined(mcpu32) .space 1016 | reserve space for rest of vectors #else #define MAKE_EXCEPTION_VECTOR(n) V___##n: .long (_CPU_ISR_jump_table + (n * 10)) |