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authorJoel Sherrill <joel.sherrill@OARcorp.com>1997-09-03 22:05:51 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1997-09-03 22:05:51 +0000
commit8d053460ffe4c68b70d0f50e9ac7912d1d0e7d47 (patch)
treefa066b23ca6c2193cb300690549a6b54469121a9 /c/src/lib/libbsp
parentMore specific information on error code. (diff)
downloadrtems-8d053460ffe4c68b70d0f50e9ac7912d1d0e7d47.tar.bz2
Fix from Eric Norum. Here is the comment:
Enable SDMA operation during FREEZE. It seems that disabling SDMA during freeze makes the SMC channels work erratically.
Diffstat (limited to 'c/src/lib/libbsp')
-rw-r--r--c/src/lib/libbsp/m68k/gen68360/startup/init68360.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
index a4adde7582..5c40acd358 100644
--- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
+++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
@@ -154,7 +154,7 @@ void _Init68360 (void)
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)
- * Disable SDMA during FREEZE
+ * Enable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register):
@@ -167,7 +167,7 @@ void _Init68360 (void)
* Vector base 128
* SCCs priority grouped at top of table
*/
- m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+ m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128);