LEON: converted AT697,GRPCi,GRPCI2,PCIF to BSD header

4 files changed, 31 insertions, 40 deletions

diff --git a/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c b/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c
index d7064234be..9927473f08 100644
--- a/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c
+++ b/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c
@@ -97,9 +97,6 @@
 #define DBG(x...) 
 #endif
 
-#define PCI_INVALID_VENDORDEVICEID	0xffffffff
-#define PCI_MULTI_FUNCTION		0x80
-
 struct at697pci_regs {
     volatile unsigned int pciid1;        /* 0x80000100 - PCI Device identification register 1         */
     volatile unsigned int pcisc;         /* 0x80000104 - PCI Status & Command                         */
diff --git a/c/src/lib/libbsp/sparc/shared/pci/grpci.c b/c/src/lib/libbsp/sparc/shared/pci/grpci.c
index b417956d90..54e5ef713f 100644
--- a/c/src/lib/libbsp/sparc/shared/pci/grpci.c
+++ b/c/src/lib/libbsp/sparc/shared/pci/grpci.c
@@ -69,9 +69,6 @@
 #define DBG(x...) 
 #endif
 
-#define PCI_INVALID_VENDORDEVICEID	0xffffffff
-#define PCI_MULTI_FUNCTION		0x80
-
 /*
  * Bit encode for PCI_CONFIG_HEADER_TYPE register
  */
@@ -438,10 +435,10 @@ static int grpci_hw_init(struct grpci_priv *priv)
 
 	if ( !priv->bt_enabled && ((priv->regs->page0 & PAGE0_BTEN) == PAGE0_BTEN) ) {
 		/* Byte twisting is on, turn it off */
-		grpci_cfg_w32(host, PCI_BASE_ADDRESS_0, 0xffffffff);
-		grpci_cfg_r32(host, PCI_BASE_ADDRESS_0, &addr);
+		grpci_cfg_w32(host, PCIR_BAR(0), 0xffffffff);
+		grpci_cfg_r32(host, PCIR_BAR(0), &addr);
 		/* Setup bar0 to nonzero value */
-		grpci_cfg_w32(host, PCI_BASE_ADDRESS_0,
+		grpci_cfg_w32(host, PCIR_BAR(0),
 				CPU_swap_u32(0x80000000));
 		/* page0 is accessed through upper half of bar0 */
 		addr = (~CPU_swap_u32(addr)+1)>>1;
@@ -454,19 +451,19 @@ static int grpci_hw_init(struct grpci_priv *priv)
 	}
 
 	/* Get the GRPCI Host PCI ID */
-	grpci_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+	grpci_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
 
 	/* set 1:1 mapping between AHB -> PCI memory */
 	priv->regs->cfg_stat = (priv->regs->cfg_stat & 0x0fffffff) | priv->pci_area;
 
 	/* determine size of target BAR1 */
-	grpci_cfg_w32(host, PCI_BASE_ADDRESS_1, 0xffffffff);
-	grpci_cfg_r32(host, PCI_BASE_ADDRESS_1, &addr);
+	grpci_cfg_w32(host, PCIR_BAR(1), 0xffffffff);
+	grpci_cfg_r32(host, PCIR_BAR(1), &addr);
 	priv->bar1_size = (~(addr & ~0xf)) + 1;
 
 	/* and map system RAM at pci address 0x40000000 */
 	priv->bar1_pci_adr &= ~(priv->bar1_size - 1); /* Fix alignment of BAR1 */
-	grpci_cfg_w32(host, PCI_BASE_ADDRESS_1, priv->bar1_pci_adr);
+	grpci_cfg_w32(host, PCIR_BAR(1), priv->bar1_pci_adr);
 	priv->regs->page1 = priv->bar1_pci_adr;
 
 	/* Translate I/O accesses 1:1 */
@@ -476,13 +473,13 @@ static int grpci_hw_init(struct grpci_priv *priv)
 	 * size will result in poor performance (256 word fetches), 0xff
 	 * will set it according to the max size of the PCI FIFO.
 	 */
-	grpci_cfg_w8(host, PCI_CACHE_LINE_SIZE, 0xff);
-	grpci_cfg_w8(host, PCI_LATENCY_TIMER, 0x40);
+	grpci_cfg_w8(host, PCIR_CACHELNSZ, 0xff);
+	grpci_cfg_w8(host, PCIR_LATTIMER, 0x40);
 
 	/* set as bus master and enable pci memory responses */  
-	grpci_cfg_r32(host, PCI_COMMAND, &data);
-	data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-	grpci_cfg_w32(host, PCI_COMMAND, data);
+	grpci_cfg_r32(host, PCIR_COMMAND, &data);
+	data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+	grpci_cfg_w32(host, PCIR_COMMAND, data);
 
 	/* unmask all PCI interrupts at PCI Core, not all GRPCI cores support
 	 * this
diff --git a/c/src/lib/libbsp/sparc/shared/pci/grpci2.c b/c/src/lib/libbsp/sparc/shared/pci/grpci2.c
index 07bc8038b3..cc685cdf2c 100644
--- a/c/src/lib/libbsp/sparc/shared/pci/grpci2.c
+++ b/c/src/lib/libbsp/sparc/shared/pci/grpci2.c
@@ -81,9 +81,6 @@
 #define DBG(x...) 
 #endif
 
-#define PCI_INVALID_VENDORDEVICEID	0xffffffff
-#define PCI_MULTI_FUNCTION		0x80
-
 /*
  * GRPCI2 APB Register MAP
  */
@@ -654,10 +651,10 @@ static int grpci2_hw_init(struct grpci2_priv *priv)
 		regs->ahbmst_map[i] = priv->pci_area;
 
 	/* Get the GRPCI2 Host PCI ID */
-	grpci2_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+	grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
 
 	/* Get address to first (always defined) capability structure */
-	grpci2_cfg_r8(host, PCI_CAP_PTR, &capptr);
+	grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
 	if (capptr == 0)
 		return -1;
 
@@ -679,17 +676,17 @@ static int grpci2_hw_init(struct grpci2_priv *priv)
 
 		pciadr = barcfg[i].pciadr;
 		ahbadr = barcfg[i].ahbadr;
-		size |= PCI_BASE_ADDRESS_MEM_PREFETCH;
+		size |= PCIM_BAR_MEM_PREFETCH;
 
 		grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
 		grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
-		grpci2_cfg_w32(host, PCI_BASE_ADDRESS_0+i*4, pciadr);
+		grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
 	}
 
 	/* set as bus master and enable pci memory responses */  
-	grpci2_cfg_r32(host, PCI_COMMAND, &data);
-	data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-	grpci2_cfg_w32(host, PCI_COMMAND, data);
+	grpci2_cfg_r32(host, PCIR_COMMAND, &data);
+	data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+	grpci2_cfg_w32(host, PCIR_COMMAND, data);
 
 	/* Enable Error respone (CPU-TRAP) on illegal memory access */
 	regs->ctrl = CTRL_ER | CTRL_PE;
diff --git a/c/src/lib/libbsp/sparc/shared/pci/pcif.c b/c/src/lib/libbsp/sparc/shared/pci/pcif.c
index 32de562283..e01a68e430 100644
--- a/c/src/lib/libbsp/sparc/shared/pci/pcif.c
+++ b/c/src/lib/libbsp/sparc/shared/pci/pcif.c
@@ -363,7 +363,7 @@ static int pcif_hw_init(struct pcif_priv *priv)
 	regs->intr = 0;
 
 	/* Get the PCIF Host PCI ID */
-	pcif_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+	pcif_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
 
 	/* set 1:1 mapping between AHB -> PCI memory space, for all Master cores */
 	for ( mst=0; mst<16; mst++) {
@@ -383,21 +383,21 @@ static int pcif_hw_init(struct pcif_priv *priv)
 	regs->bars[3] = 0;
 
 	/* determine size of target BAR1 */
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_1, 0xffffffff);
-	pcif_cfg_r32(host, PCI_BASE_ADDRESS_1, &size);
+	pcif_cfg_w32(host, PCIR_BAR(1), 0xffffffff);
+	pcif_cfg_r32(host, PCIR_BAR(1), &size);
 	priv->bar1_size = (~(size & ~0xf)) + 1;
 
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_0, 0);
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_1, SYSTEM_MAINMEM_START);
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_2, 0);
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_3, 0);
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_4, 0);
-	pcif_cfg_w32(host, PCI_BASE_ADDRESS_5, 0);
+	pcif_cfg_w32(host, PCIR_BAR(0), 0);
+	pcif_cfg_w32(host, PCIR_BAR(1), SYSTEM_MAINMEM_START);
+	pcif_cfg_w32(host, PCIR_BAR(2), 0);
+	pcif_cfg_w32(host, PCIR_BAR(3), 0);
+	pcif_cfg_w32(host, PCIR_BAR(4), 0);
+	pcif_cfg_w32(host, PCIR_BAR(5), 0);
 
 	/* set as bus master and enable pci memory responses */  
-	pcif_cfg_r32(host, PCI_COMMAND, &data);
-	data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-	pcif_cfg_w32(host, PCI_COMMAND, data);
+	pcif_cfg_r32(host, PCIR_COMMAND, &data);
+	data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+	pcif_cfg_w32(host, PCIR_COMMAND, data);
 
 	/* Successful */
 	return 0;