2010-06-17 Joel Sherrill <joel.sherrill@oarcorp.com>

	* ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
	preinstall.am, include/bsp.h, include/tm27.h,
	make/custom/niagara.cfg, start/bspinit.S: New files.

1 files changed, 69 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/sparc64/niagara/README b/c/src/lib/libbsp/sparc64/niagara/README
new file mode 100644
index 0000000000..de25743c59
--- /dev/null
+++ b/c/src/lib/libbsp/sparc64/niagara/README
@@ -0,0 +1,69 @@
+#
+#  $Id$
+#
+
+BSP NAME:           niagara
+BOARD:              
+BUS:                n/a
+CPU FAMILY:         SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v)
+CPU:                UltraSPARC T1 (OpenSPARC T1)
+COPROCESSORS:       
+MODE:               n/a
+
+DEBUG MONITOR:      
+
+PERIPHERALS
+===========
+TIMERS:             TICK and STICK registers (ASRs 4 and 24)
+  RESOLUTION:         CPU clock resolution
+SERIAL PORTS:       
+REAL-TIME CLOCK:    
+DMA:                none
+VIDEO:              none
+SCSI:               none
+NETWORKING:         none
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER:       
+IOSUPP DRIVER:      
+SHMSUPP:            
+TIMER DRIVER:       
+TTY DRIVER:         
+
+STDIO
+=====
+PORT:               
+ELECTRICAL:         
+BAUD:               
+BITS PER CHARACTER: 
+PARITY:             
+STOP BITS:          
+
+NOTES
+=====
+
+Board description
+-----------------
+clock rate:     
+bus width:      
+ROM:            
+RAM:            
+
+This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64 
+and similar processors.
+
+This BSP has been run on the Simics simulator with the niagara target, which 
+simulates the OpenSPARC T1 Niagara implementation.
+
+This BSP has been run on the M5 simulator with the SPARC_FS target, which
+simulates the OpenSPARC T1 Niagara implementation.
+
+Simics:
+A commercially available simulator licensed by Virtutech.
+https://www.simics.net/
+
+M5:
+An open-source simulator.
+http://www.m5sim.org/wiki/index.php/Main_Page
+