diff options
| author | Daniel Hellstrom <daniel@gaisler.com> | 2013-03-18 08:29:39 +0100 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2015-04-17 01:10:19 +0200 |
| commit | 819de55b6f2fa318357a33fe14a7e0aa1d3083fd (patch) | |
| tree | cbab583f2f8bb1f50dd442d1dfa6ceb693ca2379 /c/src/lib/libbsp/sparc/shared | |
| parent | GRETH: cleaned up parts of PHY init code (diff) | |
| download | rtems-819de55b6f2fa318357a33fe14a7e0aa1d3083fd.tar.bz2 | |
PCI-RASTA: set GRPCI1 target cache-line-size to avoid poor performance
Diffstat (limited to 'c/src/lib/libbsp/sparc/shared')
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c | 6 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c | 6 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c | 6 |
3 files changed, 18 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c index 21ca52cd13..3ee6293728 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c @@ -243,6 +243,12 @@ int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv) pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data); pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY)); + /* Setup cache line size. Default cache line size will result in + * poor performance (256 word fetches), 0xff will set it according + * to the max size of the PCI FIFO. + */ + pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); + /* Scan AMBA Plug&Play */ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c index f96676de78..dca0aa0161 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c @@ -260,6 +260,12 @@ int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv) } #endif + /* Setup cache line size. Default cache line size will result in + * poor performance (256 word fetches), 0xff will set it according + * to the max size of the PCI FIFO. + */ + pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); + /* Scan AMBA Plug&Play */ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c index 7a100836ae..823cd9e0ab 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c @@ -250,6 +250,12 @@ int gr_rasta_tmtc_hw_init(struct gr_rasta_tmtc_priv *priv) } #endif + /* Setup cache line size. Default cache line size will result in + * poor performance (256 word fetches), 0xff will set it according + * to the max size of the PCI FIFO. + */ + pci_cfg_w8(pcidev, PCI_CACHE_LINE_SIZE, 0xff); + /* Scan AMBA Plug&Play */ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |