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authorDaniel Cederman <cederman@gaisler.com>2015-11-16 14:13:28 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2015-11-17 08:59:23 +0100
commit2d7aad73ea79fdfd80fa466233c7dbeceb98d43c (patch)
tree7042acee89b43ad0d2d9f92c61a9abb6e1422ee0 /c/src/lib/libbsp/sparc/shared
parent72857659c1f8fc71da4a30833caab583a2cfac6d (diff)
downloadrtems-2d7aad73ea79fdfd80fa466233c7dbeceb98d43c.tar.bz2
sparc: Fix context switch on SMP
We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first write to PSR to be before the write to WIM, as there is now no risk that we get an interrupt where the CWP and WIM would be inconsistent. We only need to make sure that we do not use any of the non-global registers or instructions that affects CWP for three instructions after the write. In the earlier code the non-global %o1 register was used right after the write to PSR, which required the use of three nop:s. Close #2472.
Diffstat (limited to 'c/src/lib/libbsp/sparc/shared')
-rw-r--r--c/src/lib/libbsp/sparc/shared/irq_asm.S31
1 files changed, 14 insertions, 17 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index f7222e7623..6074130e82 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -127,14 +127,9 @@ SYM(_CPU_Context_restore_heir):
* g5 = scratch
*/
- ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr
-
and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
- ! g1 = psr w/o cwp
- andn %g1, SPARC_PSR_ET_MASK | SPARC_PSR_CWP_MASK, %g1
- or %g1, %g3, %g1 ! g1 = heirs psr
- mov %g1, %psr ! restore status register and
- ! **** DISABLE TRAPS ****
+ andn %o2, SPARC_PSR_ET_MASK, %g1 ! g1 = psr with traps disabled
+ mov %g1, %psr ! **** DISABLE TRAPS ****
mov %wim, %g2 ! g2 = wim
mov 1, %g4
sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
@@ -173,19 +168,15 @@ save_frame_loop:
done_flushing:
- add %g3, 1, %g3 ! calculate desired WIM
- and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
+ ! Wait three instructions after the write to PSR before using
+ ! non-global registers or instructions affecting the CWP
+ mov %g1, %psr ! restore cwp
+ add %g3, 1, %g2 ! calculate desired WIM
+ and %g2, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g2
mov 1, %g4
- sll %g4, %g3, %g4 ! g4 = new WIM
+ sll %g4, %g2, %g4 ! g4 = new WIM
mov %g4, %wim
- or %g1, SPARC_PSR_ET_MASK, %g1
- mov %g1, %psr ! **** ENABLE TRAPS ****
- ! and restore CWP
- nop
- nop
- nop
-
#if defined(RTEMS_SMP)
! The executing context no longer executes on this processor
st %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
@@ -202,6 +193,12 @@ try_update_is_executing:
! The next load is in a delay slot, which is all right
#endif
+ ld [%o1 + PSR_OFFSET], %g1 ! g1 = heir psr with traps enabled
+ andn %g1, SPARC_PSR_CWP_MASK, %g1 ! g1 = heir psr w/o cwp
+ or %g1, %g3, %g1 ! g1 = heir psr with cwp
+ mov %g1, %psr ! restore status register and
+ ! **** ENABLE TRAPS ****
+
ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
ld [%o1 + G7_OFFSET], %g7