LEON: updated and added PCI peripherals for LEON BSPs

The CCHIP driver is replaced with the GR_701 driver. The
RASTA driver is replaced by the GR-RASTA-IO driver.

All drivers are now compatible with both LEON2 and LEON3,
drivers were initialized directly by the PCI-board drivers
are now initialized by the driver manager and therefore
does not require the double code created by including for
example grcan.c into grcan_rasta.c. The other drivers needs
to be updated to the driver manager framework however.

Added support for:
 * GR-701 (only LEON2 before)
 * GR-RASTA-IO (only LEON2 before)
 * GR-RASTA-ADCDAC
 * GR-RASTA-TMTC
 * GR-RASTA-SPW-ROUTER
 * GR-TMTC-1553

6 files changed, 3861 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_701.c b/c/src/lib/libbsp/sparc/shared/pci/gr_701.c
new file mode 100644
index 0000000000..14830085ec
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_701.c
@@ -0,0 +1,592 @@
+/*  GR-701 PCI Target driver.
+ * 
+ *  COPYRIGHT (c) 2008.
+ *  Cobham Gaisler AB.
+ *
+ *  Configures the GR-701 interface PCI board.
+ *  This driver provides a AMBA PnP bus by using the general part
+ *  of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ *  Driver resources for the AMBA PnP bus provided can be set using
+ *  gr701_set_resources().
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+#include <pci/access.h>
+
+#include <ambapp.h>
+
+#include <ambapp.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_701.h>
+
+/* Offset from 0x80000000 (dual bus version) */
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80100000
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) 
+#endif
+
+int gr701_init1(struct drvmgr_dev *dev);
+int gr701_init2(struct drvmgr_dev *dev);
+
+#define READ_REG(address) (*(volatile unsigned int *)address)
+
+/* PCI bride reg layout on AMBA side */
+struct amba_bridge_regs {
+	volatile unsigned int bar0;
+	volatile unsigned int bar1;
+	volatile unsigned int bar2;
+	volatile unsigned int bar3;
+	volatile unsigned int bar4;/* 0x10 */
+	
+	volatile unsigned int unused[4*3-1];
+	
+	volatile unsigned int ambabars[1]; /* 0x40 */
+};
+
+/* PCI bride reg layout on PCI side */
+struct pci_bridge_regs {
+	volatile unsigned int bar0;
+	volatile unsigned int bar1;
+	volatile unsigned int bar2;
+	volatile unsigned int bar3;
+	volatile unsigned int bar4; /* 0x10 */
+
+	volatile unsigned int ilevel;
+	volatile unsigned int ipend;
+	volatile unsigned int iforce;
+	volatile unsigned int istatus;
+	volatile unsigned int iclear;
+	volatile unsigned int imask;
+};
+
+/* Private data structure for driver */
+struct gr701_priv {
+	/* Driver management */
+	struct drvmgr_dev	*dev;
+	char				prefix[16];
+
+	struct pci_bridge_regs		*pcib;
+	struct amba_bridge_regs		*ambab;
+
+	/* PCI */
+	pci_dev_t			pcidev;
+	struct pci_dev_info		*devinfo;	
+
+	/* IRQ */
+	genirq_t			genirq;
+	int				interrupt_cnt;
+
+	/* GR-701 Address translation */
+	struct drvmgr_map_entry		bus_maps_up[2];
+	struct drvmgr_map_entry		bus_maps_down[2];
+
+	/* AMBA Plug&Play information on GR-701 */
+	struct ambapp_bus		abus;
+	struct ambapp_mmap		amba_maps[3];
+        struct ambapp_config		config;
+};
+
+int ambapp_gr701_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_gr701_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg);
+int ambapp_gr701_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_gr701_int_mask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_gr701_int_clear(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_gr701_get_params(
+	struct drvmgr_dev *dev,
+	struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_gr701_ops = {
+	.int_register = ambapp_gr701_int_register,
+	.int_unregister = ambapp_gr701_int_unregister,
+	.int_unmask = ambapp_gr701_int_unmask,
+	.int_mask = ambapp_gr701_int_mask,
+	.int_clear = ambapp_gr701_int_clear,
+	.get_params = ambapp_gr701_get_params
+};
+
+struct drvmgr_drv_ops gr701_ops = 
+{
+	.init = {gr701_init1, gr701_init2, NULL, NULL},
+	.remove = NULL,
+	.info = NULL
+};
+
+struct pci_dev_id_match gr701_ids[] = 
+{
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701),
+	PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr701_info =
+{
+	{
+		DRVMGR_OBJ_DRV,			/* Driver */
+		NULL,				/* Next driver */
+		NULL,				/* Device list */
+		DRIVER_PCI_GAISLER_GR701_ID,	/* Driver ID */
+		"GR-701_DRV",			/* Driver Name */
+		DRVMGR_BUS_TYPE_PCI,		/* Bus Type */
+		&gr701_ops,
+		NULL,				/* Funcs */
+		0,				/* No devices yet */
+		0,
+	},
+	&gr701_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-701 board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-701 board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr701_resources[] __attribute__((weak)) =
+{
+	NULL
+};
+int gr701_resources_cnt = 0;
+
+void gr701_register_drv(void)
+{
+	DBG("Registering GR-701 PCI driver\n");
+	drvmgr_drv_register(&gr701_info.general);
+}
+
+void gr701_interrupt(void *arg)
+{
+	struct gr701_priv *priv = arg;
+	unsigned int status;
+	int irq = 0;
+
+	while ( (status=priv->pcib->istatus) != 0 ) {
+		priv->interrupt_cnt++;	/* An interrupt was generated */
+		irq = status;
+		genirq_doirq(priv->genirq, irq);
+		/* ACK interrupt */
+		priv->pcib->istatus = 0;
+	}
+
+	/* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+	if ( irq )
+		drvmgr_interrupt_clear(priv->dev, 0);
+}
+
+int gr701_hw_init(struct gr701_priv *priv)
+{
+	uint32_t com1;
+	struct pci_bridge_regs *pcib;
+	struct amba_bridge_regs *ambab;
+	int mst;
+	unsigned int pci_freq_hz;
+	pci_dev_t pcidev = priv->pcidev;
+	struct pci_dev_info *devinfo = priv->devinfo;
+
+	/* Set up PCI ==> AMBA */
+	priv->pcib = pcib = (void *)devinfo->resources[0].address;
+	pcib->bar0 = 0xfc000000;
+
+	/* Set up GR701 AMBA Masters connection to PCI */
+	priv->ambab = ambab = (struct amba_bridge_regs *)(
+		devinfo->resources[1].address + 0x400);
+
+	/* Init all msters, max 16 */
+	for (mst=0; mst<16; mst++) {
+		ambab->ambabars[mst] = 0x40000000;
+		if (READ_REG(&ambab->ambabars[mst]) != 0x40000000)
+			break;
+	}
+
+	/* Setup Address translation for AMBA bus, assume that PCI BAR
+	 * are mapped 1:1 to CPU.
+	 */
+
+	priv->amba_maps[0].size = 0x04000000;
+	priv->amba_maps[0].local_adr = devinfo->resources[1].address;
+	priv->amba_maps[0].remote_adr = 0xfc000000;
+
+	/* Mark end of table */
+	priv->amba_maps[1].size=0;
+	priv->amba_maps[1].local_adr = 0;
+	priv->amba_maps[1].remote_adr = 0;
+
+	/* Setup DOWN-streams address translation */
+	priv->bus_maps_down[0].name = "PCI BAR1 -> AMBA";
+	priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+	priv->bus_maps_down[0].from_adr = (void *)devinfo->resources[1].address;
+	priv->bus_maps_down[0].to_adr = (void *)0xfc000000;
+
+	/* Setup UP-streams address translation */
+	priv->bus_maps_up[0].name = "AMBA PCIF Window";
+	priv->bus_maps_up[0].size = 0x10000000;
+	priv->bus_maps_up[0].from_adr = (void *)0xe0000000;
+	priv->bus_maps_up[0].to_adr = (void *)0x40000000;
+
+	/* Mark end of translation tables */
+	priv->bus_maps_down[1].size = 0;
+	priv->bus_maps_up[1].size = 0;
+
+	/* Enable I/O and Mem accesses */
+	pci_cfg_r32(pcidev, PCI_COMMAND, &com1);
+	com1 |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+	pci_cfg_w32(pcidev, PCI_COMMAND, com1);
+
+	/* Start AMBA PnP scan at first AHB bus */
+	ambapp_scan(&priv->abus, devinfo->resources[1].address + 0x3f00000,
+			NULL, &priv->amba_maps[0]);
+
+	/* Frequency is the same as the PCI bus frequency */
+	drvmgr_freq_get(priv->dev, NULL, &pci_freq_hz);
+
+	/* Initialize Frequency of AMBA bus */
+	ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
+
+	/* Init IRQ controller (avoid IRQ generation) */
+	pcib->imask = 0x0000;
+	pcib->ipend = 0;
+	pcib->iclear = 0xffff;
+	pcib->iforce = 0;
+	pcib->ilevel = 0x0;
+
+	/* Successfully registered the GR-701 board */
+	return 0;
+}
+
+void gr701_hw_init2(struct gr701_priv *priv)
+{
+	/* Enable PCI Master (for DMA) */
+	pci_master_enable(priv->pcidev);
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr701_ids[].
+ */
+int gr701_init1(struct drvmgr_dev *dev)
+{
+	struct gr701_priv *priv;
+	struct pci_dev_info *devinfo;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+
+	priv = malloc(sizeof(struct gr701_priv));
+	if ( !priv )
+		return DRVMGR_NOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+	dev->priv = priv;
+	priv->dev = dev;
+
+	/* Determine number of configurations */
+	if ( gr701_resources_cnt == 0 ) {
+		while ( gr701_resources[gr701_resources_cnt] )
+			gr701_resources_cnt++;
+	}
+
+	/* Generate Device prefix */
+
+	strcpy(priv->prefix, "/dev/gr701_0");
+	priv->prefix[11] += dev->minor_drv;
+	mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+	priv->prefix[12] = '/';
+	priv->prefix[13] = '\0';
+
+	priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+	priv->pcidev = devinfo->pcidev;
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+	printf("\n\n--- GR-701[%d] ---\n", dev->minor_drv);
+	printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n\n\n",
+		devinfo->id.vendor, devinfo->id.device);
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+	/* all neccessary space assigned to GR-701 target? */
+	if ((bar0_size == 0) || (bar1_size == 0))
+		return DRVMGR_ENORES;
+
+	priv->genirq = genirq_init(16);
+	if ( priv->genirq == NULL ) {
+		free(priv);
+		dev->priv = NULL;
+		return DRVMGR_FAIL;
+	}
+
+	if ( gr701_hw_init(priv) ) {
+		genirq_destroy(priv->genirq);
+		free(priv);
+		dev->priv = NULL;
+		printf(" Failed to initialize GR-701 HW\n");
+		return DRVMGR_FAIL;
+	}
+
+	/* Init amba bus */
+	priv->config.abus = &priv->abus;
+	priv->config.ops = &ambapp_gr701_ops;
+	priv->config.maps_up = &priv->bus_maps_up[0];
+	priv->config.maps_down = &priv->bus_maps_down[0];
+	if ( priv->dev->minor_drv < gr701_resources_cnt ) {
+		priv->config.resources = gr701_resources[priv->dev->minor_drv];
+	} else {
+		priv->config.resources = NULL;
+	}
+
+	/* Create and register AMBA PnP bus. */
+	return ambapp_bus_register(dev, &priv->config);
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr701_ids[].
+ */
+int gr701_init2(struct drvmgr_dev *dev)
+{
+	struct gr701_priv *priv = dev->priv;
+
+	/* Clear any old interrupt requests */
+	drvmgr_interrupt_clear(dev, 0);
+
+	/* Enable System IRQ so that GR-701 PCI target interrupt goes through.
+	 *
+	 * It is important to enable it in stage init2. If interrupts were
+	 * enabled in init1 this might hang the system when more than one PCI
+	 * board is connected, this is because PCI interrupts might be shared
+	 * and PCI target 2 have not initialized and might therefore drive
+	 * interrupt already when entering init1().
+	 */
+	drvmgr_interrupt_register(dev, 0, "gr701", gr701_interrupt, priv);
+
+	gr701_hw_init2(priv);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_gr701_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg)
+{
+	struct gr701_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_register(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Clear IRQ for first registered handler */
+		priv->pcib->iclear = (1<<irq);
+	} else if ( status == 1 )
+		status = 0;
+
+	if (status != 0) {
+		rtems_interrupt_enable(level);
+		return DRVMGR_FAIL;
+	}
+
+	status = genirq_enable(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Enable IRQ for first enabled handler only */
+		priv->pcib->imask |= (1<<irq); /* unmask interrupt source */
+	} else if ( status == 1 )
+		status = DRVMGR_OK;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_gr701_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg)
+{
+	struct gr701_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_disable(priv->genirq, irq, isr, arg);
+	if ( status == 0 ) {
+		/* Disable IRQ only when no enabled handler exists */
+		priv->pcib->imask &= ~(1<<irq); /* mask interrupt source */
+	}
+
+	status = genirq_unregister(priv->genirq, irq, isr, arg);
+	if ( status != 0 )
+		status = DRVMGR_FAIL;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_gr701_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr701_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("GR-701 IRQ %d: enable\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	rtems_interrupt_disable(level);
+
+	/* Enable IRQ */
+	priv->pcib->imask |= (1<<irq); /* unmask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_gr701_int_mask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr701_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("GR-701 IRQ %d: disable\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	rtems_interrupt_disable(level);
+
+	/* Disable IRQ */
+	priv->pcib->imask &= ~(1<<irq); /* mask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_gr701_int_clear(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr701_priv *priv = dev->parent->dev->priv;
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	priv->pcib->iclear = (1<<irq);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_gr701_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+	struct gr701_priv *priv = dev->parent->dev->priv;
+
+	/* Device name prefix pointer, skip /dev */
+	params->dev_prefix = &priv->prefix[5];
+
+	return 0;
+}
+
+void gr701_print_dev(struct drvmgr_dev *dev, int options)
+{
+	struct gr701_priv *priv = dev->priv;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	unsigned int freq_hz;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+
+	/* Print */
+	printf("--- GR-701 [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ:             %d\n", devinfo->irq);
+
+	/* Frequency is the same as the PCI bus frequency */
+	drvmgr_freq_get(dev, 0, &freq_hz);
+
+	printf(" FREQ:            %u Hz\n", freq_hz);
+	printf(" IMASK:           0x%08x\n", priv->pcib->imask);
+	printf(" IPEND:           0x%08x\n", priv->pcib->ipend);
+
+	/* Print amba config */
+	if ( options & GR701_OPTIONS_AMBA ) {
+		ambapp_print(&priv->abus, 10);
+	}
+
+#if 0
+	/* Print IRQ handlers and their arguments */
+	if ( options & GR701_OPTIONS_IRQ ) {
+		int i;
+		for(i=0; i<16; i++) {
+			printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n", 
+				i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+		}
+	}
+#endif
+}
+
+void gr701_print(int options)
+{
+	struct pci_drv_info *drv = &gr701_info;
+	struct drvmgr_dev *dev;
+
+	dev = drv->general.dev;
+	while(dev) {
+		gr701_print_dev(dev, options);
+		dev = dev->next_in_drv;
+	}
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
new file mode 100644
index 0000000000..21ca52cd13
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
@@ -0,0 +1,661 @@
+/*  GR-RASTA-ADCDAC PCI Target driver.
+ * 
+ *  COPYRIGHT (c) 2008.
+ *  Cobham Gaisler AB.
+ *
+ *  Configures the GR-RASTA-ADCDAC interface PCI board.
+ *  This driver provides a AMBA PnP bus by using the general part
+ *  of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ *  Driver resources for the AMBA PnP bus provided can be set using
+ *  gr_rasta_adcdac_set_resources().
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_rasta_adcdac.h>
+
+/*#define DEBUG 1*/
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) 
+#endif
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER		0x1AC8
+#define PCIID_DEVICE_GR_RASTA_ADCDAC	0x0014
+
+int gr_rasta_adcdac_init1(struct drvmgr_dev *dev);
+int gr_rasta_adcdac_init2(struct drvmgr_dev *dev);
+
+struct grpci_regs {
+	volatile unsigned int cfg_stat;
+	volatile unsigned int bar0;
+	volatile unsigned int page0;
+	volatile unsigned int bar1;
+	volatile unsigned int page1;
+	volatile unsigned int iomap;
+	volatile unsigned int stat_cmd;
+};
+
+struct gr_rasta_adcdac_ver {
+	const unsigned int	amba_freq_hz;	/* The frequency */
+	const unsigned int	amba_ioarea;	/* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_adcdac_priv {
+	/* Driver management */
+	struct drvmgr_dev	*dev;
+	char				prefix[20];
+
+	/* PCI */
+	pci_dev_t			pcidev;
+	struct pci_dev_info		*devinfo;
+	uint32_t			ahbmst2pci_map;
+
+	/* IRQ */
+	genirq_t			genirq;
+
+	/* GR-RASTA-ADCDAC */
+	struct gr_rasta_adcdac_ver	*version;
+	struct irqmp_regs		*irq;
+	struct grpci_regs		*grpci;
+	struct drvmgr_map_entry		bus_maps_down[3];
+	struct drvmgr_map_entry		bus_maps_up[2];
+
+	/* AMBA Plug&Play information on GR-RASTA-ADCDAC */
+	struct ambapp_bus		abus;
+	struct ambapp_mmap		amba_maps[4];
+        struct ambapp_config		config;
+};
+
+struct gr_rasta_adcdac_ver gr_rasta_adcdac_ver0 = {
+	.amba_freq_hz		= 50000000,
+	.amba_ioarea		= 0x80100000,
+};
+
+int ambapp_rasta_adcdac_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_adcdac_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg);
+int ambapp_rasta_adcdac_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_adcdac_int_mask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_adcdac_int_clear(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_adcdac_get_params(
+	struct drvmgr_dev *dev,
+	struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_adcdac_ops = {
+	.int_register = ambapp_rasta_adcdac_int_register,
+	.int_unregister = ambapp_rasta_adcdac_int_unregister,
+	.int_unmask = ambapp_rasta_adcdac_int_unmask,
+	.int_mask = ambapp_rasta_adcdac_int_mask,
+	.int_clear = ambapp_rasta_adcdac_int_clear,
+	.get_params = ambapp_rasta_adcdac_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_adcdac_ops = 
+{	.init = {gr_rasta_adcdac_init1, gr_rasta_adcdac_init2, NULL, NULL},
+	.remove = NULL,
+	.info = NULL
+};
+
+struct pci_dev_id_match gr_rasta_adcdac_ids[] = 
+{
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC),
+	PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_adcdac_info =
+{
+	{
+		DRVMGR_OBJ_DRV,			/* Driver */
+		NULL,				/* Next driver */
+		NULL,				/* Device list */
+		DRIVER_PCI_GAISLER_RASTAADCDAC_ID,/* Driver ID */
+		"GR-RASTA-ADCDAC_DRV",		/* Driver Name */
+		DRVMGR_BUS_TYPE_PCI,		/* Bus Type */
+		&gr_rasta_adcdac_ops,
+		NULL,				/* Funcs */
+		0,				/* No devices yet */
+		0,
+	},
+	&gr_rasta_adcdac_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-ADCDAC board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-ADCDAC board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_adcdac_resources[] __attribute__((weak)) =
+{
+	NULL
+};
+int gr_rasta_adcdac_resources_cnt = 0;
+
+void gr_rasta_adcdac_register_drv(void)
+{
+	DBG("Registering GR-RASTA-ADCDAC PCI driver\n");
+	drvmgr_drv_register(&gr_rasta_adcdac_info.general);
+}
+
+void gr_rasta_adcdac_isr (void *arg)
+{
+	struct gr_rasta_adcdac_priv *priv = arg;
+	unsigned int status, tmp;
+	int irq;
+	tmp = status = priv->irq->ipend;
+
+	/* DBG("GR-RASTA-ADCDAC: IRQ 0x%x\n",status); */
+
+	for(irq=0; irq<16; irq++) {
+		if ( status & (1<<irq) ) {
+			genirq_doirq(priv->genirq, irq);
+			priv->irq->iclear = (1<<irq);
+			status &= ~(1<<irq);
+			if ( status == 0 )
+				break;
+		}
+	}
+
+	/* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+	if ( tmp )
+		drvmgr_interrupt_clear(priv->dev, 0);
+
+	DBG("RASTA-ADCDAC-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv)
+{
+	uint32_t data;
+	unsigned int *page0 = NULL;
+	struct ambapp_dev *tmp;
+	int status;
+	struct ambapp_ahb_info *ahb;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar0_size;
+
+	/* Select version of GR-RASTA-ADCDAC board */
+	switch (devinfo->rev) {
+		case 0:
+			priv->version = &gr_rasta_adcdac_ver0;
+			break;
+		default:
+			return -2;
+	}
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	page0 = (unsigned int *)(bar0 + bar0_size/2); 
+
+	/* Point PAGE0 to start of Plug and Play information */
+	*page0 = priv->version->amba_ioarea & 0xf0000000;
+
+	/* set parity error response */
+	pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
+	pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+
+	/* Scan AMBA Plug&Play */
+
+	/* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+	priv->amba_maps[0].size = bar0_size/2;
+	priv->amba_maps[0].local_adr = bar0;
+	priv->amba_maps[0].remote_adr = 0x80000000;
+
+	/* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
+	priv->amba_maps[1].size = devinfo->resources[1].size;
+	priv->amba_maps[1].local_adr = devinfo->resources[1].address;
+	priv->amba_maps[1].remote_adr = 0x40000000;
+
+	/* Addresses not matching with map be untouched */
+	priv->amba_maps[2].size = 0xfffffff0;
+	priv->amba_maps[2].local_adr = 0;
+	priv->amba_maps[2].remote_adr = 0;
+
+	/* Mark end of table */
+	priv->amba_maps[3].size=0;
+	priv->amba_maps[3].local_adr = 0;
+	priv->amba_maps[3].remote_adr = 0;
+
+	/* Start AMBA PnP scan at first AHB bus */
+	/*ambapp_scan(priv->bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+		NULL, &priv->amba_maps[0], NULL, &priv->abus.root, NULL);*/
+	ambapp_scan(&priv->abus,
+		bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+		NULL, &priv->amba_maps[0]);
+
+	/* Initialize Frequency of AMBA bus */
+	ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
+
+	/* Point PAGE0 to start of APB area */
+	*page0 = 0x80000000;	
+
+	/* Find GRPCI controller */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_PCIFBRG,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -3;
+	}
+	priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+	/* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
+	 * the PCI window.
+	 */
+	priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
+				(priv->ahbmst2pci_map & 0xf0000000);
+	priv->grpci->page1 = 0x40000000;
+
+	/* Find IRQ controller */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_IRQMP,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -4;
+	}
+	priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+	/* Set up GR-RASTA-ADCDAC irq controller */
+	priv->irq->iclear = 0xffff;
+	priv->irq->ilevel = 0;
+	priv->irq->mask[0] = 0;
+
+	/* DOWN streams translation table */
+	priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+	priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+	priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+	priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+
+	priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
+	priv->bus_maps_down[1].size = priv->amba_maps[1].size;
+	priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
+	priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
+
+	/* Mark end of translation table */
+	priv->bus_maps_down[2].size = 0;
+
+	/* Find GRPCI controller AHB Slave interface */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_AHB_SLVS),
+					VENDOR_GAISLER, GAISLER_PCIFBRG,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -5;
+	}
+	ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+
+	/* UP streams translation table */
+	priv->bus_maps_up[0].name = "AMBA GRPCI Window";
+	priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-ADCDAC board */
+	priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+	priv->bus_maps_up[0].to_adr = (void *)
+					(priv->ahbmst2pci_map & 0xf0000000);
+
+	/* Mark end of translation table */
+	priv->bus_maps_up[1].size = 0;
+
+	/* Successfully registered the RASTA board */
+	return 0;
+}
+
+int gr_rasta_adcdac_hw_init2(struct gr_rasta_adcdac_priv *priv)
+{
+	/* Enable DMA by enabling PCI target as master */
+	pci_master_enable(priv->pcidev);
+
+	return DRVMGR_OK;
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr_rasta_adcdac_ids[].
+ */
+int gr_rasta_adcdac_init1(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_adcdac_priv *priv;
+	struct pci_dev_info *devinfo;
+	int status;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+	union drvmgr_key_value *value;
+
+	priv = malloc(sizeof(struct gr_rasta_adcdac_priv));
+	if ( !priv )
+		return DRVMGR_NOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+	dev->priv = priv;
+	priv->dev = dev;
+
+	/* Determine number of configurations */
+	if ( gr_rasta_adcdac_resources_cnt == 0 ) {
+		while ( gr_rasta_adcdac_resources[gr_rasta_adcdac_resources_cnt] )
+			gr_rasta_adcdac_resources_cnt++;
+	}
+
+	/* Generate Device prefix */
+
+	strcpy(priv->prefix, "/dev/rastaadcdac0");
+	priv->prefix[16] += dev->minor_drv;
+	mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+	priv->prefix[17] = '/';
+	priv->prefix[18] = '\0';
+
+	priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+	priv->pcidev = devinfo->pcidev;
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+	printf("\n\n--- GR-RASTA-ADCDAC[%d] ---\n", dev->minor_drv);
+	printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+		devinfo->id.vendor, devinfo->id.device);
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+	/* all neccessary space assigned to GR-RASTA-ADCDAC target? */
+	if ((bar0_size == 0) || (bar1_size == 0))
+		return DRVMGR_ENORES;
+
+	/* Let user override which PCI address the AHB masters of the
+	 * RASTA-ADCDAC board access when doing DMA to CPU RAM. The AHB masters
+	 * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+	 * is translated according this config option before the address
+	 * goes out on the PCI bus.
+	 * Only the 4 MSB bits have an effect;
+	 */
+	value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+	if (value)
+		priv->ahbmst2pci_map = value->i;
+	else
+		priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */
+
+	priv->genirq = genirq_init(16);
+	if ( priv->genirq == NULL ) {
+		free(priv);
+		dev->priv = NULL;
+		return DRVMGR_FAIL;
+	}
+
+	if ( (status = gr_rasta_adcdac_hw_init1(priv)) != 0 ) {
+		genirq_destroy(priv->genirq);
+		free(priv);
+		dev->priv = NULL;
+		printf(" Failed to initialize GR-RASTA-ADCDAC HW: %d\n", status);
+		return DRVMGR_FAIL;
+	}
+
+	/* Init amba bus */
+	priv->config.abus = &priv->abus;
+	priv->config.ops = &ambapp_rasta_adcdac_ops;
+	priv->config.maps_up = &priv->bus_maps_up[0];
+	priv->config.maps_down = &priv->bus_maps_down[0];
+	if ( priv->dev->minor_drv < gr_rasta_adcdac_resources_cnt ) {
+		priv->config.resources = gr_rasta_adcdac_resources[priv->dev->minor_drv];
+	} else {
+		priv->config.resources = NULL;
+	}
+
+	/* Create and register AMBA PnP bus. */
+	return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_adcdac_init2(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->priv;
+
+	/* Clear any old interrupt requests */
+	drvmgr_interrupt_clear(dev, 0);
+
+	/* Enable System IRQ so that GR-RASTA-ADCDAC PCI target interrupt 
+	 * goes through.
+	 *
+	 * It is important to enable it in stage init2. If interrupts were
+	 * enabled in init1 this might hang the system when more than one 
+	 * PCI board is connected, this is because PCI interrupts might 
+	 * be shared and PCI board 2 have not initialized and might
+	 * therefore drive interrupt already when entering init1().
+	 */
+	drvmgr_interrupt_register(
+		dev,
+		0,
+		"gr_rasta_adcdac",
+		gr_rasta_adcdac_isr, 
+		(void *)priv);
+
+	return gr_rasta_adcdac_hw_init2(priv);
+}
+
+int ambapp_rasta_adcdac_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_register(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Clear IRQ for first registered handler */
+		priv->irq->iclear = (1<<irq);
+	} else if ( status == 1 )
+		status = 0;
+
+	if (status != 0) {
+		rtems_interrupt_enable(level);
+		return DRVMGR_FAIL;
+	}
+
+	status = genirq_enable(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Enable IRQ for first enabled handler only */
+		priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_adcdac_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_disable(priv->genirq, irq, isr, arg);
+	if ( status == 0 ) {
+		/* Disable IRQ only when no enabled handler exists */
+		priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+	}
+
+	status = genirq_unregister(priv->genirq, irq, isr, arg);
+	if ( status != 0 )
+		status = DRVMGR_FAIL;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_adcdac_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-ADCDAC IRQ %d: unmask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Enable IRQ for first enabled handler only */
+	priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_adcdac_int_mask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-ADCDAC IRQ %d: mask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Disable/mask IRQ */
+	priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_adcdac_int_clear(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	priv->irq->iclear = (1<<irq);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_adcdac_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+
+	/* Device name prefix pointer, skip /dev */
+	params->dev_prefix = &priv->prefix[5];
+
+	return 0;
+}
+
+void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options)
+{
+	struct gr_rasta_adcdac_priv *priv = dev->priv;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+
+	/* Print */
+	printf("--- GR-RASTA-ADCDAC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ REGS:        0x%x\n", (unsigned int)priv->irq);
+	printf(" IRQ:             %d\n", devinfo->irq);
+	printf(" PCI REVISION:    %d\n", devinfo->rev);
+	printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
+	printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
+	printf(" IPEND:           0x%08x\n", priv->irq->ipend);
+
+	/* Print amba config */
+	if ( options & RASTA_ADCDAC_OPTIONS_AMBA ) {
+		ambapp_print(&priv->abus, 10);
+	}
+#if 0
+	/* Print IRQ handlers and their arguments */
+	if ( options & RASTA_ADCDAC_OPTIONS_IRQ ) {
+		int i;
+		for(i=0; i<16; i++) {
+			printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n", 
+				i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+		}
+	}
+#endif
+}
+
+void gr_rasta_adcdac_print(int options)
+{
+	struct pci_drv_info *drv = &gr_rasta_adcdac_info;
+	struct drvmgr_dev *dev;
+
+	dev = drv->general.dev;
+	while(dev) {
+		gr_rasta_adcdac_print_dev(dev, options);
+		dev = dev->next_in_drv;
+	}
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c
new file mode 100644
index 0000000000..f96676de78
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c
@@ -0,0 +1,678 @@
+/*  GR-RASTA-IO PCI Target driver.
+ * 
+ *  COPYRIGHT (c) 2008.
+ *  Cobham Gaisler AB.
+ *
+ *  Configures the GR-RASTA-IO interface PCI board.
+ *  This driver provides a AMBA PnP bus by using the general part
+ *  of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ *  Driver resources for the AMBA PnP bus provided can be set using
+ *  gr_rasta_io_set_resources().
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_rasta_io.h>
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+/* Offset from 0x80000000 (dual bus version) */
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80100000
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) 
+#endif
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER		0x1AC8
+
+int gr_rasta_io_init1(struct drvmgr_dev *dev);
+int gr_rasta_io_init2(struct drvmgr_dev *dev);
+
+struct grpci_regs {
+	volatile unsigned int cfg_stat;
+	volatile unsigned int bar0;
+	volatile unsigned int page0;
+	volatile unsigned int bar1;
+	volatile unsigned int page1;
+	volatile unsigned int iomap;
+	volatile unsigned int stat_cmd;
+};
+
+struct gr_rasta_io_ver {
+	const unsigned int	amba_freq_hz;	/* The frequency */
+	const unsigned int	amba_ioarea;	/* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_io_priv {
+	/* Driver management */
+	struct drvmgr_dev	*dev;
+	char				prefix[16];
+
+	/* PCI */
+	pci_dev_t			pcidev;
+	struct pci_dev_info		*devinfo;
+	uint32_t			ahbmst2pci_map;
+
+	/* IRQ */
+	genirq_t			genirq;
+
+	/* GR-RASTA-IO */
+	struct gr_rasta_io_ver		*version;
+	struct irqmp_regs		*irq;
+	struct grpci_regs		*grpci;
+	struct drvmgr_map_entry		bus_maps_down[3];
+	struct drvmgr_map_entry		bus_maps_up[2];
+
+	/* AMBA Plug&Play information on GR-RASTA-IO */
+	struct ambapp_bus		abus;
+	struct ambapp_mmap		amba_maps[4];
+        struct ambapp_config		config;
+};
+
+struct gr_rasta_io_ver gr_rasta_io_ver0 = {
+	.amba_freq_hz		= 30000000,
+	.amba_ioarea		= 0x80100000,
+};
+
+struct gr_rasta_io_ver gr_rasta_io_ver1 = {
+	.amba_freq_hz		= 50000000,
+	.amba_ioarea		= 0x80100000,
+};
+
+int ambapp_rasta_io_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_io_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_io_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_io_int_mask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_io_int_clear(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_io_get_params(
+	struct drvmgr_dev *dev,
+	struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_io_ops = {
+	.int_register = ambapp_rasta_io_int_register,
+	.int_unregister = ambapp_rasta_io_int_unregister,
+	.int_unmask = ambapp_rasta_io_int_unmask,
+	.int_mask = ambapp_rasta_io_int_mask,
+	.int_clear = ambapp_rasta_io_int_clear,
+	.get_params = ambapp_rasta_io_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_io_ops = 
+{
+	.init = {gr_rasta_io_init1, gr_rasta_io_init2, NULL, NULL},
+	.remove = NULL,
+	.info = NULL
+};
+
+struct pci_dev_id_match gr_rasta_io_ids[] = 
+{
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO),
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER_OLD, PCIID_DEVICE_GR_RASTA_IO_OLD),
+	PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_io_info =
+{
+	{
+		DRVMGR_OBJ_DRV,			/* Driver */
+		NULL,				/* Next driver */
+		NULL,				/* Device list */
+		DRIVER_PCI_GAISLER_RASTAIO_ID,	/* Driver ID */
+		"GR-RASTA-IO_DRV",		/* Driver Name */
+		DRVMGR_BUS_TYPE_PCI,		/* Bus Type */
+		&gr_rasta_io_ops,
+		NULL,				/* Funcs */
+		0,				/* No devices yet */
+		0,
+	},
+	&gr_rasta_io_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-IO board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_io_resources[] __attribute__((weak)) =
+{
+	NULL
+};
+int gr_rasta_io_resources_cnt = 0;
+
+void gr_rasta_io_register_drv(void)
+{
+	DBG("Registering GR-RASTA-IO PCI driver\n");
+	drvmgr_drv_register(&gr_rasta_io_info.general);
+}
+
+void gr_rasta_io_isr (void *arg)
+{
+	struct gr_rasta_io_priv *priv = arg;
+	unsigned int status, tmp;
+	int irq;
+	tmp = status = priv->irq->ipend;
+
+	/* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */
+
+	for(irq=0; irq<16; irq++) {
+		if ( status & (1<<irq) ) {
+			genirq_doirq(priv->genirq, irq);
+			priv->irq->iclear = (1<<irq);
+			status &= ~(1<<irq);
+			if ( status == 0 )
+				break;
+		}
+	}
+
+	/* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+	if ( tmp ) 
+		drvmgr_interrupt_clear(priv->dev, 0);
+
+	DBG("RASTA-IO-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv)
+{
+	unsigned int *page0 = NULL;
+	struct ambapp_dev *tmp;
+	int status;
+	struct ambapp_ahb_info *ahb;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar0_size;
+
+	/* Select version of GR-RASTA-IO board */
+	switch (devinfo->rev) {
+		case 0:
+			priv->version = &gr_rasta_io_ver0;
+			break;
+		case 1:
+			priv->version = &gr_rasta_io_ver1;
+			break;
+		default:
+			return -2;
+	}
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	page0 = (unsigned int *)(bar0 + bar0_size/2); 
+
+	/* Point PAGE0 to start of Plug and Play information */
+	*page0 = priv->version->amba_ioarea & 0xf0000000;
+
+#if 0
+	{
+		uint32_t data;
+		/* set parity error response */
+		pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
+		pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+	}
+#endif
+
+	/* Scan AMBA Plug&Play */
+
+	/* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+	priv->amba_maps[0].size = bar0_size/2;
+	priv->amba_maps[0].local_adr = bar0;
+	priv->amba_maps[0].remote_adr = 0x80000000;
+
+	/* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
+	priv->amba_maps[1].size = devinfo->resources[1].size;
+	priv->amba_maps[1].local_adr = devinfo->resources[1].address;
+	priv->amba_maps[1].remote_adr = 0x40000000;
+
+	/* Addresses not matching with map be untouched */
+	priv->amba_maps[2].size = 0xfffffff0;
+	priv->amba_maps[2].local_adr = 0;
+	priv->amba_maps[2].remote_adr = 0;
+
+	/* Mark end of table */
+	priv->amba_maps[3].size=0;
+	priv->amba_maps[3].local_adr = 0;
+	priv->amba_maps[3].remote_adr = 0;
+
+	/* Start AMBA PnP scan at first AHB bus */
+	ambapp_scan(&priv->abus,
+			bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+			NULL, &priv->amba_maps[0]);
+
+	/* Initialize Frequency of AMBA bus */
+	ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
+
+	/* Point PAGE0 to start of APB area */
+	*page0 = 0x80000000;	
+
+	/* Find GRPCI controller */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_PCIFBRG,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -3;
+	}
+	priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+	/* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
+	 * the PCI window.
+	 */
+	priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
+				(priv->ahbmst2pci_map & 0xf0000000);
+	priv->grpci->page1 = 0x40000000;
+
+	/* Find IRQ controller, Clear all current IRQs */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_IRQMP,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -4;
+	}
+	priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+	/* Set up GR-RASTA-IO irq controller */
+	priv->irq->mask[0] = 0;
+	priv->irq->iclear = 0xffff;
+	priv->irq->ilevel = 0;
+
+	/* DOWN streams translation table */
+	priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+	priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+	priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+	priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+
+	priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
+	priv->bus_maps_down[1].size = priv->amba_maps[1].size;
+	priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
+	priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
+
+	/* Mark end of translation table */
+	priv->bus_maps_down[2].size = 0;
+
+	/* Find GRPCI controller AHB Slave interface */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_AHB_SLVS),
+					VENDOR_GAISLER, GAISLER_PCIFBRG,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -5;
+	}
+	ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+
+	/* UP streams translation table */
+	priv->bus_maps_up[0].name = "AMBA GRPCI Window";
+	priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-IO board */
+	priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+	priv->bus_maps_up[0].to_adr = (void *)
+					(priv->ahbmst2pci_map & 0xf0000000);
+
+	/* Mark end of translation table */
+	priv->bus_maps_up[1].size = 0;
+
+	/* Successfully registered the RASTA board */
+	return 0;
+}
+
+int gr_rasta_io_hw_init2(struct gr_rasta_io_priv *priv)
+{
+	/* Enable DMA by enabling PCI target as master */
+	pci_master_enable(priv->pcidev);
+
+	return DRVMGR_OK;
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr_rasta_io_ids[].
+ */
+int gr_rasta_io_init1(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_io_priv *priv;
+	struct pci_dev_info *devinfo;
+	int status;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+	union drvmgr_key_value *value;
+
+	priv = malloc(sizeof(struct gr_rasta_io_priv));
+	if ( !priv )
+		return DRVMGR_NOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+	dev->priv = priv;
+	priv->dev = dev;
+
+	/* Determine number of configurations */
+	if ( gr_rasta_io_resources_cnt == 0 ) {
+		while ( gr_rasta_io_resources[gr_rasta_io_resources_cnt] )
+			gr_rasta_io_resources_cnt++;
+	}
+
+	/* Generate Device prefix */
+
+	strcpy(priv->prefix, "/dev/rastaio0");
+	priv->prefix[12] += dev->minor_drv;
+	mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+	priv->prefix[13] = '/';
+	priv->prefix[14] = '\0';
+
+	priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+	priv->pcidev = devinfo->pcidev;
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+	printf("\n\n--- GR-RASTA-IO[%d] ---\n", dev->minor_drv);
+	printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+		devinfo->id.vendor, devinfo->id.device);
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+	/* all neccessary space assigned to GR-RASTA-IO target? */
+	if ((bar0_size == 0) || (bar1_size == 0))
+		return DRVMGR_ENORES;
+
+	/* Let user override which PCI address the AHB masters of the
+	 * GR-RASTA-IO board access when doing DMA to CPU RAM. The AHB masters
+	 * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+	 * is translated according this config option before the address
+	 * goes out on the PCI bus.
+	 * Only the 4 MSB bits have an effect;
+	 */
+	value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+	if (value)
+		priv->ahbmst2pci_map = value->i;
+	else
+		priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */	
+
+	priv->genirq = genirq_init(16);
+	if ( priv->genirq == NULL ) {
+		free(priv);
+		dev->priv = NULL;
+		return DRVMGR_FAIL;
+	}
+
+	status = gr_rasta_io_hw_init(priv);
+	if ( status != 0 ) {
+		genirq_destroy(priv->genirq);
+		free(priv);
+		dev->priv = NULL;
+		printf(" Failed to initialize GR-RASTA-IO HW: %d\n", status);
+		return DRVMGR_FAIL;
+	}
+
+	/* Init amba bus */
+	priv->config.abus = &priv->abus;
+	priv->config.ops = &ambapp_rasta_io_ops;
+	priv->config.maps_up = &priv->bus_maps_up[0];
+	priv->config.maps_down = &priv->bus_maps_down[0];
+	if ( priv->dev->minor_drv < gr_rasta_io_resources_cnt ) {
+		priv->config.resources = gr_rasta_io_resources[priv->dev->minor_drv];
+	} else {
+		priv->config.resources = NULL;
+	}
+
+	/* Create and register AMBA PnP bus. */
+	return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_io_init2(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_io_priv *priv = dev->priv;
+
+	/* Clear any old interrupt requests */
+	drvmgr_interrupt_clear(dev, 0);
+
+	/* Enable System IRQ so that GR-RASTA-IO PCI target interrupt goes
+	 * through.
+	 *
+	 * It is important to enable it in stage init2. If interrupts were
+	 * enabled in init1 this might hang the system when more than one
+	 * PCI board is connected, this is because PCI interrupts might
+	 * be shared and PCI board 2 have not initialized and
+	 * might therefore drive interrupt already when entering init1().
+	 */
+	drvmgr_interrupt_register(
+		dev,
+		0,
+		"gr_rasta_io",
+		gr_rasta_io_isr,
+		(void *)priv);
+
+	return gr_rasta_io_hw_init2(priv);
+}
+
+int ambapp_rasta_io_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg)
+{
+	struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_register(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Clear IRQ for first registered handler */
+		priv->irq->iclear = (1<<irq);
+	} else if ( status == 1 )
+		status = 0;
+
+	if (status != 0) {
+		rtems_interrupt_enable(level);
+		return DRVMGR_FAIL;
+	}
+
+	status = genirq_enable(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Enable IRQ for first enabled handler only */
+		priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_io_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg)
+{
+	struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_disable(priv->genirq, irq, isr, arg);
+	if ( status == 0 ) {
+		/* Disable IRQ only when no enabled handler exists */
+		priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+	}
+
+	status = genirq_unregister(priv->genirq, irq, isr, arg);
+	if ( status != 0 )
+		status = DRVMGR_FAIL;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_io_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-IO IRQ %d: unmask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Enable IRQ for first enabled handler only */
+	priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_io_int_mask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-IO IRQ %d: mask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Disable/mask IRQ */
+	priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_io_int_clear(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	priv->irq->iclear = (1<<irq);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_io_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+	struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+
+	/* Device name prefix pointer, skip /dev */
+	params->dev_prefix = &priv->prefix[5];
+
+	return 0;
+}
+
+void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options)
+{
+	struct gr_rasta_io_priv *priv = dev->priv;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+
+	/* Print */
+	printf("--- GR-RASTA-IO [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ REGS:        0x%x\n", (unsigned int)priv->irq);
+	printf(" IRQ:             %d\n", devinfo->irq);
+	printf(" PCI REVISION:    %d\n", devinfo->rev);
+	printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
+	printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
+	printf(" IPEND:           0x%08x\n", priv->irq->ipend);
+
+	/* Print amba config */
+	if ( options & RASTA_IO_OPTIONS_AMBA ) {
+		ambapp_print(&priv->abus, 10);
+	}
+
+#if 0
+	/* Print IRQ handlers and their arguments */
+	if ( options & RASTA_IO_OPTIONS_IRQ ) {
+		int i;
+		for(i=0; i<16; i++) {
+			printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n", 
+				i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+		}
+	}
+#endif
+}
+
+void gr_rasta_io_print(int options)
+{
+	struct pci_drv_info *drv = &gr_rasta_io_info;
+	struct drvmgr_dev *dev;
+
+	dev = drv->general.dev;
+	while(dev) {
+		gr_rasta_io_print_dev(dev, options);
+		dev = dev->next_in_drv;
+	}
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c
new file mode 100644
index 0000000000..027c1d4f82
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c
@@ -0,0 +1,675 @@
+/*  GR-RASTA-SPW-ROUTER PCI Target driver.
+ * 
+ *  COPYRIGHT (c) 2011.
+ *  Cobham Gaisler AB.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  Configures the GR-RASTA-SPW-ROUTER interface PCI board.
+ *  This driver provides a AMBA PnP bus by using the general part
+ *  of the AMBA PnP bus driver (ambapp_bus.c). Based on the 
+ *  GR-RASTA-IO driver.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+/*#include <gr_rasta_spw_router.h> */
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+/* Offset from 0x80000000 (dual bus version) */
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80100000
+
+#define GRPCI2_BAR0_TO_AHB_MAP 0x04  /* Fixme */
+#define GRPCI2_PCI_CONFIG      0x20  /* Fixme */
+#define RASTA_SPW_ROUTER_OPTIONS_AMBA  0x01 /* Print AMBA bus devices */  /* Fixme */
+#define RASTA_SPW_ROUTER_OPTIONS_IRQ   0x02 /* Print current IRQ setup */ /* Fixme */
+
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) 
+#endif
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER		0x1AC8
+
+int gr_rasta_spw_router_init1(struct drvmgr_dev *dev);
+int gr_rasta_spw_router_init2(struct drvmgr_dev *dev);
+
+struct grpci2_regs {
+	volatile unsigned int ctrl;
+	volatile unsigned int statcap;
+	volatile unsigned int pcimstprefetch;
+	volatile unsigned int ahbtopciiomap;
+	volatile unsigned int dmactrl;
+	volatile unsigned int dmadesc;
+	volatile unsigned int dmachanact;
+	volatile unsigned int reserved;
+	volatile unsigned int pcibartoahb[6];
+	volatile unsigned int reserved2[2];
+	volatile unsigned int ahbtopcimemmap[16];
+	volatile unsigned int trcctrl;
+	volatile unsigned int trccntmode;
+	volatile unsigned int trcadpat;
+	volatile unsigned int trcadmask;
+	volatile unsigned int trcctrlsigpat;
+	volatile unsigned int trcctrlsigmask;
+	volatile unsigned int trcadstate;
+	volatile unsigned int trcctrlsigstate;
+};
+
+struct gr_rasta_spw_router_ver {
+	const unsigned int	amba_freq_hz;	/* The frequency */
+	const unsigned int	amba_ioarea;	/* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_spw_router_priv {
+	/* Driver management */
+	struct drvmgr_dev	*dev;
+	char			prefix[20];
+
+	/* PCI */
+	pci_dev_t		pcidev;
+	struct pci_dev_info	*devinfo;
+	uint32_t		ahbmst2pci_map;
+
+	/* IRQ */
+	genirq_t		genirq;
+
+	/* GR-RASTA-SPW-ROUTER */
+	struct gr_rasta_spw_router_ver	*version;
+	struct irqmp_regs	*irq;
+	struct grpci2_regs	*grpci2;
+	struct drvmgr_map_entry	bus_maps_up[2];
+	struct drvmgr_map_entry	bus_maps_down[2];
+
+	/* AMBA Plug&Play information on GR-RASTA-SPW-ROUTER */
+	struct ambapp_bus	abus;
+	struct ambapp_mmap	amba_maps[3];
+	struct ambapp_config	config;
+};
+
+struct gr_rasta_spw_router_ver gr_rasta_spw_router_ver0 = {
+	.amba_freq_hz		= 50000000,
+	.amba_ioarea		= 0xfff00000,
+};
+
+int ambapp_rasta_spw_router_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_spw_router_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_spw_router_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_spw_router_int_mask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_spw_router_int_clear(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_spw_router_get_params(
+	struct drvmgr_dev *dev,
+	struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_spw_router_ops = {
+	.int_register = ambapp_rasta_spw_router_int_register,
+	.int_unregister = ambapp_rasta_spw_router_int_unregister,
+	.int_unmask = ambapp_rasta_spw_router_int_unmask,
+	.int_mask = ambapp_rasta_spw_router_int_mask,
+	.int_clear = ambapp_rasta_spw_router_int_clear,
+	.get_params = ambapp_rasta_spw_router_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_spw_router_ops = 
+{
+	.init = {gr_rasta_spw_router_init1, gr_rasta_spw_router_init2, NULL, NULL},
+	.remove = NULL,
+	.info = NULL
+};
+
+struct pci_dev_id_match gr_rasta_spw_router_ids[] =
+{
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR),
+	PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_spw_router_info =
+{
+	{
+		DRVMGR_OBJ_DRV,			/* Driver */
+		NULL,				/* Next driver */
+		NULL,				/* Device list */
+		DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID,	/* Driver ID */
+		"GR-RASTA-SPW_ROUTER_DRV",	/* Driver Name */
+		DRVMGR_BUS_TYPE_PCI,		/* Bus Type */
+		&gr_rasta_spw_router_ops,
+		NULL,				/* Funcs */
+		0,				/* No devices yet */
+		sizeof(struct gr_rasta_spw_router_priv),
+	},
+	&gr_rasta_spw_router_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-SPW-ROUTER board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-SPW-ROUTER board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_spw_router_resources[] __attribute__((weak)) =
+{
+	NULL
+};
+int gr_rasta_spw_router_resources_cnt = 0;
+
+void gr_rasta_spw_router_register_drv(void)
+{
+	DBG("Registering GR-RASTA-SPW-ROUTER PCI driver\n");
+	drvmgr_drv_register(&gr_rasta_spw_router_info.general);
+}
+
+void gr_rasta_spw_router_isr(void *arg)
+{
+	struct gr_rasta_spw_router_priv *priv = arg;
+	unsigned int status, tmp;
+	int irq;
+	tmp = status = priv->irq->ipend;
+
+	/* DBG("GR-RASTA-SPW-ROUTER: IRQ 0x%x\n",status); */
+
+	for(irq=0; irq<16; irq++) {
+		if ( status & (1<<irq) ) {
+			genirq_doirq(priv->genirq, irq);
+			priv->irq->iclear = (1<<irq);
+			status &= ~(1<<irq);
+			if ( status == 0 )
+				break;
+		}
+	}
+
+	/* ACK interrupt, this is because PCI is Level, so the IRQ Controller
+	 * still drives the IRQ
+	 */
+	if ( tmp ) 
+		drvmgr_interrupt_clear(priv->dev, 0);
+
+	DBG("RASTA-SPW_ROUTER-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_spw_router_hw_init(struct gr_rasta_spw_router_priv *priv)
+{
+	int i;
+	uint32_t data;
+	unsigned int ctrl;
+	uint8_t tmp2;
+	struct ambapp_dev *tmp;
+	int status;
+	struct ambapp_ahb_info *ahb;
+	uint8_t cap_ptr;
+	pci_dev_t pcidev = priv->pcidev;
+	struct pci_dev_info *devinfo = priv->devinfo;
+
+	/* Select version of GR-RASTA-SPW-ROUTER board. Currently only one
+	 * version
+	 */
+	switch (devinfo->rev) {
+		case 0:
+			priv->version = &gr_rasta_spw_router_ver0;
+			break;
+		default:
+			return -2;
+	}
+
+	/* Check capabilities list bit */
+	pci_cfg_r8(pcidev, PCI_STATUS, &tmp2);
+
+	if (!((tmp2 >> 4) & 1)) {
+		/* Capabilities list not available which it should be in the GRPCI2 */
+		return -3;
+	}
+
+	/* Read capabilities pointer */
+	pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr);
+
+	/* Set AHB address mappings for target PCI bars */
+	pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR0_TO_AHB_MAP, 0xffe00000);  /* APB bus, AHB I/O bus 2 MB */ 
+
+	/* Set PCI bus to be big endian */
+	pci_cfg_r32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, &data);
+	data = data & 0xFFFFFFFE;
+	pci_cfg_w32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, data);
+
+#if 0
+	/* set parity error response */
+	pci_cfg_r32(pcidev, PCI_COMMAND, &data);
+	pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+#endif
+
+	/* Scan AMBA Plug&Play */
+
+	/* AMBA MAP bar0 (in router) ==> 0xffe00000(remote amba address) */
+	priv->amba_maps[0].size = devinfo->resources[0].size;
+	priv->amba_maps[0].local_adr = devinfo->resources[0].address;
+	priv->amba_maps[0].remote_adr = 0xffe00000;
+
+	/* Addresses not matching with map be untouched */
+	priv->amba_maps[1].size = 0xfffffff0;
+	priv->amba_maps[1].local_adr = 0;
+	priv->amba_maps[1].remote_adr = 0;
+
+	/* Mark end of table */
+	priv->amba_maps[2].size=0;
+
+	/* Start AMBA PnP scan at first AHB bus */
+	ambapp_scan(
+		&priv->abus,
+		devinfo->resources[0].address + 0x100000,
+		NULL,
+		&priv->amba_maps[0]);
+
+	/* Initialize Frequency of AMBA bus */
+	ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
+
+	/* Find IRQ controller, Clear all current IRQs */
+	tmp = ambapp_for_each(&priv->abus,
+				(OPTIONS_ALL|OPTIONS_APB_SLVS),
+				VENDOR_GAISLER, GAISLER_IRQMP,
+				ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -4;
+	}
+	priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+	/* Set up GR-RASTA-SPW-ROUTER irq controller */
+	priv->irq->mask[0] = 0;
+	priv->irq->iclear = 0xffff;
+	priv->irq->ilevel = 0;
+
+	priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+	priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+	priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+	priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+	priv->bus_maps_down[1].size = 0;
+
+	/* Find GRPCI2 controller AHB Slave interface */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_AHB_SLVS),
+					VENDOR_GAISLER, GAISLER_GRPCI2,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -5;
+	}
+	ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+	priv->bus_maps_up[0].name = "AMBA GRPCI2 Window";
+	priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-SPW-ROUTER board */
+	priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+	priv->bus_maps_up[0].to_adr = (void *)
+				(priv->ahbmst2pci_map & ~(ahb->mask[0]-1));
+	priv->bus_maps_up[1].size = 0;
+
+	/* Find GRPCI2 controller APB Slave interface */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_GRPCI2,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -6;
+	}
+	priv->grpci2 = (struct grpci2_regs *)
+		((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+	/* Set AHB to PCI mapping for all AMBA AHB masters */
+	for(i = 0; i < 16; i++) {
+		priv->grpci2->ahbtopcimemmap[i] = priv->ahbmst2pci_map &
+							~(ahb->mask[0]-1);
+	}
+
+	/* Make sure dirq(0) sampling is enabled */
+	ctrl = priv->grpci2->ctrl;
+	ctrl = (ctrl & 0xFFFFFF0F) | (1 << 4);
+	printf("data: 0x%x\n", ctrl);
+	priv->grpci2->ctrl = ctrl;
+
+	/* Successfully registered the RASTA-SPW-ROUTER board */
+	return 0;
+}
+
+int gr_rasta_spw_router_hw_init2(struct gr_rasta_spw_router_priv *priv)
+{
+	/* Enable DMA by enabling PCI target as master */
+	pci_master_enable(priv->pcidev);
+
+	return DRVMGR_OK;
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr_rasta_spw_router_ids[].
+ */
+int gr_rasta_spw_router_init1(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_spw_router_priv *priv;
+	struct pci_dev_info *devinfo;
+	int status;
+	uint32_t bar0, bar0_size;
+	union drvmgr_key_value *value;
+
+	priv = dev->priv;
+	if (!priv)
+		return DRVMGR_NOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+	dev->priv = priv;
+	priv->dev = dev;
+
+	/* Determine number of configurations */
+	if ( gr_rasta_spw_router_resources_cnt == 0 ) {
+		while ( gr_rasta_spw_router_resources[gr_rasta_spw_router_resources_cnt] )
+			gr_rasta_spw_router_resources_cnt++;
+	}
+
+	/* Generate Device prefix */
+
+	strcpy(priv->prefix, "/dev/spwrouter0");
+	priv->prefix[14] += dev->minor_drv;
+	mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+	priv->prefix[15] = '/';
+	priv->prefix[16] = '\0';
+
+	priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+	priv->pcidev = devinfo->pcidev;
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	printf("\n\n--- GR-RASTA-SPW-ROUTER[%d] ---\n", dev->minor_drv);
+	printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+		devinfo->id.vendor, devinfo->id.device);
+	printf(" PCI BAR[0]: 0x%08lx - 0x%08lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+	/* all neccessary space assigned to GR-RASTA-SPW-ROUTER target? */
+	if (bar0_size == 0)
+		return DRVMGR_ENORES;
+
+	/* Let user override which PCI address the AHB masters of the
+	 * GR-RASTA-SPW board access when doing DMA to CPU RAM. The AHB masters
+	 * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+	 * is translated according this config option before the address
+	 * goes out on the PCI bus.
+	 * Only the 4 MSB bits have an effect;
+	 */
+	value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+	if (value)
+		priv->ahbmst2pci_map = value->i;
+	else
+		priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */	
+
+	priv->genirq = genirq_init(16);
+	if ( priv->genirq == NULL )
+		return DRVMGR_FAIL;
+
+	if ((status = gr_rasta_spw_router_hw_init(priv)) != 0) {
+		genirq_destroy(priv->genirq);
+		printf(" Failed to initialize GR-RASTA-SPW-ROUTER HW: %d\n", status);
+		return DRVMGR_FAIL;
+	}
+
+	/* Init amba bus */
+	priv->config.abus = &priv->abus;
+	priv->config.ops = &ambapp_rasta_spw_router_ops;
+	priv->config.maps_up = &priv->bus_maps_up[0];
+	priv->config.maps_down = &priv->bus_maps_down[0];
+	if ( priv->dev->minor_drv < gr_rasta_spw_router_resources_cnt ) {
+		priv->config.resources = gr_rasta_spw_router_resources[priv->dev->minor_drv];
+	} else {
+		priv->config.resources = NULL;
+	}
+
+	/* Create and register AMBA PnP bus. */
+	return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_spw_router_init2(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->priv;
+
+	/* Clear any old interrupt requests */
+	drvmgr_interrupt_clear(dev, 0);
+
+	/* Enable System IRQ so that GR-RASTA-SPW-ROUTER PCI target interrupt
+	 * goes through.
+	 *
+	 * It is important to enable it in stage init2. If interrupts were
+	 * enabled in init1 this might hang the system when more than one
+	 * PCI board is connected, this is because PCI interrupts might
+	 * be shared and PCI board 2 have not initialized and
+	 * might therefore drive interrupt already when entering init1().
+	 */
+	drvmgr_interrupt_register(
+		dev,
+		0,
+		"gr_rasta_spw_router",
+		gr_rasta_spw_router_isr,
+		(void *)priv);
+
+	return gr_rasta_spw_router_hw_init2(priv);
+}
+
+int ambapp_rasta_spw_router_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_register(priv->genirq, irq, handler, arg);
+	if (status == 0) {
+		/* Clear IRQ for first registered handler */
+		priv->irq->iclear = (1<<irq);
+	} else if (status == 1)
+		status = 0;
+
+	if (status != 0) {
+		rtems_interrupt_enable(level);
+		return DRVMGR_FAIL;
+	}
+
+	status = genirq_enable(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Enable IRQ for first enabled handler only */
+		priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_spw_router_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_disable(priv->genirq, irq, isr, arg);
+	if ( status == 0 ) {
+		/* Disable IRQ only when no enabled handler exists */
+		priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+	}
+
+	status = genirq_unregister(priv->genirq, irq, isr, arg);
+	if ( status != 0 )
+		status = DRVMGR_FAIL;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_spw_router_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-SPW-ROUTER IRQ %d: unmask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Enable IRQ for first enabled handler only */
+	priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_spw_router_int_mask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-SPW-ROUTER IRQ %d: mask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Disable/mask IRQ */
+	priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_spw_router_int_clear(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	priv->irq->iclear = (1<<irq);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_spw_router_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+
+	/* Device name prefix pointer, skip /dev */
+	params->dev_prefix = &priv->prefix[5];
+
+	return 0;
+}
+
+void gr_rasta_spw_router_print_dev(struct drvmgr_dev *dev, int options)
+{
+	struct gr_rasta_spw_router_priv *priv = dev->priv;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar0_size;
+
+	/* Print */
+	printf("--- GR-RASTA-SPW-ROUTER [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" IRQ REGS:        0x%x\n", (unsigned int)priv->irq);
+	printf(" IRQ:             %d\n", devinfo->irq);
+	printf(" PCI REVISION:    %d\n", devinfo->rev);
+	printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
+	printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
+	printf(" IPEND:           0x%08x\n", priv->irq->ipend);
+
+	/* Print amba config */
+	if (options & RASTA_SPW_ROUTER_OPTIONS_AMBA)
+		ambapp_print(&priv->abus, 10);
+
+#if 0
+	/* Print IRQ handlers and their arguments */
+	if (options & RASTA_SPW_ROUTER_OPTIONS_IRQ) {
+		int i;
+		for(i = 0; i < 16; i++) {
+			printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n", 
+				i, (unsigned int)priv->isrs[i].handler,
+				(unsigned int)priv->isrs[i].arg);
+		}
+	}
+#endif
+}
+
+void gr_rasta_spw_router_print(int options)
+{
+	struct pci_drv_info *drv = &gr_rasta_spw_router_info;
+	struct drvmgr_dev *dev;
+
+	dev = drv->general.dev;
+	while(dev) {
+		gr_rasta_spw_router_print_dev(dev, options);
+		dev = dev->next_in_drv;
+	}
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c
new file mode 100644
index 0000000000..7a100836ae
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c
@@ -0,0 +1,684 @@
+/*  GR-RASTA-TMTC PCI Target driver.
+ * 
+ *  COPYRIGHT (c) 2008.
+ *  Cobham Gaisler AB.
+ *
+ *  Configures the GR-RASTA-TMTC interface PCI board.
+ *  This driver provides a AMBA PnP bus by using the general part
+ *  of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ *  Driver resources for the AMBA PnP bus provided can be set by overriding
+ *  the defaults by declaring gr_rasta_tmtc_resources[].
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_rasta_tmtc.h>
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+#define GAISLER_GPIO         0x01a
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80200000
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) 
+#endif
+
+int gr_rasta_tmtc_init1(struct drvmgr_dev *dev);
+int gr_rasta_tmtc_init2(struct drvmgr_dev *dev);
+
+struct grpci_regs {
+	volatile unsigned int cfg_stat;
+	volatile unsigned int bar0;
+	volatile unsigned int page0;
+	volatile unsigned int bar1;
+	volatile unsigned int page1;
+	volatile unsigned int iomap;
+	volatile unsigned int stat_cmd;
+};
+
+struct gr_rasta_tmtc_ver {
+	const unsigned int	amba_freq_hz;	/* The frequency */
+	const unsigned int	amba_ioarea;	/* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_tmtc_priv {
+	/* Driver management */
+	struct drvmgr_dev	*dev;
+	char				prefix[20];
+
+	/* PCI */
+	pci_dev_t			pcidev;
+	struct pci_dev_info		*devinfo;
+	uint32_t			ahbmst2pci_map;
+
+	/* IRQ */
+	genirq_t			genirq;
+
+	/* GR-RASTA-TMTC */
+	struct gr_rasta_tmtc_ver	*version;
+	struct irqmp_regs		*irq;
+	struct grpci_regs		*grpci;
+	struct grgpio_regs		*gpio;
+	struct drvmgr_map_entry		bus_maps_down[3];
+	struct drvmgr_map_entry		bus_maps_up[2];
+
+	/* AMBA Plug&Play information on GR-RASTA-TMTC */
+	struct ambapp_bus		abus;
+	struct ambapp_mmap		amba_maps[4];
+        struct ambapp_config		config;
+};
+
+struct gr_rasta_tmtc_ver gr_rasta_tmtc_ver0 = {
+	.amba_freq_hz		= 30000000,
+	.amba_ioarea		= AHB1_IOAREA_BASE_ADDR,
+};
+
+int ambapp_rasta_tmtc_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_tmtc_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_rasta_tmtc_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_tmtc_int_mask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_tmtc_int_clear(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_rasta_tmtc_get_params(
+	struct drvmgr_dev *dev,
+	struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_tmtc_ops = {
+	.int_register = ambapp_rasta_tmtc_int_register,
+	.int_unregister = ambapp_rasta_tmtc_int_unregister,
+	.int_unmask = ambapp_rasta_tmtc_int_unmask,
+	.int_mask = ambapp_rasta_tmtc_int_mask,
+	.int_clear = ambapp_rasta_tmtc_int_clear,
+	.get_params = ambapp_rasta_tmtc_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_tmtc_ops = 
+{
+	.init = {gr_rasta_tmtc_init1, gr_rasta_tmtc_init2, NULL, NULL},
+	.remove = NULL,
+	.info = NULL,
+};
+
+struct pci_dev_id_match gr_rasta_tmtc_ids[] =
+{
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC),
+	PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_tmtc_info =
+{
+	{
+		DRVMGR_OBJ_DRV,			/* Driver */
+		NULL,				/* Next driver */
+		NULL,				/* Device list */
+		DRIVER_PCI_GAISLER_RASTATMTC_ID,/* Driver ID */
+		"GR-RASTA-TMTC_DRV",		/* Driver Name */
+		DRVMGR_BUS_TYPE_PCI,		/* Bus Type */
+		&gr_rasta_tmtc_ops,
+		NULL,				/* Funcs */
+		0,				/* No devices yet */
+		sizeof(struct gr_rasta_tmtc_priv) /* Let drvmgr alloc private */
+	},
+	&gr_rasta_tmtc_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-TMTC board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-TMTC board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_tmtc_resources[] __attribute__((weak)) =
+{
+	NULL,
+};
+int gr_rasta_tmtc_resources_cnt = 0;
+
+void gr_rasta_tmtc_register_drv(void)
+{
+	DBG("Registering GR-RASTA-TMTC PCI driver\n");
+	drvmgr_drv_register(&gr_rasta_tmtc_info.general);
+}
+
+void gr_rasta_tmtc_isr (void *arg)
+{
+	struct gr_rasta_tmtc_priv *priv = arg;
+	unsigned int status, tmp;
+	int irq;
+	tmp = status = priv->irq->ipend;
+
+	/* printk("GR-RASTA-TMTC: IRQ 0x%x\n",status); */
+
+	for(irq=0; irq<32; irq++) {
+		if ( status & (1<<irq) ) {
+			genirq_doirq(priv->genirq, irq);
+			priv->irq->iclear = (1<<irq);
+			status &= ~(1<<irq);
+			if ( status == 0 )
+				break;
+		}
+	}
+
+	/* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+	if ( tmp )
+		drvmgr_interrupt_clear(priv->dev, 0);
+
+	DBG("RASTA-TMTC-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_tmtc_hw_init(struct gr_rasta_tmtc_priv *priv)
+{
+	unsigned int *page0 = NULL;
+	struct ambapp_dev *tmp;
+	struct ambapp_ahb_info *ahb;
+	unsigned int pci_freq_hz;
+	pci_dev_t pcidev = priv->pcidev;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar0_size;
+
+	/* Select version of GR-RASTA-TMTC board */
+	switch (devinfo->rev) {
+		case 0:
+			priv->version = &gr_rasta_tmtc_ver0;
+			break;
+		default:
+			return -2;
+	}
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	page0 = (unsigned int *)(bar0 + bar0_size/2); 
+
+	/* Point PAGE0 to start of Plug and Play information */
+	*page0 = priv->version->amba_ioarea & 0xf0000000;
+
+#if 0
+	{
+		uint32_t data;
+		/* set parity error response */
+		pci_cfg_r32(pcidev, PCI_COMMAND, &data);
+		pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+	}
+#endif
+
+	/* Scan AMBA Plug&Play */
+
+	/* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+	priv->amba_maps[0].size = 0x10000000;
+	priv->amba_maps[0].local_adr = bar0;
+	priv->amba_maps[0].remote_adr = AHB1_BASE_ADDR;
+
+	/* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
+	priv->amba_maps[1].size = devinfo->resources[1].size;
+	priv->amba_maps[1].local_adr = devinfo->resources[1].address;
+	priv->amba_maps[1].remote_adr = 0x40000000;
+
+	/* Addresses not matching with map be untouched */
+	priv->amba_maps[2].size = 0xfffffff0;
+	priv->amba_maps[2].local_adr = 0;
+	priv->amba_maps[2].remote_adr = 0;
+
+	/* Mark end of table */
+	priv->amba_maps[3].size=0;
+	priv->amba_maps[3].local_adr = 0;
+	priv->amba_maps[3].remote_adr = 0;
+
+	/* Start AMBA PnP scan at first AHB bus */
+	ambapp_scan(&priv->abus,
+		bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+		NULL, &priv->amba_maps[0]);
+
+	/* Frequency is the same as the PCI bus frequency */
+	drvmgr_freq_get(priv->dev, 0, &pci_freq_hz);
+
+	/* Initialize Frequency of AMBA bus */
+	ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
+
+	/* Point PAGE0 to start of APB area */
+	*page0 = AHB1_BASE_ADDR;
+
+	/* Find GRPCI controller */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_PCIFBRG,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -3;
+	}
+	priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+	/* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
+	 * the PCI window.
+	 */
+	priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
+				(priv->ahbmst2pci_map & 0xf0000000);
+	priv->grpci->page1 = 0x40000000;
+
+	/* Find IRQ controller, Clear all current IRQs */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_IRQMP,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -4;
+	}
+	priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+	/* Set up GR-RASTA-TMTC irq controller */
+	priv->irq->mask[0] = 0;
+	priv->irq->iclear = 0xffffffff;
+	priv->irq->ilevel = 0;
+
+	/* Find First GPIO controller */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_GPIO,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -5;
+	}
+	priv->gpio = (struct grgpio_regs *) (((struct ambapp_apb_info *)tmp->devinfo)->start);
+	/* Clear GR-RASTA-TMTC GPIO controller */
+	priv->gpio->imask = 0;
+	priv->gpio->ipol = 0;
+	priv->gpio->iedge = 0;
+	priv->gpio->bypass = 0;
+	/* Set up GR-RASTA-TMTC GPIO controller to select GRTM and GRTC */
+	priv->gpio->output = (GR_TMTC_GPIO_GRTM_SEL|GR_TMTC_GPIO_TRANSP_CLK) | (GR_TMTC_GPIO_TC_BIT_LOCK|GR_TMTC_GPIO_TC_RF_AVAIL|GR_TMTC_GPIO_TC_ACTIVE_HIGH|GR_TMTC_GPIO_TC_RISING_CLK);
+	priv->gpio->dir = 0xffffffff;
+	DBG("GR-TMTC GPIO: 0x%x\n", (unsigned int)priv->gpio);
+
+	/* Enable DMA by enabling PCI target as master */
+	pci_master_enable(pcidev);
+
+	/* DOWN streams translation table */
+	priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+	priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+	priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+	priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+
+	priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
+	priv->bus_maps_down[1].size = priv->amba_maps[1].size;
+	priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
+	priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
+
+	/* Mark end of translation table */
+	priv->bus_maps_down[2].size = 0;
+
+	/* Find GRPCI controller AHB Slave interface */
+	tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus,
+				(OPTIONS_ALL|OPTIONS_AHB_SLVS),
+				VENDOR_GAISLER, GAISLER_PCIFBRG,
+				ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -6;
+	}
+	ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+
+	/* UP streams translation table */
+	priv->bus_maps_up[0].name = "AMBA GRPCI Window";
+	priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-TMTC board */
+	priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+	priv->bus_maps_up[0].to_adr = (void *)
+					(priv->ahbmst2pci_map & 0xf0000000);
+
+	/* Mark end of translation table */
+	priv->bus_maps_up[1].size = 0;
+
+	/* Successfully registered the RASTA board */
+	return 0;
+}
+
+void gr_rasta_tmtc_hw_init2(struct gr_rasta_tmtc_priv *priv)
+{
+	/* Enable DMA by enabling PCI target as master */
+	pci_master_enable(priv->pcidev);
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr_rasta_tmtc_ids[].
+ */
+int gr_rasta_tmtc_init1(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_tmtc_priv *priv;
+	struct pci_dev_info *devinfo;
+	int status;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+	union drvmgr_key_value *value;
+
+	priv = dev->priv;
+	if (!priv)
+		return DRVMGR_NOMEM;
+	priv->dev = dev;
+
+	/* Determine number of configurations */
+	if ( gr_rasta_tmtc_resources_cnt == 0 ) {
+		while ( gr_rasta_tmtc_resources[gr_rasta_tmtc_resources_cnt] )
+			gr_rasta_tmtc_resources_cnt++;
+	}
+
+	/* Generate Device prefix */
+
+	strcpy(priv->prefix, "/dev/rastatmtc0");
+	priv->prefix[14] += dev->minor_drv;
+	mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+	priv->prefix[15] = '/';
+	priv->prefix[16] = '\0';
+
+	priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+	priv->pcidev = devinfo->pcidev;
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+	printf("\n\n--- GR-RASTA-TMTC[%d] ---\n", dev->minor_drv);
+	printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+		devinfo->id.vendor, devinfo->id.device);
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+	/* all neccessary space assigned to GR-RASTA-IO target? */
+	if ((bar0_size == 0) || (bar1_size == 0))
+		return DRVMGR_ENORES;
+
+	/* Let user override which PCI address the AHB masters of the
+	 * GR-RASTA-TMTC board access when doing DMA to CPU RAM. The AHB masters
+	 * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+	 * is translated according this config option before the address
+	 * goes out on the PCI bus.
+	 * Only the 4 MSB bits have an effect;
+	 */
+	value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+	if (value)
+		priv->ahbmst2pci_map = value->i;
+	else
+		priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */	
+
+	priv->genirq = genirq_init(32);
+	if ( priv->genirq == NULL )
+		return DRVMGR_FAIL;
+
+	status = gr_rasta_tmtc_hw_init(priv);
+	if ( status != 0 ) {
+		genirq_destroy(priv->genirq);
+		printf(" Failed to initialize GR-RASTA-TMTC HW: %d\n", status);
+		return DRVMGR_FAIL;
+	}
+
+	/* Init amba bus */
+	priv->config.abus = &priv->abus;
+	priv->config.ops = &ambapp_rasta_tmtc_ops;
+	priv->config.maps_up = &priv->bus_maps_up[0];
+	priv->config.maps_down = &priv->bus_maps_down[0];
+	if ( priv->dev->minor_drv < gr_rasta_tmtc_resources_cnt ) {
+		priv->config.resources = gr_rasta_tmtc_resources[priv->dev->minor_drv];
+	} else {
+		priv->config.resources = NULL;
+	}
+
+	return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_tmtc_init2(struct drvmgr_dev *dev)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->priv;
+
+	/* Clear any old interrupt requests */
+	drvmgr_interrupt_clear(priv->dev, 0);
+
+	/* Enable System IRQ so that GR-RASTA-TMTC PCI target interrupt goes
+	 * through.
+	 *
+	 * It is important to enable it in stage init2. If interrupts were
+	 * enabled in init1 this might hang the system when more than one
+	 * PCI target is connected, this is because PCI interrupts might 
+	 * be shared and PCI board 2 have not initialized and
+	 * might therefore drive interrupt already when entering init1().
+	 */
+	drvmgr_interrupt_register(
+		priv->dev,
+		0,
+		"gr_rasta_tmtc",
+		gr_rasta_tmtc_isr,
+		(void *)priv);
+
+	gr_rasta_tmtc_hw_init2(priv);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_register(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Disable and clear IRQ for first registered handler */
+		priv->irq->iclear = (1<<irq);
+	} else if ( status == 1 )
+		status = 0;
+
+	if (status != 0) {
+		rtems_interrupt_enable(level);
+		return DRVMGR_FAIL;
+	}
+
+	status = genirq_enable(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Enable IRQ for first enabled handler only */
+		priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_tmtc_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_disable(priv->genirq, irq, isr, arg);
+	if ( status == 0 ) {
+		/* Disable IRQ only when no enabled handler exists */
+		priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	status = genirq_unregister(priv->genirq, irq, isr, arg);
+	if ( status != 0 )
+		status = DRVMGR_FAIL;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_rasta_tmtc_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-TMTC IRQ %d: unmask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Enable IRQ */
+	priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_int_mask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("RASTA-TMTC IRQ %d: mask\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_EINVAL;
+
+	rtems_interrupt_disable(level);
+
+	/* Disable IRQ */
+	priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_int_clear(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	priv->irq->iclear = (1<<irq);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+
+	/* Device name prefix pointer, skip /dev */
+	params->dev_prefix = &priv->prefix[5];
+
+	return 0;
+}
+
+void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options)
+{
+	struct gr_rasta_tmtc_priv *priv = dev->priv;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar1, bar0_size, bar1_size;
+
+	/* Print */
+	printf("--- GR-RASTA-TMTC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	bar1 = devinfo->resources[1].address;
+	bar1_size = devinfo->resources[1].size;
+
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+	printf(" IRQ:             %d\n", devinfo->irq);
+	printf(" PCI REVISION:    %d\n", devinfo->rev);
+	printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
+	printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
+	printf(" IPEND:           0x%08x\n", priv->irq->ipend);
+
+	/* Print amba config */
+	if ( options & RASTA_TMTC_OPTIONS_AMBA ) {
+		ambapp_print(&priv->abus, 10);
+	}
+
+#if 0
+	/* Print IRQ handlers and their arguments */
+	if ( options & RASTA_TMTC_OPTIONS_IRQ ) {
+		int i;
+		for(i=0; i<16; i++) {
+			printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n", 
+				i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+		}
+	}
+#endif
+}
+
+void gr_rasta_tmtc_print(int options)
+{
+	struct pci_drv_info *drv = &gr_rasta_tmtc_info;
+	struct drvmgr_dev *dev;
+
+	dev = drv->general.dev;
+	while(dev) {
+		gr_rasta_tmtc_print_dev(dev, options);
+		dev = dev->next_in_drv;
+	}
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c b/c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c
new file mode 100644
index 0000000000..6b512a9748
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c
@@ -0,0 +1,571 @@
+/*  GR-TMTC-1553 PCI Target driver.
+ * 
+ *  COPYRIGHT (c) 2008.
+ *  Cobham Gaisler AB.
+ *
+ *  Configures the GR-TMTC-1553 interface PCI board.
+ *  This driver provides a AMBA PnP bus by using the general part
+ *  of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ *  Driver resources for the AMBA PnP bus provided can be set using
+ *  gr_tmtc_1553_set_resources().
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+#include <pci/access.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_tmtc_1553.h>
+
+
+/*#define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) 
+#endif
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER		0x1AC8
+
+int gr_tmtc_1553_init1(struct drvmgr_dev *dev);
+int gr_tmtc_1553_init2(struct drvmgr_dev *dev);
+
+struct gr_tmtc_1553_ver {
+	const unsigned int	amba_freq_hz;	/* The frequency */
+	const unsigned int	amba_ioarea;	/* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_tmtc_1553_priv {
+	/* Driver management */
+	struct drvmgr_dev	*dev;
+	char				prefix[32];
+
+	/* PCI */
+	pci_dev_t			pcidev;
+	struct pci_dev_info		*devinfo;
+
+	/* IRQ */
+	genirq_t			genirq;
+
+	struct gr_tmtc_1553_ver         *version;
+	struct irqmp_regs		*irq;
+	struct drvmgr_map_entry		bus_maps_down[2];
+
+	struct ambapp_bus		abus;
+	struct ambapp_mmap		amba_maps[4];
+        struct ambapp_config		config;
+};
+
+struct gr_tmtc_1553_ver gr_tmtc_1553_ver0 = {
+	.amba_freq_hz		= 33333333,
+	.amba_ioarea		= 0xfff00000,
+};
+
+
+int ambapp_tmtc_1553_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_tmtc_1553_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr handler,
+	void *arg);
+int ambapp_tmtc_1553_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_tmtc_1553_int_mask(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_tmtc_1553_int_clear(
+	struct drvmgr_dev *dev,
+	int irq);
+int ambapp_tmtc_1553_get_params(
+	struct drvmgr_dev *dev,
+	struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_tmtc_1553_ops = {
+	.int_register = ambapp_tmtc_1553_int_register,
+	.int_unregister = ambapp_tmtc_1553_int_unregister,
+	.int_unmask = ambapp_tmtc_1553_int_unmask,
+	.int_mask = ambapp_tmtc_1553_int_mask,
+	.int_clear = ambapp_tmtc_1553_int_clear,
+	.get_params = ambapp_tmtc_1553_get_params
+};
+
+struct drvmgr_drv_ops gr_tmtc_1553_ops = 
+{
+	{gr_tmtc_1553_init1, gr_tmtc_1553_init2, NULL, NULL},
+	NULL,
+	NULL
+};
+
+struct pci_dev_id_match gr_tmtc_1553_ids[] = 
+{
+	PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553),
+	PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_tmtc_1553_info =
+{
+	{
+		DRVMGR_OBJ_DRV,			/* Driver */
+		NULL,				/* Next driver */
+		NULL,				/* Device list */
+		DRIVER_PCI_GAISLER_TMTC_1553_ID, /* Driver ID */
+		"GR-TMTC-1553_DRV",		/* Driver Name */
+		DRVMGR_BUS_TYPE_PCI,		/* Bus Type */
+		&gr_tmtc_1553_ops,
+		NULL,				/* Funcs */
+		0,				/* No devices yet */
+		0,
+	},
+	&gr_tmtc_1553_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-IO board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_tmtc_1553_resources[] __attribute__((weak)) =
+{
+	NULL
+};
+int gr_tmtc_1553_resources_cnt = 0;
+
+void gr_tmtc_1553_register_drv(void)
+{
+	DBG("Registering GR-TMTC-1553 PCI driver\n");
+	drvmgr_drv_register(&gr_tmtc_1553_info.general);
+}
+
+void gr_tmtc_1553_isr (void *arg)
+{
+	struct gr_tmtc_1553_priv *priv = arg;
+	unsigned int status, tmp;
+	int irq;
+	tmp = status = priv->irq->ipend;
+
+	/* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */
+
+	for(irq=0; irq<16; irq++) {
+		if ( status & (1<<irq) ) {
+			genirq_doirq(priv->genirq, irq);
+			priv->irq->iclear = (1<<irq);
+			status &= ~(1<<irq);
+			if ( status == 0 )
+				break;
+		}
+	}
+
+	/* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+	if ( tmp ) 
+		drvmgr_interrupt_clear(priv->dev, 0);
+
+	DBG("GR-TMTC-1553-IRQ: 0x%x\n", tmp);
+}
+
+int gr_tmtc_1553_hw_init(struct gr_tmtc_1553_priv *priv)
+{
+	unsigned int *page0 = NULL;
+	struct ambapp_dev *tmp;
+	int status;
+	unsigned int pci_freq_hz;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar0_size;
+
+	/* Select version of GR-TMTC-1553 board */
+	switch (devinfo->rev) {
+		case 0:
+			priv->version = &gr_tmtc_1553_ver0;
+			break;
+		default:
+			return -2;
+	}
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	page0 = (unsigned int *)(bar0 + bar0_size/2); 
+
+	/* Point PAGE0 to start of board address map. RAM at 0xff000000, APB at 0xffc00000, IOAREA at 0xfff000000 */
+	/* XXX We assume little endian host with byte twisting enabled here */
+	*page0 = 0x010000ff;	/* Set little endian mode on peripheral. */
+
+	/* Scan AMBA Plug&Play */
+
+	/* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+	priv->amba_maps[0].size = 0x1000000;
+	priv->amba_maps[0].local_adr = bar0;
+	priv->amba_maps[0].remote_adr = 0xff000000;
+	
+	/* Addresses not matching with map be untouched */
+	priv->amba_maps[2].size = 0xfffffff0;
+	priv->amba_maps[2].local_adr = 0;
+	priv->amba_maps[2].remote_adr = 0;
+
+	/* Mark end of table */
+	priv->amba_maps[3].size=0;
+	priv->amba_maps[3].local_adr = 0;
+	priv->amba_maps[3].remote_adr = 0;
+
+	/* Start AMBA PnP scan at first AHB bus */
+	ambapp_scan(&priv->abus,
+		bar0 + (priv->version->amba_ioarea & ~0xff000000),
+		NULL, &priv->amba_maps[0]);
+
+	/* Frequency is the hsame as the PCI bus frequency */
+	drvmgr_freq_get(priv->dev, NULL, &pci_freq_hz);
+
+	ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
+
+	/* Find IRQ controller */
+	tmp = (void *)ambapp_for_each(&priv->abus,
+					(OPTIONS_ALL|OPTIONS_APB_SLVS),
+					VENDOR_GAISLER, GAISLER_IRQMP,
+					ambapp_find_by_idx, NULL);
+	if ( !tmp ) {
+		return -4;
+	}
+	priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+	/* Set up irq controller */
+	priv->irq->mask[0] = 0;
+	priv->irq->iclear = 0xffff;
+	priv->irq->ilevel = 0;
+
+	/* DOWN streams translation table */
+	priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+	priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+	priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+	priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+	/* Mark end of translation table */
+	priv->bus_maps_down[1].size = 0;
+
+	/* Successfully registered the board */
+	return 0;
+}
+
+
+/* Called when a PCI target is found with the PCI device and vendor ID 
+ * given in gr_tmtc_1553_ids[].
+ */
+int gr_tmtc_1553_init1(struct drvmgr_dev *dev)
+{
+	struct gr_tmtc_1553_priv *priv;
+	struct pci_dev_info *devinfo;
+	int status;
+	uint32_t bar0, bar0_size;
+
+	/* PCI device does not have the IRQ line register, when PCI autoconf configures it the configuration
+	 * is forgotten. We take the IRQ number from the PCI Host device (AMBA device), this works as long
+	 * as PCI-IRQs are ored together on the bus.
+	 *
+	 * Note that this only works on LEON.
+	 */
+	((struct pci_dev_info *)dev->businfo)->irq = ((struct amba_dev_info *)dev->parent->dev->businfo)->info.irq; 
+	
+	priv = malloc(sizeof(struct gr_tmtc_1553_priv));
+	if ( !priv )
+		return DRVMGR_NOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+	dev->priv = priv;
+	priv->dev = dev;
+
+	/* Determine number of configurations */
+	if ( gr_tmtc_1553_resources_cnt == 0 ) {
+		while ( gr_tmtc_1553_resources[gr_tmtc_1553_resources_cnt] )
+			gr_tmtc_1553_resources_cnt++;
+	}
+
+	/* Generate Device prefix */
+
+	strcpy(priv->prefix, "/dev/tmtc1553_0/");
+	priv->prefix[19] += dev->minor_drv;
+	mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+	priv->prefix[20] = '/';
+	priv->prefix[21] = '\0';
+
+	priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+	priv->pcidev = devinfo->pcidev;
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+	printf("\n\n--- GR-TMTC-1553[%d] ---\n", dev->minor_drv);
+	printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+	printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+		devinfo->id.vendor, devinfo->id.device);
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+	/* all neccessary space assigned to GR-TMTC-1553 target? */
+	if (bar0_size == 0)
+		return DRVMGR_ENORES;
+
+	priv->genirq = genirq_init(16);
+	if ( priv->genirq == NULL ) {
+		free(priv);
+		dev->priv = NULL;
+		return DRVMGR_FAIL;
+	}
+
+	status = gr_tmtc_1553_hw_init(priv);
+	if ( status != 0 ) {
+		genirq_destroy(priv->genirq);
+		free(priv);
+		dev->priv = NULL;
+		printf(" Failed to initialize GR-TMTC-1553 HW: %d\n", status);
+		return DRVMGR_FAIL;
+	}
+
+	/* Init amba bus */
+	priv->config.abus = &priv->abus;
+	priv->config.ops = &ambapp_tmtc_1553_ops;
+	priv->config.maps_down = &priv->bus_maps_down[0];
+	/* This PCI device has only target interface so DMA is not supported,
+	 * which means that translation from AMBA->PCI should fail if attempted.
+	 */
+	priv->config.maps_up = DRVMGR_TRANSLATE_NO_BRIDGE;
+	if ( priv->dev->minor_drv < gr_tmtc_1553_resources_cnt ) {
+		priv->config.resources = gr_tmtc_1553_resources[priv->dev->minor_drv];
+	} else {
+		priv->config.resources = NULL;
+	}
+
+	/* Create And Register AMBA PnP Bus */
+	return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_tmtc_1553_init2(struct drvmgr_dev *dev)
+{
+	struct gr_tmtc_1553_priv *priv = dev->priv;
+
+	/* Clear any old interrupt requests */
+	drvmgr_interrupt_clear(dev, 0);
+
+	/* Enable System IRQ so that GR-TMTC-1553 PCI target interrupt goes through.
+	 *
+	 * It is important to enable it in stage init2. If interrupts were enabled in init1
+	 * this might hang the system when more than one PCI target is connected, this is
+	 * because PCI interrupts might be shared and PCI target 2 have not initialized and
+	 * might therefore drive interrupt already when entering init1().
+	 */
+	drvmgr_interrupt_register(
+		dev,
+		0,
+		"gr_tmtc_1553",
+		gr_tmtc_1553_isr,
+		(void *)priv);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_int_register(
+	struct drvmgr_dev *dev,
+	int irq,
+	const char *info,
+	drvmgr_isr handler,
+	void *arg)
+{
+	struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_register(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Disable and clear IRQ for first registered handler */
+		priv->irq->iclear = (1<<irq);
+		priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	if (status != 0) {
+		rtems_interrupt_enable(level);
+		return DRVMGR_FAIL;
+	}
+
+	status = genirq_enable(priv->genirq, irq, handler, arg);
+	if ( status == 0 ) {
+		/* Enable IRQ for first enabled handler only */
+		priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_tmtc_1553_int_unregister(
+	struct drvmgr_dev *dev,
+	int irq,
+	drvmgr_isr isr,
+	void *arg)
+{
+	struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+	int status;
+
+	rtems_interrupt_disable(level);
+
+	status = genirq_disable(priv->genirq, irq, isr, arg);
+	if ( status == 0 ) {
+		/* Disable IRQ only when no enabled handler exists */
+		priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+	} else if ( status == 1 )
+		status = 0;
+
+	status = genirq_unregister(priv->genirq, irq, isr, arg);
+	if ( status != 0 )
+		status = DRVMGR_FAIL;
+
+	rtems_interrupt_enable(level);
+
+	return status;
+}
+
+int ambapp_tmtc_1553_int_unmask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("TMTC-1553 IRQ %d: enable\n", irq);
+	
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	rtems_interrupt_disable(level);
+
+	/* Enable IRQ */
+	priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_int_mask(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+	rtems_interrupt_level level;
+
+	DBG("TMTC-1553 IRQ %d: disable\n", irq);
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	rtems_interrupt_disable(level);
+
+	/* Disable IRQ */
+	priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+	rtems_interrupt_enable(level);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_int_clear(
+	struct drvmgr_dev *dev,
+	int irq)
+{
+	struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+
+	if ( genirq_check(priv->genirq, irq) )
+		return DRVMGR_FAIL;
+
+	priv->irq->iclear = (1<<irq);
+
+	return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+	struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+
+	/* Device name prefix pointer, skip /dev */
+	params->dev_prefix = &priv->prefix[5];
+
+	return 0;
+}
+
+void gr_tmtc_1553_print_dev(struct drvmgr_dev *dev, int options)
+{
+	struct gr_tmtc_1553_priv *priv = dev->priv;
+	struct pci_dev_info *devinfo = priv->devinfo;
+	uint32_t bar0, bar0_size;
+
+	/* Print */
+	printf("--- GR-TMTC-1553 [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+		PCI_DEV_EXPAND(priv->pcidev));
+
+	bar0 = devinfo->resources[0].address;
+	bar0_size = devinfo->resources[0].size;
+
+	printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+	printf(" IRQ REGS:        0x%x\n", (unsigned int)priv->irq);
+	printf(" IRQ:             %d\n", devinfo->irq);
+	printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
+	printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
+	printf(" IPEND:           0x%08x\n", priv->irq->ipend);
+
+	/* Print amba config */
+	if ( options & TMTC_1553_OPTIONS_AMBA ) {
+		ambapp_print(&priv->abus, 10);
+	}
+#if 0
+	/* Print IRQ handlers and their arguments */
+	if ( options & TMTC_1553_OPTIONS_IRQ ) {
+		int i;
+		for(i=0; i<16; i++) {
+			printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n", 
+				i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+		}
+	}
+#endif
+}
+
+void gr_tmtc_1553_print(int options)
+{
+	struct pci_drv_info *drv = &gr_tmtc_1553_info;
+	struct drvmgr_dev *dev;
+
+	dev = drv->general.dev;
+	while(dev) {
+		gr_tmtc_1553_print_dev(dev, options);
+		dev = dev->next_in_drv;
+	}
+}