diff options
| author | Daniel Hellstrom <daniel@gaisler.com> | 2014-05-29 21:09:00 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-10-09 09:07:22 +0200 |
| commit | fa40ec528874610bff7d1b245f7b3285bbf7c8d4 (patch) | |
| tree | 3232d072137c855f2c95ed463efdc739e1b60dc9 /c/src/lib/libbsp/sparc/shared/irq | |
| parent | bsps/mcf5235: Fix warnings (diff) | |
| download | rtems-fa40ec528874610bff7d1b245f7b3285bbf7c8d4.tar.bz2 | |
SPARC BSPs: added CPU aware interrupt ctrl operations
The LEON2 and ERC32 maps the new macros to CPU0 since they do not
support SMP. With the LEON3 a specific CPU's interrupt controller
registers can be modified using macros.
Diffstat (limited to 'c/src/lib/libbsp/sparc/shared/irq')
0 files changed, 0 insertions, 0 deletions