LEON: replaced old BSP PCI layer with new generic libpci PCI layer

The old code used a limited PCI configuration library, which was
duplicated into LEON2 and LEON3 BSP pci.c together with respective
Host controller PCI interface.

The LEON2 BSP had support for AT697 PCI, and LEON3 for GRPCI PCI
Host controller. With this update new PCI Host drivers are added,
and all support the new generic PCI Library:
 * AT697 PCI (LEON2 only)
 * GRPCI (LEON2-GRLIB and LEON3)
 * GRPCI2 (LEON2-GRLIB and LEON3)
 * Actel PCIF GRLIB Wrapper (LEON3 only)

The LEON2 BSP is defined as big-endian PCI in bsp.h, since the
AT697 supports only big-endian PCI.

1 files changed, 61 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/sparc/shared/include/grpci2.h b/c/src/lib/libbsp/sparc/shared/include/grpci2.h
new file mode 100644
index 0000000000..6316c7abb9
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/grpci2.h
@@ -0,0 +1,61 @@
+/*  GRLIB GRPCI2 PCI HOST driver.
+ * 
+ *  COPYRIGHT (c) 2011
+ *  Cobham Gaisler AB.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GRPCI2_H__
+#define __GRPCI2_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void grpci2_register_drv(void);
+
+/* Driver Resources:
+ *
+ * PCI Interrupts
+ * ==============
+ * The interrupt settings are normally autodetected from Plyg&Play, however
+ * if IRQs are routed using custom GPIO pins in order to reduce the PIN count
+ * reserved for PCI, the options below can be used to tell GRPCI2 driver which
+ * System IRQ a PCI interrupt is connected to.
+ * Name="INTA#", Type=INT, System Interrupt number that PCI INTA is connected to
+ * Name="INTB#", Type=INT, System Interrupt number that PCI INTB is connected to
+ * Name="INTC#", Type=INT, System Interrupt number that PCI INTC is connected to
+ * Name="INTD#", Type=INT, System Interrupt number that PCI INTD is connected to
+ *
+ * Name="IRQmask", Type=INT, 
+ *
+ * PCI Bytetwisting (endianess)
+ * ============================
+ * Name="byteTwisting", Type=INT, Enable/Disable Bytetwisting by hardware
+ *
+ * PCI Host's Target BARs setup
+ * ============================
+ * The Host's BARs are not configured by the configuration routines, by default
+ * the BARs are configured disabled (BAR=0) except for BAR0 which is mapped to
+ * the Main Memory for the Host.
+ * Name="tgtBarCfg", Type=PTR (*grpci2_pcibar_cfg), Target PCI BARs of Host
+ */
+
+/* When the Host acts as a target on the PCI bus, the PCI BARs of the host's
+ * configuration space determine at which PCI address the Host will be accessed
+ * at and when accessing a BAR which AMBA address it will be translated to.
+ */
+struct grpci2_pcibar_cfg {
+	unsigned int pciadr;	/* PCI address of BAR (BAR content) */
+	unsigned int ahbadr;	/* 'pciadr' translated to this AHB Address */
+	unsigned int barsize;	/* PCI BAR Size, must be a power of 2 */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif