diff options
author | Daniel Hellstrom <daniel@gaisler.com> | 2012-05-16 17:20:35 +0200 |
---|---|---|
committer | Gedare Bloom <gedare@rtems.org> | 2012-05-16 13:29:13 -0400 |
commit | 226d48d8262ff040aeca439c22e7398179eb01cd (patch) | |
tree | 931d2a37d49440bd95902f9b367f72f02ea5db2c /c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c | |
parent | nfsclient: Fix symbolic link evaluation (diff) | |
download | rtems-226d48d8262ff040aeca439c22e7398179eb01cd.tar.bz2 |
LEON: moved register definitions into grlib header file
Some register layout definitions for LEON3 reside in ambapp.h which
does not really has anything to do with device registers. The
register structures has been incorrectly named LEON3_*, the cores
are not only used on LEON3 but on LEON4 and perhaps on LEON5 when
that day comes. Some structures has been renamed according to the
GRLIB core name instead, which CPU that actually use it is not
relevant. Drivers has been updated with the new names.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c b/c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c index 7ba7208622..7acf17d1b3 100644 --- a/c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c +++ b/c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c @@ -17,6 +17,7 @@ #include <bsp.h> #include <i2cmst.h> #include <ambapp.h> +#include <grlib.h> #include <rtems/libi2c.h> /* Enable debug printks? */ @@ -318,11 +319,11 @@ rtems_status_code leon_register_i2c(struct ambapp_bus *abus) /* LEON3: find timer address via AMBA Plug&Play info */ { struct ambapp_apb_info gptimer; - LEON3_Timer_Regs_Map *tregs; + struct gptimer_regs *tregs; if (ambapp_find_apbslv(abus, VENDOR_GAISLER, GAISLER_GPTIMER, &gptimer) == 1 ) { - tregs = (LEON3_Timer_Regs_Map *)gptimer.start; + tregs = (struct gptimer_regs *)gptimer.start; gr_i2cmst_desc.prv.sysfreq = (tregs->scaler_reload+1)*1000; } else { gr_i2cmst_desc.prv.sysfreq = 40000; /* Default to 40MHz */ |