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| author | Daniel Hellstrom <daniel@gaisler.com> | 2014-05-29 21:09:00 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-10-09 09:07:22 +0200 |
| commit | fa40ec528874610bff7d1b245f7b3285bbf7c8d4 (patch) | |
| tree | 3232d072137c855f2c95ed463efdc739e1b60dc9 /c/src/lib/libbsp/sparc/erc32 | |
| parent | bsps/mcf5235: Fix warnings (diff) | |
| download | rtems-fa40ec528874610bff7d1b245f7b3285bbf7c8d4.tar.bz2 | |
SPARC BSPs: added CPU aware interrupt ctrl operations
The LEON2 and ERC32 maps the new macros to CPU0 since they do not
support SMP. With the LEON3 a specific CPU's interrupt controller
registers can be modified using macros.
Diffstat (limited to 'c/src/lib/libbsp/sparc/erc32')
| -rw-r--r-- | c/src/lib/libbsp/sparc/erc32/include/erc32.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/sparc/erc32/include/erc32.h b/c/src/lib/libbsp/sparc/erc32/include/erc32.h index f3eb293faa..7db4a6c91b 100644 --- a/c/src/lib/libbsp/sparc/erc32/include/erc32.h +++ b/c/src/lib/libbsp/sparc/erc32/include/erc32.h @@ -405,7 +405,7 @@ static __inline__ int bsp_irq_fixup(int irq) sparc_enable_interrupts( _level ); \ } while (0) -/* Make all SPARC BSPs have common macros for interrupt handling */ +/* Make all SPARC BSPs have common macros for interrupt handling on local CPU */ #define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source) #define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source) #define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source) @@ -417,6 +417,18 @@ static __inline__ int bsp_irq_fixup(int irq) #define BSP_Restore_interrupt(_source, _previous) \ ERC32_Restore_interrupt(_source, _previous) +/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ +#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ + BSP_Is_interrupt_masked(_source) +#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ + BSP_Unmask_interrupt(_source) +#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ + BSP_Mask_interrupt(_source) +#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ + BSP_Disable_interrupt(_source, _prev) +#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ + BSP_Cpu_Restore_interrupt(_source, _previous) + /* * The following macros attempt to hide the fact that the General Purpose * Timer and Real Time Clock Timer share the Timer Control Register. Because |