bsps/sparc: Make lines in SPARC BSPs adhere to 80 character limit.

5 files changed, 34 insertions, 29 deletions

diff --git a/c/src/lib/libbsp/sparc/erc32/configure.ac b/c/src/lib/libbsp/sparc/erc32/configure.ac
index 8155514c39..4cbfb7e3d4 100644
--- a/c/src/lib/libbsp/sparc/erc32/configure.ac
+++ b/c/src/lib/libbsp/sparc/erc32/configure.ac
@@ -1,7 +1,8 @@
 ## Process this file with autoconf to produce a configure script.
 
 AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libbsp-sparc-erc32],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
+AC_INIT([rtems-c-src-lib-libbsp-sparc-erc32],
+[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
 AC_CONFIG_SRCDIR([bsp_specs])
 RTEMS_TOP(../../../../../..)
 
@@ -23,11 +24,11 @@ AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
 RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
 RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
 [The erc32 console driver can operate in either polled or interrupt mode.
-Under the simulator (especially when FAST_UART is defined), polled seems to operate
-better.  It is common for a task to print a line (like the end of test message) and
-then exit.  In this case, the program returns control to the simulator command line
-before the program has even queued the output to the uart.  Thus sis has no chance
-of getting the data out.])
+Under the simulator (especially when FAST_UART is defined), polled seems
+to operate better. It is common for a task to print a line (like the end
+of test message) and then exit.  In this case, the program returns control
+to the simulator command line before the program has even queued the output
+to the uart.  Thus sis has no chance of getting the data out.])
 
 RTEMS_BSPOPTS_SET([SIMSPARC_FAST_IDLE],[*],[])
 RTEMS_BSPOPTS_HELP([SIMSPARC_FAST_IDLE],
diff --git a/c/src/lib/libbsp/sparc/erc32/console/erc32_console.c b/c/src/lib/libbsp/sparc/erc32/console/erc32_console.c
index 4965f2fabc..212d5e0daf 100644
--- a/c/src/lib/libbsp/sparc/erc32/console/erc32_console.c
+++ b/c/src/lib/libbsp/sparc/erc32/console/erc32_console.c
@@ -147,7 +147,8 @@ static int erc32_console_first_open(int major, int minor, void *arg)
 }
 
 #if (CONSOLE_USE_INTERRUPTS)
-static ssize_t erc32_console_write_support_int(int minor, const char *buf, size_t len)
+static ssize_t erc32_console_write_support_int(
+		int minor, const char *buf, size_t len)
 {
   if (len > 0) {
     console_data *cd = &Console_Port_Data[minor];
@@ -155,13 +156,15 @@ static ssize_t erc32_console_write_support_int(int minor, const char *buf, size_
 
     if (minor == 0) { /* uart a */
       for (k = 0;
-           k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA); k ++) {
+           k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA);
+           k ++) {
         ERC32_MEC.UART_Channel_A = (unsigned char)buf[k];
       }
       ERC32_Force_interrupt(ERC32_INTERRUPT_UART_A_RX_TX);
     } else { /* uart b */
       for (k = 0;
-           k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB); k ++) {
+           k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB);
+           k ++) {
         ERC32_MEC.UART_Channel_B = (unsigned char)buf[k];
       }
       ERC32_Force_interrupt(ERC32_INTERRUPT_UART_B_RX_TX);
diff --git a/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c b/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
index 31f81b7c3e..baa39ed8b6 100644
--- a/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
+++ b/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
@@ -98,7 +98,8 @@ sonic_configuration_t erc32_sonic_configuration = {
 int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
 {
 
-  ERC32_MEC.IO_Configuration |= (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
+  ERC32_MEC.IO_Configuration |=
+		  (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
   ERC32_MEC.Control &= ~0x60001; /* Disable DMA time-out, parity & power-down */
   ERC32_MEC.Control |= 0x10000; 		/* Enable DMA */
   ERC32_MEC.Interrupt_Mask &= ~(1 << (SONIC_VECTOR - 0x10));
diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
index 47aefddc8f..b2c1b919c3 100644
--- a/c/src/lib/libbsp/sparc/erc32/include/bsp.h
+++ b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
@@ -98,8 +98,8 @@ void bsp_spurious_initialize( void );
 
 /* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function
  * can be called at any time. The work-area will shrink when called before
- * bsp_work_area_initialize(). malloc() is called to get memory when this function
- * is called after bsp_work_area_initialize().
+ * bsp_work_area_initialize(). malloc() is called to get memory when this
+ * function is called after bsp_work_area_initialize().
  */
 void *bsp_early_malloc(int size);
 
diff --git a/c/src/lib/libbsp/sparc/erc32/include/erc32.h b/c/src/lib/libbsp/sparc/erc32/include/erc32.h
index 5520cdb8d1..f3eb293faa 100644
--- a/c/src/lib/libbsp/sparc/erc32/include/erc32.h
+++ b/c/src/lib/libbsp/sparc/erc32/include/erc32.h
@@ -257,23 +257,23 @@ typedef struct {
  *  The following defines the bits in the Timer Control Register.
  */
 
-#define ERC32_MEC_TIMER_CONTROL_GCR    0x00000001  /* 1 = reload at 0 */
-                                               /* 0 = stop at 0 */
-#define ERC32_MEC_TIMER_CONTROL_GCL    0x00000002  /* 1 = load and start */
-                                               /* 0 = no function */
-#define ERC32_MEC_TIMER_CONTROL_GSE    0x00000004  /* 1 = enable counting */
-                                               /* 0 = hold scalar and counter */
-#define ERC32_MEC_TIMER_CONTROL_GSL    0x00000008  /* 1 = load scalar and start */
-                                               /* 0 = no function */
-
-#define ERC32_MEC_TIMER_CONTROL_RTCCR  0x00000100  /* 1 = reload at 0 */
-                                               /* 0 = stop at 0 */
-#define ERC32_MEC_TIMER_CONTROL_RTCCL  0x00000200  /* 1 = load and start */
-                                               /* 0 = no function */
-#define ERC32_MEC_TIMER_CONTROL_RTCSE  0x00000400  /* 1 = enable counting */
-                                               /* 0 = hold scalar and counter */
-#define ERC32_MEC_TIMER_CONTROL_RTCSL  0x00000800  /* 1 = load scalar and start */
-                                               /* 0 = no function */
+#define ERC32_MEC_TIMER_CONTROL_GCR   0x00000001 /* 1 = reload at 0 */
+                                              /* 0 = stop at 0 */
+#define ERC32_MEC_TIMER_CONTROL_GCL   0x00000002 /* 1 = load and start */
+                                              /* 0 = no function */
+#define ERC32_MEC_TIMER_CONTROL_GSE   0x00000004 /* 1 = enable counting */
+                                              /* 0 = hold scalar and counter */
+#define ERC32_MEC_TIMER_CONTROL_GSL   0x00000008 /* 1 = load scalar and start*/
+                                              /* 0 = no function */
+
+#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
+                                              /* 0 = stop at 0 */
+#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
+                                              /* 0 = no function */
+#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
+                                              /* 0 = hold scalar and counter */
+#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/
+                                              /* 0 = no function */
 
 /*
  *  The following defines the bits in the UART Control Registers.