Virtex5 BSP: Various updates and improvements.

This BSP now uses the MPC6xx clock driver instead of a modified PPC403 clock
driver.  Support for the MMU has been added, but is not enabled by default.

3 files changed, 122 insertions, 94 deletions

diff --git a/c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c b/c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
index 8847dc8b90..4aa89f7bdf 100644
--- a/c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
@@ -54,20 +54,23 @@
  *  Modifications for PPC405GP by Dennis Ehlin
  *  Modifications for Virtex5 by Richard Claus <claus@slac.stanford.edu>
  */
-
-#include <string.h>
-#include <fcntl.h>
-
-#include <bsp.h>
-#include <bsp/irq.h>
-#include <bsp/vectors.h>
+#include <rtems.h>
+#include <rtems/config.h>
 #include <rtems/bspIo.h>
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
-#include <rtems/sptables.h>             /* for RTEMS_VERSION */
+
 #include <libcpu/cpuIdent.h>
 #include <libcpu/spr.h>
 
+#include <bsp.h>
+#include <bsp/vectors.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq.h>
+
+#include <string.h>
+#include <fcntl.h>
+
 #define DO_DOWN_ALIGN(x,a) ((x) & ~((a)-1))
 
 #define DO_UP_ALIGN(x,a)   DO_DOWN_ALIGN(((x) + (a) - 1 ),a)
@@ -76,13 +79,6 @@
 #define CPU_UP_ALIGN(x)    DO_UP_ALIGN(x, CPU_ALIGNMENT)
 
 
-/* Expected by clock.c */
-uint32_t    bsp_clicks_per_usec;
-bool        bsp_timer_internal_clock;   /* true, when timer runs with CPU clk */
-uint32_t    bsp_timer_least_valid;
-uint32_t    bsp_timer_average_overhead;
-
-
 /* Defined in linkcmds linker script */
 LINKER_SYMBOL(RamBase);
 LINKER_SYMBOL(RamSize);
@@ -96,35 +92,37 @@ LINKER_SYMBOL(WorkAreaBase);
 LINKER_SYMBOL(MsgAreaBase);
 LINKER_SYMBOL(MsgAreaSize);
 LINKER_SYMBOL(__phy_ram_end);
+LINKER_SYMBOL(bsp_exc_vector_base);
 
 
+/* Expected by clock.c */
+uint32_t    bsp_clicks_per_usec;
+bool        bsp_timer_internal_clock;   /* true, when timer runs with CPU clk */
+uint32_t    bsp_timer_least_valid;
+uint32_t    bsp_timer_average_overhead;
+
 /*
- * Provide weak aliases so that RTEMS distribution builds
+ * Bus Frequency
  */
-static void _noopfun(void) {}
-static void _bsp_start(void)
-{
-  uintptr_t         intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
-  uintptr_t         intrStackSize  = rtems_configuration_get_interrupt_stack_size();
+unsigned int BSP_bus_frequency;
+/*
+ * processor clock frequency
+ */
+unsigned int BSP_processor_frequency;
 
-  /*
-   * Initialize default raw exception handlers.
-   *
-   * This BSP does not assume anything about firmware possibly loaded in the
-   * FPGA, so the external interrupt should not be enabled in order to avoid
-   * spurious interrupts.
-   */
-  ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT & ~MSR_EE,
-                     intrStackStart,
-                     intrStackSize);
+/*
+ * Time base divisior (bus freq / TB clock)
+ */
+unsigned int BSP_time_base_divisor;
 
-  /* Install our own set of exception vectors */
-  BSP_rtems_irq_mngt_init(0);
-}
+/*
+ * Provide weak aliases so that RTEMS distribution builds
+ */
+static void _noopfun(void) {}
 
 
 void app_bsp_start(void)
-__attribute__(( weak, alias("_bsp_start") ));
+__attribute__(( weak, alias("_noopfun") ));
 
 void app_bsp_pretasking_hook(void)
 __attribute__(( weak, alias("_noopfun") ));
@@ -147,20 +145,31 @@ static void __bsp_outchar_to_memory(char c)
 void BSP_ask_for_reset(void)
 {
   printk("\nSystem stopped, issue RESET");
+
   for(;;);
 }
 
 
 void BSP_panic(char *s)
 {
-  printk("\n%s PANIC %s\n", _RTEMS_version, s);
+  rtems_interrupt_level level;
+
+  rtems_interrupt_disable(level);
+
+  printk("\n%s PANIC %s\n", rtems_get_version_string(), s);
+
   BSP_ask_for_reset();
 }
 
 
 void _BSP_Fatal_error(unsigned int v)
 {
-  printk("\n%s FATAL ERROR %x\n", _RTEMS_version, v);
+  rtems_interrupt_level level;
+
+  rtems_interrupt_disable(level);
+
+  printk("\n%s FATAL ERROR %x\n", rtems_get_version_string(), v);
+
   BSP_ask_for_reset();
 }
 
@@ -176,13 +185,14 @@ void bsp_start(void)
 {
   uintptr_t          intrStackStart;
   uintptr_t          intrStackSize;
+
   ppc_cpu_id_t       myCpu;
   ppc_cpu_revision_t myCpuRevision;
 
   /* Set the character output function;  The application may override this */
   BSP_output_char = __bsp_outchar_to_memory;
 
-  printk("\nWelcome to RTEMS %s\n", _RTEMS_version );
+  printk("RTEMS %s\n", rtems_get_version_string());
 
   /*
    * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
@@ -197,8 +207,13 @@ void bsp_start(void)
    *  Initialize the device driver parameters
    */
 
+  /* For mpc6xx clock driver: */
+  BSP_bus_frequency       = 465000000;
+  BSP_processor_frequency = 465000000;  /* Measured with a DPM 440 2012/8/13 */
+  BSP_time_base_divisor   = 1000;
+
   /* Timebase register ticks/microsecond;  The application may override these */
-  bsp_clicks_per_usec        = 450;
+  bsp_clicks_per_usec        = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
   bsp_timer_internal_clock   = true;
   bsp_timer_average_overhead = 2;
   bsp_timer_least_valid      = 3;
@@ -208,6 +223,12 @@ void bsp_start(void)
    */
   intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
   intrStackSize  = rtems_configuration_get_interrupt_stack_size();
+
+  ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+                     intrStackStart,
+                     intrStackSize);
+
+  /* Let the user know what parameters we were compiled with */
   printk("                  Base/Start     End         Size\n"
          "RAM:              0x%08x              0x%x\n"
          "RTEMS:                        0x%08x\n"
@@ -224,6 +245,11 @@ void bsp_start(void)
          (uint32_t)MsgAreaBase,                           (uint32_t)MsgAreaSize,
          (uint32_t)__phy_ram_end);
 
+  /*
+   * Initialize RTEMS IRQ system
+   */
+  BSP_rtems_irq_mngt_init(0);
+
   /* Continue with application-specific initialization */
   app_bsp_start();
 }
diff --git a/c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds b/c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds
index 20d4095d41..a92d9a1e5e 100644
--- a/c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds
+++ b/c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds
@@ -20,16 +20,17 @@ HeapSize          = DEFINED(HeapSize)      ? HeapSize      : 0; /* 0=Use def */
 
 MEMORY
 {
-  VECTORS         : ORIGIN = 0x00000000, LENGTH = 8K
-  RAM             : ORIGIN = 0x00002000, LENGTH = 2048M - 8K
+  VECTORS         : ORIGIN = 0x00000000, LENGTH = 512
+  RAM             : ORIGIN = 0x00000200, LENGTH = 2048M - 512
 }
 
 
 SECTIONS
 {
-  __exeentry      = download_entry;
-  __exestart      = 0x100;
-  .vectors __exestart : { *(.vectors)                           } > VECTORS
+  bsp_exc_vector_base = 0;
+  __exeentry          = download_entry;
+  __exestart          = bsp_exc_vector_base;
+  .vectors bsp_exc_vector_base : { *(.vectors)                  } > VECTORS
 
   /* Read-only sections, merged into text segment: */
   .interp         : { *(.interp)                                } > RAM
diff --git a/c/src/lib/libbsp/powerpc/virtex5/startup/start.S b/c/src/lib/libbsp/powerpc/virtex5/startup/start.S
index 1afa587ab3..40938e55ab 100644
--- a/c/src/lib/libbsp/powerpc/virtex5/startup/start.S
+++ b/c/src/lib/libbsp/powerpc/virtex5/startup/start.S
@@ -61,6 +61,7 @@
 
 #include <rtems/asm.h>
 #include <rtems/powerpc/powerpc.h>
+#include <rtems/powerpc/registers.h>
 
 #define   V_TS_SZ_I    0x0290      // V,TS=0(Inst),SIZE=9,TID=0
 #define   V_TS_SZ_D    0x0390      // V,TS=1(Data),SIZE=9,TID=0
@@ -154,43 +155,44 @@ first:  li      r0,0              // Clear r0
 
        /*------------------------------------------------------------------
         * Set Core Configuration Register 0 as follows:
-        * sum: 0x00200000
+        * sum: 0x00206000
         * bit  1    off  Parity Recovery Enable
         * bit  4    off  Cache Read Parity Enable
         * bit 10    on   Disable Store Gathering
         * bit 11    off  Disable APU Instruction Broadcast
         * bit 16    off  Disable Trace Broadcast
-        * bit 17:18 off  Specifies behaviour of icbt,dcbt/dcbtst insts
+        * bit 17:18 on   Specifies behaviour of icbt,dcbt/dcbtst insts
         * bit 23    off  Force Load/Store Alignment
         * bit 28:29 off  Instruction Cache Speculative Line Count
         * bit 30:31 off  Instruction Cache Speculative Line Threshold
         *            NB: UG200/pg 21: Spec. prefetching must be disabled
         *------------------------------------------------------------------*/
 
-        lis     r2,0x0020         // 7. Set CCR0: DSTG
-        mtccr0  r2                // Configure CCR0
+        lis     r2,   0x00206000@h // 7. Set CCR0: DSTG
+        ori     r2,r2,0x00206000@l //    Set CCR0: GDCBT, GICBT
+        mtccr0  r2                 // Configure CCR0
 
-        mtspr   ccr1,r0           // 8. Clear CCR1
+        mtspr   PPC440_CCR1,r0     // 8. Clear CCR1
 
        /*------------------------------------------------------------------
 	* 9. Configure cache regions
         *------------------------------------------------------------------*/
-	mtspr   inv0,r0
-	mtspr   inv1,r0
-	mtspr   inv2,r0
-	mtspr   inv3,r0
-	mtspr   dnv0,r0
-	mtspr   dnv1,r0
-	mtspr   dnv2,r0
-	mtspr   dnv3,r0
-	mtspr   itv0,r0
-	mtspr   itv1,r0
-	mtspr   itv2,r0
-	mtspr   itv3,r0
-	mtspr   dtv0,r0
-	mtspr   dtv1,r0
-	mtspr   dtv2,r0
-	mtspr   dtv3,r0
+	mtspr   PPC440_INV0,r0
+	mtspr   PPC440_INV1,r0
+	mtspr   PPC440_INV2,r0
+	mtspr   PPC440_INV3,r0
+	mtspr   PPC440_DNV0,r0
+	mtspr   PPC440_DNV1,r0
+	mtspr   PPC440_DNV2,r0
+	mtspr   PPC440_DNV3,r0
+	mtspr   PPC440_ITV0,r0
+	mtspr   PPC440_ITV1,r0
+	mtspr   PPC440_ITV2,r0
+	mtspr   PPC440_ITV3,r0
+	mtspr   PPC440_DTV0,r0
+	mtspr   PPC440_DTV1,r0
+	mtspr   PPC440_DTV2,r0
+	mtspr   PPC440_DTV3,r0
 
        /*------------------------------------------------------------------
 	* Cache victim limits
@@ -198,8 +200,8 @@ first:  li      r0,0              // Clear r0
         *------------------------------------------------------------------*/
 	lis	r2,   0x0001f800@h
 	ori	r2,r2,0x0001f800@l
-	mtspr   ivlim,r2
-	mtspr   dvlim,r2
+	mtspr   PPC440_IVLIM,r2
+	mtspr   PPC440_DVLIM,r2
 
        /*------------------------------------------------------------------
         * Configure instruction and data cache regions:
@@ -241,7 +243,7 @@ first:  li      r0,0              // Clear r0
         *    31  SR    1     1     Supervisor State Read Enable
         *------------------------------------------------------------------*/
 
-        mtspr   mmucr,r0          // 10a. Clear MMUCR
+        mtspr   PPC440_MMUCR,r0   // 10a. Clear MMUCR
         li      r7,WIMG_U_S_1     // Word 2: Pages are NOT cache inhibited
         lis     r6,   PAGE_SZ@h   // Page size constant
         ori     r6,r6,PAGE_SZ@l
@@ -255,9 +257,9 @@ first:  li      r0,0              // Clear r0
         * Select whether Wait Enable, interrupts/exceptions and which address
         * spaces should be enabled when application starts
         *------------------------------------------------------------------*/
-        lis     r0,   0x00000000@h // 10d. MSR[IS]=0 MSR[DS]=0
-        ori     r0,r0,0x00000000@l
-        mtsrr1  r0
+        lis     r3,   0x00000000@h // 10d. MSR[IS]=0 MSR[DS]=0
+        ori     r3,r3,0x00000000@l
+        mtsrr1  r3
         mtsrr0  r28               // Return address
         rfi                       // Context synchronize to invalidate shadow TLB contents
 
@@ -275,43 +277,43 @@ startupDL:
         * 11. Tell the processor where the exception vector table will be
         *------------------------------------------------------------------*/
         .extern SYM(__vectors)
-        lis     r2, __vectors@h     /* set EVPR exc. vector prefix */
-        mtspr   ivpr,r2
+        lis     r1, __vectors@h     /* set EVPR exc. vector prefix */
+        mtspr   BOOKE_IVPR,r1
 
        /*------------------------------------------------------------------
         * Set up default exception and interrupt vectors
         *------------------------------------------------------------------*/
-        li       r1,0x100
+        li       r1,0
         mtivor0  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor1  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor2  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor3  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor4  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor5  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor6  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor7  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor8  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor9  r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor10 r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor11 r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor12 r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor13 r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor14 r1
-        addi     r1,r1,0x100
+        addi     r1,r1,0x10
         mtivor15 r1
 
        /*------------------------------------------------------------------
@@ -336,16 +338,15 @@ startupDL:
         * 13. Configure timer facilities
         *------------------------------------------------------------------*/
         mtdec   r0                // Clear Decrementer to prevent exception
-        mttbu   r0                // Clear Timebase to prevent Fixed Interval..
-        mttbl   r0                // ..timer and Watchdog Timer exceptions
+        mttbl   r0                // Clear Timebase to prevent Fixed Interval..
+        mttbu   r0                // ..timer and Watchdog Timer exceptions
         mtpit   r0                // Programmable interval timer
-        li      r1,-1             // -1 to clear TSR
-        mttsr   r1                // Timer status register
+        li      r2,-1             // -1 to clear TSR
+        mttsr   r2                // Timer status register
 
        /*-------------------------------------------------------------------
         * Clear out stale values in certain registers to avoid confusion
         *------------------------------------------------------------------*/
-        li      r0,0
         mtcrf   0xff,r0           // Need for simulation
         mtctr   r0                // Counter register
         mtxer   r0                // Fixed-point exception register