diff options
author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-09-23 19:53:38 +0000 |
---|---|---|
committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-09-23 19:53:38 +0000 |
commit | 6067359a1416c83d21de9fd500bc113b9538e430 (patch) | |
tree | 4bef96272d3c5b73caf2d151ec8fca84152e9bec /c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c | |
parent | 2008-09-23 Eric Norum <norume@aps.anl.gov> (diff) | |
download | rtems-6067359a1416c83d21de9fd500bc113b9538e430.tar.bz2 |
make sure cahce is ON when MMU is off (important for exception handling)
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c index 23311ee2aa..5b3ed03cda 100644 --- a/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c @@ -22,6 +22,7 @@ void _InitTQM8xx (void) { register uint32_t r1; + uint32_t msr; /* * Initialize the Instruction Support Control Register (ICTRL) to a @@ -122,12 +123,23 @@ void _InitTQM8xx (void) r1 = 0x00000000; _mtspr( M8xx_TBU_WR, r1 ); _mtspr( M8xx_TBL_WR, r1 ); -} -/* - * further initialization (called from bsp_start) - */ -void cpu_init(void) -{ - /* mmu initialization */ + /* init the MMU */ mmu_init(); + + /* + * override setting from mmu_init: + * make sure the cache is ON(!!!) when the MMU is disabled + * otherwise the exception code will break + */ + r1 = 0x04000e00; + _mtspr( M8xx_MD_CTR, r1 ); + + /* Read MSR */ + msr = ppc_machine_state_register(); + + /* Enable data and instruction MMU in MSR */ + msr |= MSR_DR | MSR_IR; + + /* Update MSR */ + ppc_set_machine_state_register( msr); } |