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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 19:57:02 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 19:57:02 +0000 |
| commit | 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 (patch) | |
| tree | 9253f150814c99167239f7c2cc850cdd9d92c003 /c/src/lib/libbsp/powerpc/support/old_exception_processing | |
| parent | Ensure that when -msoft-float is specified for multilib builds, that (diff) | |
| download | rtems-8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52.tar.bz2 | |
Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
Diffstat (limited to 'c/src/lib/libbsp/powerpc/support/old_exception_processing')
3 files changed, 16 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/Makefile.am b/c/src/lib/libbsp/powerpc/support/old_exception_processing/Makefile.am index 9629808140..92f3fee811 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/Makefile.am +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/Makefile.am @@ -5,7 +5,7 @@ AUTOMAKE_OPTIONS = foreign 1.4 # C source names -C_FILES = cpu.c ppccache.c +C_FILES = cpu.c C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o) ROOT_H_FILES = diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c index 7d6824cb26..5a5fadfd97 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c @@ -50,6 +50,9 @@ static void ppc_spurious(int, CPU_Interrupt_frame *); +int _CPU_spurious_count = 0; +int _CPU_last_spurious = 0; + void _CPU_Initialize( rtems_cpu_table *cpu_table, void (*thread_dispatch) /* ignored on this CPU */ @@ -369,6 +372,8 @@ static void ppc_spurious(int v, CPU_Interrupt_frame *i) "=&r" ((r)) : "0" ((r))); /* TSR */ } #endif + ++_CPU_spurious_count; + _CPU_last_spurious = v; } void _CPU_Fatal_error(unsigned32 _error) @@ -748,7 +753,7 @@ unsigned32 ppc_exception_vector_addr( case PPC_IRQ_LVL7: Offset = 0x23c0; break; - case PPC_IRQ_CPM_RESERVED_0: + case PPC_IRQ_CPM_ERROR: Offset = 0x2400; break; case PPC_IRQ_CPM_PC4: diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.h b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.h index 2a502d0745..30dd6dc092 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.h +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.h @@ -766,6 +766,15 @@ SCORE_EXTERN struct { ); \ } while (0) +#define _CPU_Data_Cache_Block_Invalidate( _address ) \ + do { register void *__address = (_address); \ + register unsigned32 _zero = 0; \ + asm volatile ( "dcbi %0,%1" : \ + "=r" (_zero), "=r" (__address) : \ + "0" (_zero), "1" (__address) \ + ); \ + } while (0) + /* * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |