2007-12-02 Till Straumann <strauman@slac.stanford.edu>

	* shared/openpic/openpic.c shared/openpic/openpic.h,
	shared/irq/irq_init.c: added more parameters to
	openpic_init() so that more details of the configuration
	can be overridden/set from the BSP. Moved setup of
	the EPIC-specific EOI delay from BSP code into openpic_init()
	using the new 'epic_freq' parameter.

1 files changed, 4 insertions, 34 deletions

diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
index 4ba7d6bf2f..47ac343740 100644
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
@@ -270,45 +270,15 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
 #ifdef TRACE_IRQ_INIT
   printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
 #endif
-  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
-  /* Speed up the serial interface; if it is too slow then we might get spurious
-   * interrupts:
-   * After an ISR clears the interrupt condition at the source/device, the wire
-   * remains asserted during the propagation delay introduced by the serial interface
-   * (something really stupid). If the ISR returns while the wire is not released
-   * yet, then a spurious interrupt happens.
-   * The book says we should be careful if the serial clock is > 33MHz.
-   * Empirically, it seems that running it at 33MHz is fast enough. Otherwise,
-   * we should introduce a delay in openpic_eoi().
-   * The maximal delay are 16 (serial) clock cycles. If the divisor is 8
-   * [power-up default] then the lag is 2us [66MHz SDRAM clock; I assume this
-   * is equal to the bus frequency].
-   * FIXME: This should probably be a 8240-specific piece in 'openpic.c'
+  /* EPIC sources don't start at the regular place; define appropriate offset
+   * prior to initializing the PIC.
    */
-  {
-  uint32_t eicr_val, ratio;
-    /* On the 8240 this is the EICR register */
-    eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);
-    if ( (1<<27) & eicr_val ) {
-      /* serial interface mode enabled */
-
-      /* round to nearest integer:
-       *   round(Bus_freq/33000000) = floor( 2*(Bus_freq/33e6) + 1 ) / 2
-       */ 
-      ratio   = BSP_bus_frequency / 16500000 + 1;
-      ratio >>= 2; /* EICR value is half actual divisor */
-      if ( 0==ratio )
-        ratio = 1;
-      out_le32(&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));
-      /*  Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */
-      openpic_set_eoi_delay( 16 * (2*ratio) / 4 );
-    }
-  }
+  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses, 16, 16, BSP_bus_frequency);
 #else
 #ifdef TRACE_IRQ_INIT  
   printk("Going to initialize raven interrupt controller (openpic compliant)\n");
 #endif
-  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
+  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 0, 0);
 #ifdef TRACE_IRQ_INIT  
   printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
 #endif