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authorJoel Sherrill <joel.sherrill@OARcorp.com>2003-02-20 21:32:07 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2003-02-20 21:32:07 +0000
commit4f3e4f33db96df1182c0fb24c987fd9cbed95062 (patch)
tree791e7ffa208a92511c7f899ec4905b8afe24f9c3 /c/src/lib/libbsp/powerpc/shared/irq
parent2003-02-20 Till Straumann <strauman@slac.stanford.edu> (diff)
downloadrtems-4f3e4f33db96df1182c0fb24c987fd9cbed95062.tar.bz2
2003-02-20 Till Straumann <strauman@slac.stanford.edu>
PR 349/bsps * console/console.c, console/uart.c, console/uart.h: implement IOCTLs for the serial (UART) console to install/retrieve a BREAK-IRQ callback. The callback routine (if installed) is invoked from the UART ISR when a BREAK interrupt is detected. This can be used e.g. to enforce a "hotkey" reboot a la vxWorks Ctrl-X (although we use the serial line break condition) NOTE: The callback runs in ISR context.
Diffstat (limited to '')
-rw-r--r--c/src/lib/libbsp/powerpc/shared/irq/irq.c19
-rw-r--r--c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S52
-rw-r--r--c/src/lib/libbsp/powerpc/shared/irq/irq_init.c2
3 files changed, 39 insertions, 34 deletions
diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq.c b/c/src/lib/libbsp/powerpc/shared/irq/irq.c
index d62c29be3d..94c7f72119 100644
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq.c
@@ -14,6 +14,7 @@
#include <rtems/system.h>
#include <bsp.h>
#include <bsp/irq.h>
+#include <bsp/VME.h>
#include <bsp/openpic.h>
#include <rtems/score/thread.h>
#include <rtems/score/apiext.h>
@@ -86,14 +87,14 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
*/
static void compute_i8259_masks_from_prio ()
{
- unsigned int i;
- unsigned int j;
+ int i;
+ int j;
/*
* Always mask at least current interrupt to prevent re-entrance
*/
- for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_NUMBER; i++) {
+ for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
* ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
- for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_NUMBER; j++) {
+ for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
/*
* Mask interrupts at i8259 level that have a lower priority
*/
@@ -261,7 +262,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
*/
compute_i8259_masks_from_prio ();
- for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_NUMBER; i++) {
+ for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
BSP_irq_enable_at_i8259s (i);
rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
@@ -375,10 +376,10 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
}
else {
-#ifdef BSP_PCI_VME_BRIDGE_DOES_EOI
- /* leave it to the VME bridge to do EOI, so
- * it can re-enable the openpic while handling
- * VME interrupts (-> VME priorities in software)
+#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
+ /* leave it to the VME bridge driver to do EOI, so
+ * it can re-enable the openpic while handling
+ * VME interrupts (-> VME priorities in software)
*/
if (BSP_PCI_VME_BRIDGE_IRQ!=irq)
#endif
diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
index 9a44367deb..ad01722742 100644
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
@@ -73,15 +73,19 @@ SYM (shared_raw_irq_code_entry):
* to reenable exception processing
*/
stw r0, GPR0_OFFSET(r1)
+ /* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it
+ * but we still save/restore it, just in case...
+ */
stw r2, GPR2_OFFSET(r1)
stw r3, GPR3_OFFSET(r1)
mfsrr0 r0
- mfsrr1 r2
- mfmsr r3
+ mfsrr1 r3
stw r0, SRR0_FRAME_OFFSET(r1)
- stw r2, SRR1_FRAME_OFFSET(r1)
+ stw r3, SRR1_FRAME_OFFSET(r1)
+
+ mfmsr r3
/*
* Enable data and instruction address translation, exception recovery
*
@@ -137,21 +141,21 @@ SYM (shared_raw_irq_code_entry):
*/
addis r15,0, _Thread_Dispatch_disable_level@ha
/*
- * Get current nesting level in R2
+ * Get current nesting level in R3
*/
- mfspr r2, SPRG0
+ mfspr r3, SPRG0
/*
* Check if stack switch is necessary
*/
- cmpwi r2,0
+ cmpwi r3,0
bne nested
mfspr r1, SPRG1
nested:
/*
- * Start Incrementing nesting level in R2
+ * Start Incrementing nesting level in R3
*/
- addi r2,r2,1
+ addi r3,r3,1
/*
* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
*/
@@ -159,7 +163,7 @@ nested:
/*
* store new nesting level in SPRG0
*/
- mtspr SPRG0, r2
+ mtspr SPRG0, r3
addi r6, r6, 1
mfmsr r5
@@ -183,14 +187,14 @@ nested:
* value as an easy exit condition because if interrupt nesting level > 1
* then _Thread_Dispatch_disable_level > 1
*/
- mfspr r2, SPRG0
+ mfspr r4, SPRG0
/*
* start decrementing _Thread_Dispatch_disable_level
*/
lwz r3,_Thread_Dispatch_disable_level@l(r15)
- addi r2, r2, -1 /* Continue decrementing nesting level */
+ addi r4, r4, -1 /* Continue decrementing nesting level */
addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
- mtspr SPRG0, r2 /* End decrementing nesting level */
+ mtspr SPRG0, r4 /* End decrementing nesting level */
stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
cmpwi r3, 0
/*
@@ -222,14 +226,14 @@ nested:
*/
stmw r16, GPR16_OFFSET(r1)
addi r3, r1, 0x8
- /*
- * compute SP at exception entry
- */
- addi r2, r1, EXCEPTION_FRAME_END
- /*
- * store it at the right place
- */
- stw r2, GPR1_OFFSET(r1)
+ /*
+ * compute SP at exception entry
+ */
+ addi r4, r1, EXCEPTION_FRAME_END
+ /*
+ * store it at the right place
+ */
+ stw r4, GPR1_OFFSET(r1)
/*
* Call High Level signal handling code
*/
@@ -314,14 +318,14 @@ easy_exit:
*/
lwz r4, SRR1_FRAME_OFFSET(r1)
- lwz r2, SRR0_FRAME_OFFSET(r1)
- lwz r3, GPR3_OFFSET(r1)
+ lwz r3, SRR0_FRAME_OFFSET(r1)
+ lwz r2, GPR2_OFFSET(r1)
lwz r0, GPR0_OFFSET(r1)
mtsrr1 r4
- mtsrr0 r2
+ mtsrr0 r3
lwz r4, GPR4_OFFSET(r1)
- lwz r2, GPR2_OFFSET(r1)
+ lwz r3, GPR3_OFFSET(r1)
addi r1,r1, EXCEPTION_FRAME_END
SYNC
rfi
diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
index 72065be0ed..4ae88cc8b7 100644
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
@@ -237,7 +237,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
#ifdef TRACE_IRQ_INIT
printk("Going to initialize raven interrupt controller (openpic compliant)\n");
#endif
- openpic_init(1, mcp750_openpic_initsenses, mcp750_openpic_initpolarities);
+ openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
#ifdef TRACE_IRQ_INIT
printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
#endif