diff options
| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-15 14:21:20 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-16 08:58:49 -0500 |
| commit | d4ab6611f3a809b7a177c3e4340f346f288588b7 (patch) | |
| tree | 3e22f747e1792b63edde4507815a2e81051f5dc4 /c/src/lib/libbsp/powerpc/score603e | |
| parent | SH libcpu and libbsp: Fix warnings (diff) | |
| download | rtems-d4ab6611f3a809b7a177c3e4340f346f288588b7.tar.bz2 | |
powerpc/score603e: Fix warnings
Diffstat (limited to 'c/src/lib/libbsp/powerpc/score603e')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c | 14 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c | 2 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c | 23 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/console/console.c | 40 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/cscope.out | 11129 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/bsp.h | 88 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c | 11 |
7 files changed, 11197 insertions, 110 deletions
diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c index 817037e6dc..999ab9390c 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c @@ -1,6 +1,5 @@ /* - * - * COPYRIGHT (c) 1989-2009. + * COPYRIGHT (c) 1989-2014. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -25,10 +24,10 @@ * an UNIVERSE register, without sufficient delay, the second access will * not work correctly. */ -void PCI_bus_delay (void) +static void PCI_bus_delay (void) { - __asm__ (" nop"); - __asm__ (" nop"); + __asm__ volatile ("nop"); + __asm__ volatile ("nop"); } /* @@ -43,7 +42,7 @@ void PCI_bus_write( *_addr = _data; } -uint32_t PCI_bus_read( +uint32_t PCI_bus_read( volatile uint32_t * _addr /* IN */ ) { @@ -57,8 +56,7 @@ uint32_t PCI_bus_read( * PCI Configuration Cycle Read/Write Access which is used to access all of * devices registers on the PCI bus. i.e.: Universe, Ethernet & PMC. */ - -uint32_t Read_pci_device_register( +uint32_t Read_pci_device_register( uint32_t address ) { diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c index c50c09b0af..a2e084a45d 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c @@ -60,6 +60,7 @@ unsigned int SCORE603e_FLASH_verify_enable( void ) return RTEMS_SUCCESSFUL; } +#if 0 unsigned int SCORE603e_FLASH_pci_reset_reg( uint8_t reg, uint32_t cmask, @@ -79,6 +80,7 @@ unsigned int SCORE603e_FLASH_pci_reset_reg( } return RTEMS_SUCCESSFUL; } +#endif /* * SCORE603e_FLASH_Enable_writes diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c index a1011daff8..c373aa6955 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @@ -16,22 +16,6 @@ #include <bsp.h> #include "PCI.h" -/******************************************************************** - ******************************************************************** - ********* ********* - ********* Prototypes ********* - ********* ********* - ******************************************************************** - ********************************************************************/ - -/******************************************************************** - ******************************************************************** - ********* ********* - ********* ********* - ********* ********* - ******************************************************************** - ********************************************************************/ - typedef struct { uint32_t PCI_ID; /* 0x80030000 */ uint32_t PCI_CSR; /* 0x80030004 */ @@ -153,7 +137,6 @@ volatile Universe_Memory *UNIVERSE = * by the boot code. This routine should be called by user code only if * a complete SCORE603e VME initialization is required. */ - void initialize_universe(void) { uint32_t jumper_selection; @@ -227,7 +210,7 @@ void set_vme_base_address ( /* * Gets the VME base address */ -uint32_t get_vme_base_address (void) +static uint32_t get_vme_base_address (void) { volatile uint32_t temp; @@ -236,7 +219,7 @@ uint32_t get_vme_base_address (void) return (temp); } -uint32_t get_vme_slave_size(void) +uint32_t get_vme_slave_size(void) { volatile uint32_t temp; temp = PCI_bus_read( &UNIVERSE->VSI0_BD); @@ -249,7 +232,7 @@ uint32_t get_vme_slave_size(void) * Set the size of the VME slave image * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) */ -void set_vme_slave_size (uint32_t size) +void set_vme_slave_size (uint32_t size) { volatile uint32_t temp; diff --git a/c/src/lib/libbsp/powerpc/score603e/console/console.c b/c/src/lib/libbsp/powerpc/score603e/console/console.c index 5ae61ea9db..afbc5b4fbb 100644 --- a/c/src/lib/libbsp/powerpc/score603e/console/console.c +++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c @@ -4,8 +4,10 @@ * This driver uses the termios pseudo driver. * * Currently only polled mode is supported. - * - * COPYRIGHT (c) 1989-2009. + */ + +/* + * COPYRIGHT (c) 1989-2014. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -36,14 +38,12 @@ int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF; * Console Device Driver Entry Points */ -/* PAGE - * +/* * console_inbyte_nonblocking * * Console Termios polling input entry point. */ - -int console_inbyte_nonblocking( +static int console_inbyte_nonblocking( int minor ) { @@ -164,8 +164,7 @@ void console_outbyte_interrupts( #endif -/* PAGE - * +/* * console_initialize * * Routine called to initialize the console device driver. @@ -178,7 +177,7 @@ rtems_device_driver console_initialize( { rtems_status_code status; rtems_device_minor_number console; - int port, chip, p0,p1; + int port, p0,p1; /* * initialize the termio interface. @@ -234,7 +233,6 @@ rtems_device_driver console_initialize( */ for (port=1; port<NUM_Z85C30_PORTS; port++) { - chip = port >> 1; initialize_85c30_port( &Ports_85C30[port] ); } @@ -245,14 +243,13 @@ rtems_device_driver console_initialize( return RTEMS_SUCCESSFUL; } -/* PAGE - * +/* * console_write_support * * Console Termios output entry point. * */ -ssize_t console_write_support( +static ssize_t console_write_support( int minor, const char *buf, size_t len) @@ -289,12 +286,10 @@ ssize_t console_write_support( return nwrite; } -/* PAGE - * +/* * console_open * * open a port as a termios console. - * */ rtems_device_driver console_open( rtems_device_major_number major, @@ -354,19 +349,10 @@ rtems_device_driver console_open( } #if (CONSOLE_USE_INTERRUPTS) - /* * console_outbyte_interrupts * * This routine transmits a character out. - * - * Input parameters: - * port - port to transmit character to - * ch - character to be transmitted - * - * Output parameters: NONE - * - * Return values: NONE */ void console_outbyte_interrupts( const Port_85C30_info *Port, @@ -396,12 +382,10 @@ void console_outbyte_interrupts( Ring_buffer_Add_character( &protocol->TX_Buffer, ch ); } - #endif /* const char arg to be compatible with BSP_output_char decl. */ -void -debug_putc_onlcr(const char c) +static void debug_putc_onlcr(const char c) { int console; volatile uint8_t *csr; diff --git a/c/src/lib/libbsp/powerpc/score603e/cscope.out b/c/src/lib/libbsp/powerpc/score603e/cscope.out new file mode 100644 index 0000000000..bb15e454a0 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/cscope.out @@ -0,0 +1,11129 @@ +cscope 15 $HOME/rtems-4.11-work/rtems/c/src/lib/libbsp/powerpc/score603e 0000068551 + @PCI_bus/PCI.c + +10 + ~<ems.h +> + +11 + ~<as.h +> + +12 + ~<dio.h +> + +14 + ~<b.h +> + +27 + $PCI_bus_day + ( ) + +29 +__asm__ + volatile ("nop"); + +30 +__asm__ + volatile ("nop"); + +31 + } +} + +36 + $PCI_bus_wre +( + +37 vީ +ut32_t + * +_addr +, + +38 +ut32_t + +_da + + +41 +_da + = + `Cvt_Endn_32 +( _data ); + +42 * +_addr + = +_da +; + +43 + } +} + +45 +ut32_t + + $PCI_bus_ad +( + +46 vީ +ut32_t + * +_addr + + +49 +ut32_t + +da +; + +51 +da + = * +_addr +; + +52 +da + = + `Cvt_Endn_32 +( data ); + +53 +da +; + +54 + } +} + +59 +ut32_t + + $Rd_pci_devi_gi +( + +60 +ut32_t + +addss + + +63 +ut32_t + +da +; + +68 + `PCI_bus_wre +(vީ +ut32_t +*) +SCORE603E_PCI_IO_CFG_ADDR +, +addss + ); + +73 + `PCI_bus_day + (); + +78 +da + = + `PCI_bus_ad +(vީ +ut32_t +*) +SCORE603E_PCI_IO_CFG_DATA + ); + +80 +da +; + +81 + } +} + +83 + $Wre_pci_devi_gi +( + +84 +ut32_t + +addss +, + +85 +ut32_t + +da + + +91 + `PCI_bus_wre +(vީ +ut32_t +*) +SCORE603E_PCI_IO_CFG_ADDR +, +addss + ); + +96 + `PCI_bus_day + (); + +101 + `PCI_bus_wre +(vީ +ut32_t +*) +SCORE603E_PCI_IO_CFG_DATA +, +da + ); + +102 + } +} + + @PCI_bus/PCI.h + +17 #ide +__PCI_h + + +18 + #__PCI_h + + + ) + +24 +PCI_bus_wre +( + +25 vީ +ut32_t + * +_addr +, + +26 +ut32_t + +_da + + +29 +ut32_t + +PCI_bus_ad +( + +30 vީ +ut32_t + * +_addr + + +33 +ut32_t + +Rd_pci_devi_gi +( + +34 +ut32_t + +addss + + +37 +Wre_pci_devi_gi +( + +38 +ut32_t + +addss +, + +39 +ut32_t + +da + + + @PCI_bus/flash.c + +10 + ~<ems.h +> + +11 + ~<as.h +> + +12 + ~<dio.h +> + +13 + ~<ys.h +> + +15 + ~<b.h +> + +16 + ~<b/q.h +> + +17 + ~"PCI.h +" + +22 + $SCORE603e_FLASH_Dib +( + +23 +ut32_t + + + + +26 +ut8_t + +vue +; + +28 +vue + = * +SCORE603E_BOARD_CTRL_REG +; + +29 +vue + = vu| (~ +SCORE603E_BRD_FLASH_DISABLE_MASK +); + +30 * +SCORE603E_BOARD_CTRL_REG + = +vue +; + +32 +RTEMS_SUCCESSFUL +; + +33 + } +} + +35 + $SCORE603e_FLASH_vify_ab +( ) + +37 vީ +ut8_t + * +Cl_Stus_Regi + = + +38 ( *) +SCORE603E_BOARD_CTRL_REG +; + +39 +ut8_t + +_vue +; + +40 +ut32_t + +pci_vue +; + +42 +_vue + = * +Cl_Stus_Regi +; + +43 i +_vue + & +SCORE603E_BRD_FLASH_DISABLE_MASK + ) { + +44 + `tf + ("Flash Writes Disabled by board controlegister %x\n", + +45 +_vue + ); + +46 + `as +( 0x0 ); + +49 +pci_vue + = + `Rd_pci_devi_gi +( 0x800000A8 ); + +50 i( +pci_vue + & 0x00001000 ) == 0) { + +51 + `tf +("Error PCI A8 \n"); + +52 + `as +( 0x0 ); + +55 +pci_vue + = + `Rd_pci_devi_gi +( 0x800000AC ); + +56 i +pci_vue + & 0x02000000) { + +57 + `tf +("Error PCI AC \n"); + +58 + `as +( 0x0 ); + +60 +RTEMS_SUCCESSFUL +; + +61 + } +} + +64 + $SCORE603e_FLASH_pci_t_g +( + +65 +ut8_t + +g +, + +66 +ut32_t + +cmask +, + +67 +ut32_t + +mask + + +70 +ut32_t + +pci_vue +; + +71 +ut32_t + +vue +; + +73 +pci_vue + = + `Rd_pci_devi_gi + +g + ); + +74 +pci_vue + & +cmask +; + +75 +pci_vue + | +mask +; + +76 + `Wre_pci_devi_gi + +g +, +pci_vue + ); + +77 +vue + = + `Rd_pci_devi_gi + +g + ); + +78 i( +vue + ! +pci_vue +) { + +79 + `tf +("E PCI 0x%2" +PRIX8 +" wrِ0x%8" +PRIX32 +"d %8"PRIX32"\n", +g +, +pci_vue +, +vue +); + +81 +RTEMS_SUCCESSFUL +; + +82 + } +} + +88 + $SCORE603e_FLASH_Eb_wres +( + +89 +ut32_t + + + + +92 +ut8_t + +_vue +; + +93 +ut32_t + +pci_vue +; + +95 +_vue + = * +SCORE603E_BOARD_CTRL_REG +; + +96 +_vue + = ctrl_value & 0xbf; + +97 * +SCORE603E_BOARD_CTRL_REG + = +_vue +; + +99 +pci_vue + = + `Rd_pci_devi_gi +( 0x800000A8 ); + +100 +pci_vue + |= 0x00001000; + +101 + `Wre_pci_devi_gi +0x800000A8, +pci_vue + ); + +103 +pci_vue + = + `Rd_pci_devi_gi +( 0x800000AC ); + +104 +pci_vue + &= (~0x02000000); + +105 + `Wre_pci_devi_gi +0x000000AC, +pci_vue + ); + +107 +RTEMS_SUCCESSFUL +; + +108 + } +} + + @PCI_bus/universe.c + +10 + ~<ems.h +> + +11 + ~<as.h +> + +12 + ~<dio.h +> + +13 + ~<ys.h +> + +14 + ~<ems/bIo.h +> + +16 + ~<b.h +> + +17 + ~"PCI.h +" + +20 +ut32_t + + mPCI_ID +; + +21 +ut32_t + + mPCI_CSR +; + +22 +ut32_t + + mPCI_CLASS +; + +23 +ut32_t + + mPCI_MISC0 +; + +24 +ut32_t + + mPCI_BS +; + +25 +ut32_t + + mBuf_0x80030014 +[ 0x0A ]; + +26 +ut32_t + + mPCI_MISC1 +; + +27 +ut32_t + + mBuf_0x80030040 +[ 0x30 ]; + +28 +ut32_t + + mLSI0_CTL +; + +29 +ut32_t + + mLSI0_BS +; + +30 +ut32_t + + mLSI0_BD +; + +31 +ut32_t + + mLSI0_TO +; + +32 +ut32_t + + mBuf_0x80030110 +; + +33 +ut32_t + + mLSI1_CTL +; + +34 +ut32_t + + mLSI1_BS +; + +35 +ut32_t + + mLSI1_BD +; + +36 +ut32_t + + mLSI1_TO +; + +37 +ut32_t + + mBuf_0x80030124 +; + +38 +ut32_t + + mLSI2_CTL +; + +39 +ut32_t + + mLSI2_BS +; + +40 +ut32_t + + mLSI2_BD +; + +41 +ut32_t + + mLSI2_TO +; + +42 +ut32_t + + mBuf_0x80030138 +; + +43 +ut32_t + + mLSI3_CTL +; + +44 +ut32_t + + mLSI3_BS +; + +45 +ut32_t + + mLSI3_BD +; + +46 +ut32_t + + mLSI3_TO +; + +47 +ut32_t + + mBuf_0x8003014C +[ 0x09 ]; + +48 +ut32_t + + mSCYC_CTL +; + +49 +ut32_t + + mSCYC_ADDR +; + +50 +ut32_t + + mSCYC_EN +; + +51 +ut32_t + + mSCYC_CMP +; + +52 +ut32_t + + mSCYC_SWP +; + +53 +ut32_t + + mLMISC +; + +54 +ut32_t + + mSLSI +; + +55 +ut32_t + + mL_CMDERR +; + +56 +ut32_t + + mLAERR +; + +57 +ut32_t + + mBuf_0x80030194 +[ 0x1B ]; + +58 +ut32_t + + mDCTL +; + +59 +ut32_t + + mDTBC +; + +60 +ut32_t + + mDLA +; + +61 +ut32_t + + mBuf_0x8003020C +; + +62 +ut32_t + + mDVA +; + +63 +ut32_t + + mBuf_0x80030214 +; + +64 +ut32_t + + mDCPP +; + +65 +ut32_t + + mBuf_0x8003021C +; + +66 +ut32_t + + mDGCS +; + +67 +ut32_t + + mD_LLUE +; + +68 +ut32_t + + mBuf_0x80030228 +[ 0x36 ]; + +69 +ut32_t + + mLINT_EN +; + +70 +ut32_t + + mLINT_STAT +; + +71 +ut32_t + + mLINT_MAP0 +; + +72 +ut32_t + + mLINT_MAP1 +; + +73 +ut32_t + + mVINT_EN +; + +74 +ut32_t + + mVINT_STAT +; + +75 +ut32_t + + mVINT_MAP0 +; + +76 +ut32_t + + mVINT_MAP1 +; + +77 +ut32_t + + mSTATID +; + +78 +ut32_t + + mV1_STATID +; + +79 +ut32_t + + mV2_STATID +; + +80 +ut32_t + + mV3_STATID +; + +81 +ut32_t + + mV4_STATID +; + +82 +ut32_t + + mV5_STATID +; + +83 +ut32_t + + mV6_STATID +; + +84 +ut32_t + + mV7_STATID +; + +85 +ut32_t + + mBuf_0x80030340 +[ 0x30 ]; + +86 +ut32_t + + mMAST_CTL +; + +87 +ut32_t + + mMISC_CTL +; + +88 +ut32_t + + mMISC_STAT +; + +89 +ut32_t + + mUSER_AM +; + +90 +ut32_t + + mBuf_0x80030410 +[ 0x2bc ]; + +91 +ut32_t + + mVSI0_CTL +; + +92 +ut32_t + + mVSI0_BS +; + +93 +ut32_t + + mVSI0_BD +; + +94 +ut32_t + + mVSI0_TO +; + +95 +ut32_t + + mBuf_0x80030f10 +; + +96 +ut32_t + + mVSI1_CTL +; + +97 +ut32_t + + mVSI1_BS +; + +98 +ut32_t + + mVSI1_BD +; + +99 +ut32_t + + mVSI1_TO +; + +100 +ut32_t + + mBuf_0x80030F24 +; + +101 +ut32_t + + mVSI2_CTL +; + +102 +ut32_t + + mVSI2_BS +; + +103 +ut32_t + + mVSI2_BD +; + +104 +ut32_t + + mVSI2_TO +; + +105 +ut32_t + + mBuf_0x80030F38 +; + +106 +ut32_t + + mVSI3_CTL +; + +107 +ut32_t + + mVSI3_BS +; + +108 +ut32_t + + mVSI3_BD +; + +109 +ut32_t + + mVSI3_TO +; + +110 +ut32_t + + mBuf_0x80030F4C +[ 0x9 ]; + +111 +ut32_t + + mVRAI_CTL +; + +112 +ut32_t + + mVRAI_BS +; + +113 +ut32_t + + mBuf_0x80030F78 +[ 0x2 ]; + +114 +ut32_t + + mVCSR_CTL +; + +115 +ut32_t + + mVCSR_TO +; + +116 +ut32_t + + mV_AMERR +; + +117 +ut32_t + + mVAERR +; + +118 +ut32_t + + mBuf_0x80030F90 +[ 0x19 ]; + +119 +ut32_t + + mVCSR_CLR +; + +120 +ut32_t + + mVCSR_SET +; + +121 +ut32_t + + mVCSR_BS +; + +122 } + tUniv_Memy +; + +124 vީ +Univ_Memy + * + gUNIVERSE + = + +125 (vީ +Univ_Memy + *) +SCORE603E_UNIVERSE_BASE +; + +140 + $lize_univ +( ) + +142 +ut32_t + +jumr_i +; + +143 +ut32_t + +pci_id +; + +148 +jumr_i + = + `PCI_bus_ad +( + +149 (vީ +ut32_t +*) +SCORE603E_VME_JUMPER_ADDR + ); + +150 + `tk +("initialize_universe: Read 0x%x = 0x%x\n", + +151 +SCORE603E_VME_JUMPER_ADDR +, +jumr_i +); + +152 +jumr_i + = (jumper_selection >> 3) & 0x1f; + +157 +pci_id + = + `Rd_pci_devi_gi + +SCORE603E_IO_VME_UNIVERSE_BASE + ); + +162 i( +pci_id + ! +SCORE603E_UNIVERSE_CHIP_ID + ){ + +163 + `tk + ("Invid SCORE603E_UNIVERSE_CHIP_ID: 0x08%" +PRId32 + "\n", +pci_id +); + +164 + `ems_l_r_occued +( 0x603e0bad ); + +166 + `tk +("initialize_universe: Reg 0x%xead 0x%x\n", + +167 +SCORE603E_IO_VME_UNIVERSE_BASE +, +pci_id + ); + +173 + } +} + +180 + $t_vme_ba_addss + ( + +181 +ut32_t + +ba_addss + + +184 vީ +ut32_t + +mp +; + +189 +mp + = ( + `PCI_bus_ad +& +UNIVERSE +-> +VSI0_BD +) & 0xFFFFF000) - + +190 + `PCI_bus_ad +& +UNIVERSE +-> +VSI0_BS +) & 0xFFFFF000); + +196 + `PCI_bus_wre +& +UNIVERSE +-> +VSI0_BS +, ( +ba_addss + & 0xFFFFF000) ); + +201 + `PCI_bus_wre +& +UNIVERSE +-> +VSI0_BD +, +mp + ); + +206 +mp + = 0xFFFFFFFF - ( +ba_addss + & 0xFFFFF000) + 1 + 0x80000000; + +207 + `PCI_bus_wre +& +UNIVERSE +-> +VSI0_TO +, +mp + ); + +208 + } +} + +213 +ut32_t + + $g_vme_ba_addss + ( ) + +215 vީ +ut32_t + +mp +; + +217 +mp + = + `PCI_bus_ad +& +UNIVERSE +-> +VSI0_BS + ); + +218 +mp + &= 0xFFFFF000; + +219 ( +mp +); + +220 + } +} + +222 +ut32_t + + $g_vme_ave_size +( ) + +224 vީ +ut32_t + +mp +; + +225 +mp + = + `PCI_bus_ad +& +UNIVERSE +-> +VSI0_BD +); + +226 +mp + &= 0xFFFFF000; + +227 +mp + =em- + `g_vme_ba_addss + (); + +228 +mp +; + +229 + } +} + +235 + $t_vme_ave_size + ( +ut32_t + +size +) + +237 vީ +ut32_t + +mp +; + +239 i( +size +<0) + +240 +size + = 0; + +242 i( +size + > 0x17FFFFF) + +243 +size + = 0x17FFFFF; + +248 +mp + = + `g_vme_ba_addss + (); + +253 +mp + =em+ ( +size + & 0xFFFFF000); + +254 + `PCI_bus_wre +& +UNIVERSE +-> +VSI0_BD +, +mp + ); + +255 + } +} + + @console/85c30.c + +17 + ~<ems.h +> + +18 + ~<b.h +> + +19 + ~<ems/libio.h +> + +20 + ~<as.h +> + +22 + ~"85c30.h +" + +23 + ~"cseb.h +" + +25 + #STATUS_REGISTER + 0x00 + + ) + +26 + #DATA_REGISTER + 0x08 + + ) + +28 + #Z8530_Stus_Is_RX_cha_avaab + +_us + ) \ + +29 ( +_us +& 0x01 ) + + ) + +31 + #Z8530_Stus_Is_TX_bufr_emy + +_us + ) \ + +32 ( +_us +& 0x04 ) + + ) + +34 + #Z8530_Stus_Is_bak_abt + +_us + ) \ + +35 ( +_us +& 0x80 ) + + ) + +38 + mad_tup +; + +39 + mwre_tup +; + +40 + mmask_vue +; + +41 } + tch_size_fo +; + +43 cڡ +ch_size_fo + + gCh_size_85c30 +[] = { + +44 { +Z8530_READ_CHARACTER_BITS_8 +, +Z8530_WRITE_CHARACTER_BITS_8 +, 0xFF }, + +45 { +Z8530_READ_CHARACTER_BITS_7 +, +Z8530_WRITE_CHARACTER_BITS_7 +, 0x7F }, + +46 { +Z8530_READ_CHARACTER_BITS_6 +, +Z8530_WRITE_CHARACTER_BITS_6 +, 0x3F }, + +47 { +Z8530_READ_CHARACTER_BITS_5 +, +Z8530_WRITE_CHARACTER_BITS_5 +, 0x1F } + +50 cڡ + gClock_d_85c30 +[] = { + +51 +Z8530_x1_CLOCK +, +Z8530_x16_CLOCK +, +Z8530_x32_CLOCK +, +Z8530_x64_CLOCK + }; + +53 cڡ + gSt_b_85c30 +[] = { + +54 +Z8530_STOP_BITS_1 +, +Z8530_STOP_BITS_1_AND_A_HALF +, +Z8530_STOP_BITS_2 + }; + +56 cڡ + gPy_85c30 +[] = { + +57 +Z8530_PARITY_NONE +, +Z8530_PARITY_ODD +, +Z8530_PARITY_EVEN + }; + +65 + $Rd_85c30_gi +( + +66 vީ * +c +, + +67 +gi_numb + + +70 +Da +; + +72 * +c + = +gi_numb +; + +74 + `ems_b_day__bus_cyes +( 40 ); + +76 +Da + = * +c +; + +78 + `ems_b_day__bus_cyes +( 40 ); + +80 +Da +; + +81 + } +} + +88 + $Wre_85c30_gi +( + +89 vީ * +c +, + +90 +gi_numb +, + +91 +da + + +94 * +c + = +gi_numb +; + +96 + `ems_b_day__bus_cyes +( 40 ); + +97 * +c + = +da +; + +98 + `ems_b_day__bus_cyes +( 40 ); + +99 + } +} + +108 + $Ret_85c30_ch +( + +109 vީ * +_0 +, + +110 vީ * +_1 + + +113 + `Wre_85c30_gi + +_0 +, 0x09, 0x80 ); + +114 + `Wre_85c30_gi + +_1 +, 0x09, 0x40 ); + +115 + } +} + +123 + $lize_85c30_pt +( + +124 cڡ +Pt_85C30_fo + * +Pt + + +127 +ut16_t + +vue +; + +128 vީ * + +; + +129 +Cse_Proc + * +Sup +; + +130 +ut16_t + +baud_cڡt +; + +132 +Sup + = +Pt +-> +Proc +; + +133 + + = +Pt +->ctrl; + +135 +baud_cڡt + = + `_Sce603e_Z8530_Baud + +Pt +-> +Ch +-> +ock_equcy +, + +136 +Pt +-> +Ch +-> +ock_x +, +Sup +-> +baud_ + ); + +142 +vue + = +Clock_d_85c30 +[ +Pt +-> +Ch +-> +ock_d + ] | + +143 +St_b_85c30 +[ +Sup +-> +_bs + ] | + +144 +Py_85c30 +[ +Sup +-> +ry + ]; + +145 + `Wre_85c30_gi + + +, 0x04, +vue + ); + +150 + `Wre_85c30_gi + + +, 1, 0 ); + +152 #i +CONSOLE_USE_INTERRUPTS + + +156 + `Wre_85c30_gi + + +, 2, +Pt +-> +Ch +-> +ve + ); + +162 + `Wre_85c30_gi + + +, 0x03, 0x00 ); + +167 + `Wre_85c30_gi + + +, 5, 0x00 ); + +176 + `Wre_85c30_gi + + +, 9, 0x00 ); + +181 + `Wre_85c30_gi + + +, 0x0a, 0x00 ); + +188 + `Wre_85c30_gi + + +, 0x0b, 0x56 ); + +190 +vue + = +baud_cڡt +; + +197 + `Wre_85c30_gi + + +, 0x0c, +vue + & 0xff ); + +203 + `Wre_85c30_gi + + +, 0x0d, +vue +>>8 ); + +211 + `Wre_85c30_gi + + +, 0x0e, 0x07 ); + +223 +vue + = 0x01; + +224 +vue + = vu| +Ch_size_85c30 +[ +Sup +-> +ad_ch_bs + ]. +ad_tup +; + +226 + `Wre_85c30_gi + + +, 0x03, +vue + ); + +238 +vue + = 0x8a; + +239 +vue + = vu| +Ch_size_85c30 +[ +Sup +-> +wre_ch_bs + ]. +wre_tup +; + +240 + `Wre_85c30_gi + + +, 0x05, +vue + ); + +246 + `Wre_85c30_gi + + +, 0x00, 0xf0 ); + +248 #i +CONSOLE_USE_INTERRUPTS + + +252 + `Wre_85c30_gi + + +, 1, 0x10 ); + +259 + `Wre_85c30_gi + + +, 15, 0x00 ); + +264 + `Wre_85c30_gi + + +, 0x00, 0x10 ); + +266 #i +CONSOLE_USE_INTERRUPTS + + +274 + `Wre_85c30_gi + + +, 1, 0x16 ); + +280 + `Wre_85c30_gi + + +, 9, 0x0A ); + +287 + `Wre_85c30_gi + +Pt +-> + +, +STATUS_REGISTER +, 0x38 ); + +291 + } +} + +300 + $outby_pd_85c30 +( + +301 vީ * +c +, + +302 +ch + + +305 +z8530_us +; + +306 +ut32_t + +iv +; + +308 + `ems_u_dib + +iv + ); + +314 +z8530_us + = + `Rd_85c30_gi + +c +, +STATUS_REGISTER + ); + +315 } ! + `Z8530_Stus_Is_TX_bufr_emy + +z8530_us + ) ); + +320 + `Wre_85c30_gi + +c +, +DATA_REGISTER +, ( +ch + ); + +322 + `ems_u_ab + +iv + ); + +323 + } +} + +332 + $by_nblockg_85c30 +( + +333 cڡ +Pt_85C30_fo + * +Pt + + +336 vީ * +c +; + +337 +z8530_us +; + +338 +ut8_t + +da +; + +340 +c + = +Pt +-> + +; + +345 +z8530_us + = + `Rd_85c30_gi + +c +, +STATUS_REGISTER + ); + +346 i! + `Z8530_Stus_Is_RX_cha_avaab + +z8530_us + ) ) + +352 +da + = + `Rd_85c30_gi + +c +, +DATA_REGISTER + ); + +353 +da + & +Ch_size_85c30 +[ +Pt +-> +Proc +-> +ad_ch_bs + ]. +mask_vue +; + +355 +da +; + +356 + } +} + +362 #i +CONSOLE_USE_INTERRUPTS + + +369 +ems_i + + $ISR_85c30_Async +( + +370 cڡ +Pt_85C30_fo + * +Pt + + +373 +ut16_t + +us +; + +374 vީ +Cse_Proc + * +Proc +; + +375 +da +; + +376 +bo + +did_somhg + = +l +; + +378 +Proc + = +Pt +->Protocol; + +380 +us + = + `Rd_85c30_gi + +Pt +-> + +, 0x00 ); + +386 i + `Z8530_Stus_Is_RX_cha_avaab + +us + ) ) { + +387 +da + = + `Rd_85c30_gi + +Pt +-> + +, +DATA_REGISTER + ); + +388 +da + & +Ch_size_85c30 +[ +Pt +-> +Proc +-> +ad_ch_bs + ]. +mask_vue +; + +390 + `ems_rmios_queue_w_chas + +Pt +-> +Proc +-> +cse_rmios_da +, + +391 & +da +, 1 ); + +392 +did_somhg + = +ue +; + +399 i( + `Z8530_Stus_Is_TX_bufr_emy + +us + ) ) { + +400 i! + `Rg_bufr_Is_emy +& +Proc +-> +TX_Bufr + ) ) { + +401 + `Rg_bufr_Remove_cha +& +Proc +-> +TX_Bufr +, +da + ); + +402 + `Wre_85c30_gi + +Pt +-> + +, +DATA_REGISTER +, +da + ); + +405 +Proc +-> +Is_TX_aive + = +l +; + +406 + `Wre_85c30_gi + +Pt +-> + +, +STATUS_REGISTER +, 0x28 ); + +409 +did_somhg + = +ue +; + +419 + `Wre_85c30_gi + +Pt +-> + +, +STATUS_REGISTER +, 0x38 ); + +420 + } +} + + @console/85c30.h + +13 #ide +__85c30_H + + +14 + #__85c30_H + + + ) + +20 + #Z8530_x1_CLOCK + 0x00 + + ) + +21 + #Z8530_x16_CLOCK + 0x40 + + ) + +22 + #Z8530_x32_CLOCK + 0x80 + + ) + +23 + #Z8530_x64_CLOCK + 0xC0 + + ) + +28 + #Z8530_STOP_BITS_1 + 0x04 + + ) + +29 + #Z8530_STOP_BITS_1_AND_A_HALF + 0x08 + + ) + +30 + #Z8530_STOP_BITS_2 + 0x0C + + ) + +35 + #Z8530_PARITY_NONE + 0x00 + + ) + +36 + #Z8530_PARITY_ODD + 0x01 + + ) + +37 + #Z8530_PARITY_EVEN + 0x03 + + ) + +42 + #Z8530_READ_CHARACTER_BITS_8 + 0xC0 + + ) + +43 + #Z8530_READ_CHARACTER_BITS_7 + 0x40 + + ) + +44 + #Z8530_READ_CHARACTER_BITS_6 + 0x80 + + ) + +45 + #Z8530_READ_CHARACTER_BITS_5 + 0x00 + + ) + +47 + #Z8530_WRITE_CHARACTER_BITS_8 + 0x60 + + ) + +48 + #Z8530_WRITE_CHARACTER_BITS_7 + 0x20 + + ) + +49 + #Z8530_WRITE_CHARACTER_BITS_6 + 0x40 + + ) + +50 + #Z8530_WRITE_CHARACTER_BITS_5 + 0x00 + + ) + + @console/console.c + +18 + ~<b.h +> + +19 + ~<ems/libio.h +> + +20 + ~<dlib.h +> + +21 + ~<as.h +> + +23 + ~"cseb.h +" + +24 + ~<ems/bIo.h +> + +33 + #USE_FOR_CONSOLE_DEF + 0 + + ) + +34 + gUSE_FOR_CONSOLE + = +USE_FOR_CONSOLE_DEF +; + +46 + $cse_by_nblockg +( + +47 +m + + +50 +pt + = +m +; + +55 + `as + ( +pt + < +NUM_Z85C30_PORTS + ); + +60 + `by_nblockg_85c30 +& +Pts_85C30 +[ +pt + ] ); + +61 + } +} + +63 +ems_devi_driv + + $cse_o +( + +64 +ems_devi_maj_numb + +maj +, + +65 +ems_devi_m_numb + +m +, + +66 * +g + + +69 + `ems_rmios_o + ( +g +); + +70 + } +} + +72 +ems_devi_driv + + $cse_ad +( + +73 +ems_devi_maj_numb + +maj +, + +74 +ems_devi_m_numb + +m +, + +75 * +g + + +78 + `ems_rmios_ad + ( +g +); + +79 + } +} + +81 +ems_devi_driv + + $cse_wre +( + +82 +ems_devi_maj_numb + +maj +, + +83 +ems_devi_m_numb + +m +, + +84 * +g + + +87 + `ems_rmios_wre + ( +g +); + +88 + } +} + +90 +ems_devi_driv + + $cse_cڌ +( + +91 +ems_devi_maj_numb + +maj +, + +92 +ems_devi_m_numb + +m +, + +93 * +g + + +96 + `ems_rmios_iol + ( +g +); + +97 + } +} + +103 #i +CONSOLE_USE_INTERRUPTS + + +105 +ems_i + + $cse_i +( + +106 +ems_ve_numb + +ve + + +109 +i +; + +111 +i +=0; i < +NUM_Z85C30_PORTS +; i++){ + +112 + `ISR_85c30_Async +& +Pts_85C30 +[ +i +] ); + +114 + } +} + +116 + $cse_ex +() + +118 +i +; + +119 vީ +Rg_bufr_t + * +bufr +; + +120 +ut32_t + +ch +; + +122 +i +=0 ; i < +NUM_Z85C30_PORTS + ; i++ ) { + +124 +bufr + = & +Pts_85C30 +[ +i +]. +Proc +-> +TX_Bufr +); + +126 ! + `Rg_bufr_Is_emy + +bufr + ) ) { + +127 + `Rg_bufr_Remove_cha + +bufr +, +ch + ); + +128 + `outby_pd_85c30 + +Pts_85C30 +[ +i +]. + +, +ch + ); + +131 + } +} + +133 + $cse_lize_us +( ) + +135 vީ +Rg_bufr_t + * +bufr +; + +136 +Cse_Proc + * +oc +; + +137 +i +; + +139 +i +=0 ; i < +NUM_Z85C30_PORTS + ; i++ ) { + +140 +oc + = +Pts_85C30 +[ +i +]. +Proc +; + +145 +bufr + = & +oc +-> +TX_Bufr +; + +146 + `Rg_bufr_Inlize + +bufr + ); + +147 +oc +-> +Is_TX_aive + = +l +; + +153 +i +=0; i < +NUM_Z85C30_CHIPS +; i++) + +154 + `t_ve + +cse_i +, +Chs_85C30 +[ +i +]. +ve +, 1 ); + +157 + `ex + +cse_ex + ); + +159 + } +} + +160 +cse_outby_us +( + +161 cڡ +Pt_85C30_fo + * +Pt +, + +162 +ch + + +172 +ems_devi_driv + + $cse_lize +( + +173 +ems_devi_maj_numb + +maj +, + +174 +ems_devi_m_numb + +m +, + +175 * +g + + +178 +ems_us_code + +us +; + +179 +ems_devi_m_numb + +cse +; + +180 +pt +, +p0 +, +p1 +; + +185 + `ems_rmios_lize +(); + +190 +cse + = +USE_FOR_CONSOLE +; + +191 +us + = + `ems_io_gi_me +"/dev/cse", +maj +, +cse + ); + +192 i( +us + ! +RTEMS_SUCCESSFUL +) + +193 + `ems_l_r_occued +( +us +); + +205 #i +INITIALIZE_COM_PORTS + ) + +211 +pt +=0;t< +NUM_Z85C30_PORTS +;ort++){ + +212 +p0 + = +pt +; + +213 +pt +++; + +214 +p1 + = +pt +; + +215 + `Ret_85c30_ch + +Pts_85C30 +[ +p0 +]. + +, Pts_85C30[ +p1 +].ctrl ); + +221 +pt +=2;t< +NUM_Z85C30_PORTS +;ort++){ + +222 +p0 + = +pt +; + +223 +pt +++; + +224 +p1 + = +pt +; + +225 + `Ret_85c30_ch + +Pts_85C30 +[ +p0 +]. + +, Pts_85C30[ +p1 +].ctrl ); + +235 +pt +=1;t< +NUM_Z85C30_PORTS +;ort++) { + +236 + `lize_85c30_pt +& +Pts_85C30 +[ +pt +] ); + +239 #i +CONSOLE_USE_INTERRUPTS + + +240 + `cse_lize_us +(); + +243 +RTEMS_SUCCESSFUL +; + +244 + } +} + +252 +ssize_t + + $cse_wre_sut +( + +253 +m +, + +254 cڡ * +buf +, + +255 +size_t + +n +) + +257 +nwre + = 0; + +258 vީ +ut8_t + * +c +; + +259 +pt + = +m +; + +264 + `as + ( +pt + < +NUM_Z85C30_PORTS + ); + +269 +c + = +Pts_85C30 +[ +pt + ]. + +; + +274 +nwre + < +n +) { + +275 #i( +CONSOLE_USE_INTERRUPTS +) + +276 + `cse_outby_us +& +Pts_85C30 +[ +pt + ], * +buf +++ ); + +278 + `outby_pd_85c30 + +c +, * +buf +++ ); + +280 +nwre +++; + +286 +nwre +; + +287 + } +} + +294 +ems_devi_driv + + $cse_ݒ +( + +295 +ems_devi_maj_numb + +maj +, + +296 +ems_devi_m_numb + +m +, + +297 * +g + + +300 +ems_us_code + +sc +; + +301 +pt + = +m +; + +302 #i( +CONSOLE_USE_INTERRUPTS +) + +303 +ems_libio_ݒ_o_gs_t + * +gs + = +g +; + +304 cڡ +ems_rmios_backs + +Clbacks + = { + +305 +NULL +, + +306 +NULL +, + +307 +NULL +, + +308 +cse_wre_sut +, + +309 +NULL +, + +310 +NULL +, + +311 +NULL +, + +315 cڡ +ems_rmios_backs + +plClbacks + = { + +316 +NULL +, + +317 +NULL +, + +318 +cse_by_nblockg +, + +319 +cse_wre_sut +, + +320 +NULL +, + +321 +NULL +, + +322 +NULL +, + +330 i( +m + < 0) + +331 +RTEMS_INVALID_NUMBER +; + +333 i +pt + > +NUM_Z85C30_PORTS + ) + +334 +RTEMS_INVALID_NUMBER +; + +340 #i( +CONSOLE_USE_INTERRUPTS +) + +341 +sc + = + `ems_rmios_ݒ + +maj +, +m +, +g +, & +Clbacks + ); + +343 +Pts_85C30 +[ +m + ]. +Proc +-> +cse_rmios_da + = +gs +-> +i +-> +da1 +; + +345 +sc + = + `ems_rmios_ݒ + +maj +, +m +, +g +, & +plClbacks + ); + +348 +sc +; + +349 + } +} + +351 #i( +CONSOLE_USE_INTERRUPTS +) + +357 + $cse_outby_us +( + +358 cڡ +Pt_85C30_fo + * +Pt +, + +359 +ch + + +362 +Cse_Proc + * +oc +; + +363 +ut32_t + +iv +; + +365 +oc + = +Pt +-> +Proc +; + +371 i +oc +-> +Is_TX_aive + = +l + ) { + +373 + `ems_u_dib + +iv + ); + +374 +oc +-> +Is_TX_aive + = +ue +; + +375 + `outby_pd_85c30 + +Pt +-> + +, +ch + ); + +376 + `ems_u_ab + +iv + ); + +381 + `Rg_bufr_Is_fu +& +oc +-> +TX_Bufr + ) ); + +383 + `Rg_bufr_Add_cha +& +oc +-> +TX_Bufr +, +ch + ); + +384 + } +} + +388 + $debug_putc_l +(cڡ +c +) + +390 +cse +; + +391 vީ +ut8_t + * +c +; + +392 +ut32_t + +iv +; + +394 +cse + = +USE_FOR_CONSOLE +; + +395 +c + = +Pts_85C30 +[ +cse + ]. + +; + +397 i('\n'== +c +){ + +398 + `ems_u_dib + +iv + ); + +399 + `outby_pd_85c30 + +c +, '\r' ); + +400 +__asm__ + volatile("isync"); + +401 + `ems_u_ab + +iv + ); + +404 + `ems_u_dib + +iv + ); + +405 + `outby_pd_85c30 + +c +, +c + ); + +406 +__asm__ + volatile("isync"); + +407 + `ems_u_ab + +iv + ); + +408 + } +} + +410 +BSP_ouut_ch_funi_ty + + gBSP_ouut_ch + = +debug_putc_l +; + +411 +BSP_plg_gch_funi_ty + + gBSP_pl_ch + = +NULL +; + + @console/consolebsp.h + +13 #ide +__CONSOLEBSP_H + + +14 + #__CONSOLEBSP_H + + + ) + +16 + ~<ems.h +> + +17 + ~<ems/rgbuf.h +> + +18 + ~<b.h +> + +20 #ifde +__lulus + + +35 #i( +HAS_PMC_PSC8 +) + +36 + #NUM_Z85C30_CHIPS_ON_MEZZANINE + 4 + + ) + +38 + #NUM_Z85C30_CHIPS_ON_MEZZANINE + 0 + + ) + +41 + #NUM_Z85C30_CHIPS + (2 + +NUM_Z85C30_CHIPS_ON_MEZZANINE +) + + ) + +42 + #NUM_Z85C30_PORTS + ( +NUM_Z85C30_CHIPS + * 2) + + ) + +45 +CONSOLE_x1_CLOCK +, + +46 +CONSOLE_x16_CLOCK +, + +47 +CONSOLE_x32_CLOCK +, + +48 +CONSOLE_x64_CLOCK +, + +49 } + tCONSOLE_Clock_d +; + +52 +CONSOLE_STOP_BITS_1 +, + +53 +CONSOLE_STOP_BITS_1_AND_A_HALF +, + +54 +CONSOLE_STOP_BITS_2 +, + +55 } + tCONSOLE_St_bs +; + +58 +CONSOLE_PARITY_NONE +, + +59 +CONSOLE_PARITY_ODD +, + +60 +CONSOLE_PARITY_EVEN +, + +61 } + tCONSOLE_Py +; + +64 +CONSOLE_CHARACTER_BITS_8 +, + +65 +CONSOLE_CHARACTER_BITS_7 +, + +66 +CONSOLE_CHARACTER_BITS_6 +, + +67 +CONSOLE_CHARACTER_BITS_5 +, + +68 } + tCONSOLE_Cha_bs +; + +71 +ut32_t + +baud_ +; + +72 +CONSOLE_St_bs + +_bs +; + +73 +CONSOLE_Py + +ry +; + +74 +CONSOLE_Cha_bs + +ad_ch_bs +; + +75 +CONSOLE_Cha_bs + +wre_ch_bs +; + +77 #i +CONSOLE_USE_INTERRUPTS + + +78 vީ +Rg_bufr_t + +TX_Bufr +; + +79 vީ +bo + +Is_TX_aive +; + +80 * +cse_rmios_da +; + +83 } + tCse_Proc +; + +89 +ut32_t + +ve +; + +90 +ut32_t + +ock_equcy +; + +91 +ut16_t + +ock_x +; + +92 +CONSOLE_Clock_d + +ock_d +; + +93 } + tCh_85C30_fo +; + +100 vީ * + +; + +101 vީ * +da +; + +103 +pt +; + +105 +Cse_Proc + * +Proc +; + +106 +Ch_85C30_fo + * +Ch +; + +108 } + tPt_85C30_fo +; + +113 +Ch_85C30_fo + +Chs_85C30 + [ +NUM_Z85C30_CHIPS + ]; + +114
cڡ +Pt_85C30_fo + +Pts_85C30 + [ +NUM_Z85C30_PORTS + ]; + +119 +lize_85c30_pt +( + +120 cڡ +Pt_85C30_fo + * +Pt + + +123 +outby_pd_85c30 +( + +124 vީ * +c +, + +125 +ch + + +128 +by_nblockg_85c30 +( + +129 cڡ +Pt_85C30_fo + * +Pt + + +132 +Ret_85c30_ch +( + +133 vީ * +_0 +, + +134 vީ * +_1 + + +137 #i +CONSOLE_USE_INTERRUPTS + + +138 +ems_i + +ISR_85c30_Async +( + +139 cڡ +Pt_85C30_fo + * +Pt + + +142 #ifde +__lulus + + + @console/tbl85c30.c + +13 + ~"cseb.h +" + +14 + ~<b.h +> + +15 + ~<b/q.h +> + +17 + #CONSOLE_DEFAULT_BAUD_RATE + 9600 + + ) + +18 + #CONSOLE_DEFAULT_BAUD_CONSTANT + + `Sce603e_Z8530_Ch0_Baud +(9600) + + ) + +20 + #CONSOLE_DEFAULT_STOP_BITS + +CONSOLE_STOP_BITS_1 + + + ) + +21 + #CONSOLE_DEFAULT_PARITY + +CONSOLE_PARITY_NONE + + + ) + +22 + #CONSOLE_DEFAULT_READ_CHARACTER_BITS + +CONSOLE_CHARACTER_BITS_8 + + + ) + +23 + #CONSOLE_DEFAULT_WRITE_CHARACTER_BITS + +CONSOLE_CHARACTER_BITS_8 + + + ) + +24 + #CONSOLE_DEFAULT_CONSOLE_CLOCK + +CONSOLE_x16_CLOCK + + + ) + +26 + #DEFAULT_PROTOCOL + { +CONSOLE_DEFAULT_BAUD_RATE +, \ + +27 +CONSOLE_DEFAULT_STOP_BITS +, \ + +28 +CONSOLE_DEFAULT_PARITY +, \ + +29 +CONSOLE_DEFAULT_READ_CHARACTER_BITS +, \ + +30 +CONSOLE_DEFAULT_WRITE_CHARACTER_BITS + } + + ) + +35 +Cse_Proc + + gProcs_85c30 + [ +NUM_Z85C30_PORTS + ] = + +37 +DEFAULT_PROTOCOL +, + +38 +DEFAULT_PROTOCOL +, + +39 +DEFAULT_PROTOCOL +, + +40 +DEFAULT_PROTOCOL +, + +42 #i( +HAS_PMC_PSC8 +) + +43 +DEFAULT_PROTOCOL +, + +44 +DEFAULT_PROTOCOL +, + +45 +DEFAULT_PROTOCOL +, + +46 +DEFAULT_PROTOCOL +, + +47 +DEFAULT_PROTOCOL +, + +48 +DEFAULT_PROTOCOL +, + +49 +DEFAULT_PROTOCOL +, + +50 +DEFAULT_PROTOCOL +, + +58 +Ch_85C30_fo + + gChs_85C30 + [ +NUM_Z85C30_CHIPS + ] = + +61 +SCORE603E_85C30_0_IRQ +, + +62 +SCORE603E_85C30_0_CLOCK +, + +63 +SCORE603E_85C30_0_CLOCK_X +, + +64 +CONSOLE_DEFAULT_CONSOLE_CLOCK + + +67 +SCORE603E_85C30_1_IRQ +, + +68 +SCORE603E_85C30_1_CLOCK +, + +69 +SCORE603E_85C30_1_CLOCK_X +, + +70 +CONSOLE_DEFAULT_CONSOLE_CLOCK + + +73 #i( +HAS_PMC_PSC8 +) + +75 +SCORE603E_85C30_2_IRQ +, + +76 +SCORE603E_85C30_2_CLOCK +, + +77 +SCORE603E_85C30_2_CLOCK_X +, + +78 +CONSOLE_DEFAULT_CONSOLE_CLOCK + + +81 +SCORE603E_85C30_3_IRQ +, + +82 +SCORE603E_85C30_3_CLOCK +, + +83 +SCORE603E_85C30_3_CLOCK_X +, + +84 +CONSOLE_DEFAULT_CONSOLE_CLOCK + + +87 +SCORE603E_85C30_4_IRQ +, + +88 +SCORE603E_85C30_4_CLOCK +, + +89 +SCORE603E_85C30_4_CLOCK_X +, + +90 +CONSOLE_DEFAULT_CONSOLE_CLOCK + + +93 +SCORE603E_85C30_5_IRQ +, + +94 +SCORE603E_85C30_5_CLOCK +, + +95 +SCORE603E_85C30_5_CLOCK_X +, + +96 +CONSOLE_DEFAULT_CONSOLE_CLOCK + + +106 cڡ +Pt_85C30_fo + + gPts_85C30 + [ +NUM_Z85C30_PORTS + ] = { + +108 (vީ * +SCORE603E_85C30_CTRL_0 +, + +109 (vީ * +SCORE603E_85C30_DATA_0 +, + +111 & +Procs_85c30 +[0], + +112 & +Chs_85C30 +[0], + +115 (vީ * +SCORE603E_85C30_CTRL_1 +, + +116 (vީ * +SCORE603E_85C30_DATA_1 +, + +118 & +Procs_85c30 +[1], + +119 & +Chs_85C30 +[0], + +122 (vީ * +SCORE603E_85C30_CTRL_2 +, + +123 (vީ * +SCORE603E_85C30_DATA_2 +, + +125 & +Procs_85c30 +[2], + +126 & +Chs_85C30 +[1], + +129 (vީ * +SCORE603E_85C30_CTRL_3 +, + +130 (vީ * +SCORE603E_85C30_DATA_3 +, + +132 & +Procs_85c30 +[3], + +133 & +Chs_85C30 +[1], + +136 #i( +HAS_PMC_PSC8 +) + +138 (vީ * +SCORE603E_85C30_CTRL_4 +, + +139 (vީ * +SCORE603E_85C30_DATA_4 +, + +141 & +Procs_85c30 +[4], + +142 & +Chs_85C30 +[2], + +145 (vީ * +SCORE603E_85C30_CTRL_5 +, + +146 (vީ * +SCORE603E_85C30_DATA_5 +, + +148 & +Procs_85c30 +[5], + +149 & +Chs_85C30 +[2], + +152 (vީ * +SCORE603E_85C30_CTRL_6 +, + +153 (vީ * +SCORE603E_85C30_DATA_6 +, + +155 & +Procs_85c30 +[6], + +156 & +Chs_85C30 +[3], + +159 (vީ * +SCORE603E_85C30_CTRL_7 +, + +160 (vީ * +SCORE603E_85C30_DATA_7 +, + +162 & +Procs_85c30 +[7], + +163 & +Chs_85C30 +[3], + +166 (vީ * +SCORE603E_85C30_CTRL_8 +, + +167 (vީ * +SCORE603E_85C30_DATA_8 +, + +169 & +Procs_85c30 +[8], + +170 & +Chs_85C30 +[4], + +173 (vީ * +SCORE603E_85C30_CTRL_9 +, + +174 (vީ * +SCORE603E_85C30_DATA_9 +, + +176 & +Procs_85c30 +[9], + +177 & +Chs_85C30 +[4], + +180 (vީ * +SCORE603E_85C30_CTRL_10 +, + +181 (vީ * +SCORE603E_85C30_DATA_10 +, + +183 & +Procs_85c30 +[10], + +184 & +Chs_85C30 +[5], + +187 (vީ * +SCORE603E_85C30_CTRL_11 +, + +188 (vީ * +SCORE603E_85C30_DATA_11 +, + +190 & +Procs_85c30 +[11], + +191 & +Chs_85C30 +[5], + + @include/bsp.h + +14 #ide +_BSP_H + + +15 + #_BSP_H + + + ) + +17 #ifde +__lulus + + +21 + #BSP_ZERO_WORKSPACE_AUTOMATICALLY + +TRUE + + + ) + +23 + ~<bts.h +> + +24 + ~<b/deu-l-exnsi.h +> + +25 + ~<ems.h +> + +26 + ~<ems/cse.h +> + +27 + ~<libu/io.h +> + +28 + ~<ems/ockdrv.h +> + +29 + ~<b/ves.h +> + +31 #ifde +ASM + + +33 + #ALIGN_REGS + 0x0140 + + ) + +36 + ~<ems.h +> + +37 + ~<ems/cse.h +> + +38 + ~<ems/ockdrv.h +> + +39 + ~<ems/iosu.h +> + +45 + ~<g2.h +> + +46 + ~<b/q.h +> + +54 + #_Sce603e_Z8530_Baud + +_equcy +, +_ock_by +, +_baud_ + ) \ + +55 ( +_equcy + / +_ock_by + * 2 * +_baud_ +)- 2) + + ) + +57 + #Sce603e_Z8530_Ch1_Baud + +_vue + ) \ + +58 + `_Sce603e_Z8530_Baud + +SCORE603E_85C30_1_CLOCK +, \ + +59 +SCORE603E_85C30_1_CLOCK_X +, +_vue + ) + + ) + +61 + #Sce603e_Z8530_Ch0_Baud + +_vue + ) \ + +62 + `_Sce603e_Z8530_Baud + +SCORE603E_85C30_0_CLOCK +, \ + +63 +SCORE603E_85C30_0_CLOCK_X +, +_vue + ) + + ) + +65 + #Inlize_Brd__gi +() \ + +66 * +SCORE603E_BOARD_CTRL_REG + = (*SCORE603E_BOARD_CTRL_REG | \ + +67 +SCORE603E_BRD_FLASH_DISABLE_MASK +) + + ) + +69 + #Pross_Synchrize +() \ + +70 +__asm__ + vީe("i") + + ) + +91
+RAM_START +; + +92
+RAM_END +; + +93
+RAM_SIZE +; + +95
+PROM_START +; + +96
+PROM_END +; + +97
+PROM_SIZE +; + +99
+CLOCK_SPEED +; + +100
+CPU_PPC_CLICKS_PER_MS +; + +102
+d +; + +107
+d +; + +108
+RAM_END +; + +109 +ut32_t + +BSP_mem_size +; + +116 + #BSP_LIBIO_MAX_FDS + 20 + + ) + +123 +ems_i_y + +t_EE_ve +( + +124 +ems_i_y + +hdr +, + +125 +ems_ve_numb + +ve + + +127 +lize_ex_exi_ve +( ); + +132 +_PCI +( ); + +133 +_RTC +( ); + +134 +rui_che_ab +( ); + +135 +da_che_ab +( ); + +137 +lize_PCI_bridge +( ); + +138 +ut16_t + +ad_d_r_q +( ); + +139 +t_q_mask +( +ut16_t + +vue +); + +140 +ut16_t + +g_q_mask +( ); + +145 +lize_univ +( ); + +146 +t_q_mask +( +ut16_t + +vue +); + +147 +ut16_t + +g_q_mask +( ); + +148 +unmask_q +( +ut16_t + +q_idx +); + +149 +mask_q +( +ut16_t + +q_idx +); + +150 +_q_da_gi +( ); + +151 +ut16_t + +ad_d_r_PMC_q +(ut16_ +q +); + +152 +bo + +Is_PMC_IRQ + +ut32_t + +pmc_q +, +ut16_t + +us_wd +); + +153 +ut16_t + +ad_d_r_q +( ); + +154 +t_vme_ba_addss +( +ut32_t + +ba_addss +); + +155 +ut32_t + +g_vme_ave_size +( ); + +156 +t_vme_ave_size + ( +ut32_t + +size +); + +161 +lize_PCI_bridge +( ); + +162 +_q_da_gi +( ); + +163 +ut32_t + +Rd_pci_devi_gi +(ut32_ +addss +); + +164 +Wre_pci_devi_gi +( +ut32_t + +addss +, ut32_ +da +); + +167 +SCORE603e_FLASH_Dib +( +ut32_t + +unud +); + +168 +SCORE603e_FLASH_vify_ab +( ); + +169 +SCORE603e_FLASH_Eb_wres +( +ut32_t + + +); + +174 +ut32_t + +PCI_bus_ad +(vީut32_* +_addr +); + +175 +PCI_bus_wre +(vީ +ut32_t + * +_addr +, ut32_ +_da +); + +177 + #BSP_FLASH_ENABLE_WRITES + +_ + + `SCORE603e_FLASH_Eb_wres +_ ) + + ) + +178 + #BSP_FLASH_DISABLE_WRITES +( +_ + + `SCORE603e_FLASH_Dib +_ ) + + ) + +180 + #Cvt_Endn_32 + +_da + ) \ + +181 (( +_da +&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \ + +182 (( +_da +&0x00ff0000)>>8| ((_da&0xff000000)>>24) + + ) + +184 + #Cvt_Endn_16 + +_da + ) \ + +185 (( +_da +&0x00ff)<<8| ((_da&0xff00)>>8) + + ) + +190 +BSP_disc_ock_hdr +( ); + +191 +BSP_c_ock_hdr +( ); + +195 #ifde +__lulus + + + @include/gen2.h + +13 #ide +__SCORE_GENERATION_2_h + + +14 + #__SCORE_GENERATION_2_h + + + ) + +16 #ifde +__lulus + + +20 + ~<ems.h +> + +25 + #SCORE603E_VME_JUMPER_ADDR + 0x00e20000 + + ) + +26 + #BSP_FLASH_BASE + 0x04000000 + + ) + +27 + #SCORE603E_ISA_PCI_IO_BASE + 0x80000000 + + ) + +28 + #SCORE603E_TIMER_PORT_C + 0xfd000000 + + ) + +29 + #SCORE603E_TIMER_INT_ACK + 0xfd000000 + + ) + +30 + #SCORE603E_TIMER_PORT_B + 0xfd000008 + + ) + +31 + #SCORE603E_TIMER_PORT_A + 0xfd000004 + + ) + +33 + #SCORE603E_BOARD_CTRL_REG + ((vީ +ut8_t +*)0xfd00002c) + + ) + +34 + #SCORE603E_BRD_FLASH_DISABLE_MASK + 0x40 + + ) + +36 + #SCORE603E_85C30_CTRL_0 + ((vީ +ut8_t +*)0x200020) + + ) + +37 + #SCORE603E_85C30_DATA_0 + ((vީ +ut8_t +*)0x200024) + + ) + +38 + #SCORE603E_85C30_CTRL_1 + ((vީ +ut8_t +*)0x200028) + + ) + +39 + #SCORE603E_85C30_DATA_1 + ((vީ +ut8_t +*)0x20002c) + + ) + +40 + #SCORE603E_85C30_CTRL_2 + ((vީ +ut8_t +*)0x200000) + + ) + +41 + #SCORE603E_85C30_DATA_2 + ((vީ +ut8_t +*)0x200004) + + ) + +42 + #SCORE603E_85C30_CTRL_3 + ((vީ +ut8_t +*)0x200008) + + ) + +43 + #SCORE603E_85C30_DATA_3 + ((vީ +ut8_t +*)0x20000c) + + ) + +49 + #PCI_DRAM_OFFSET + +PREP_PCI_DRAM_OFFSET + + + ) + +50 + #BSP_PCI_CONFIGURATION_BASE + 0x80800000 + + ) + +51 + #BSP_PMC_BASE + +BSP_PCI_CONFIGURATION_BASE + + + ) + +52 + #PCI_MEM_BASE_ADJUSTMENT + 0 + + ) + +53 + #BSP_PCI_PMC_DEVICE_BASE + 0x80808000 + + ) + +54 + #BSP_PCI_REGISTER_BASE + 0xfc000000 + + ) + +56 + #BSP_PCI_DEVICE_ADDRESS + +_offt +) \ + +57 ((vީ +ut32_t + *) +BSP_PCI_PMC_DEVICE_BASE + + +_offt + )) + + ) + +60 + #BSP_PMC_SERIAL_ADDRESS + +_offt + ) \ + +61 ((vީ +ut8_t +*)( +BSP_PCI_REGISTER_BASE + + +_offt +)) + + ) + +66 + #SCORE603E_85C30_CTRL_4 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200020) + + ) + +67 + #SCORE603E_85C30_DATA_4 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200024) + + ) + +68 + #SCORE603E_85C30_CTRL_5 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200028) + + ) + +69 + #SCORE603E_85C30_DATA_5 + + `BSP_PMC_SERIAL_ADDRESS +(0x0020002c) + + ) + +70 + #SCORE603E_85C30_CTRL_6 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200030) + + ) + +71 + #SCORE603E_85C30_DATA_6 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200034) + + ) + +72 + #SCORE603E_85C30_CTRL_7 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200038) + + ) + +73 + #SCORE603E_85C30_DATA_7 + + `BSP_PMC_SERIAL_ADDRESS +(0x0020003c) + + ) + +74 + #SCORE603E_85C30_CTRL_8 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200000) + + ) + +75 + #SCORE603E_85C30_DATA_8 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200004) + + ) + +76 + #SCORE603E_85C30_CTRL_9 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200008) + + ) + +77 + #SCORE603E_85C30_DATA_9 + + `BSP_PMC_SERIAL_ADDRESS +(0x0020000c) + + ) + +78 + #SCORE603E_85C30_CTRL_10 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200010) + + ) + +79 + #SCORE603E_85C30_DATA_10 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200014) + + ) + +80 + #SCORE603E_85C30_CTRL_11 + + `BSP_PMC_SERIAL_ADDRESS +(0x00200018) + + ) + +81 + #SCORE603E_85C30_DATA_11 + + `BSP_PMC_SERIAL_ADDRESS +(0x0020001c) + + ) + +83 + #_IO_BASE + +PREP_ISA_IO_BASE + + + ) + +84 + #SCORE603E_PCI_IO_CFG_ADDR + 0x80000cf8 + + ) + +85 + #SCORE603E_PCI_IO_CFG_DATA + 0x80000cfc + + ) + +87 + #SCORE603E_UNIVERSE_BASE + 0x80030000 + + ) + +88 + #SCORE603E_IO_VME_UNIVERSE_BASE + 0x80007000 + + ) + +89 + #PCI_MEM_BASE + 0xc0000000 + + ) + +90 + #BSP_PCI_MEM_BASE + +PCI_MEM_BASE + + + ) + +91 + #BSP_NVRAM_BASE + 0xfd100000 + + ) + +92 + #BSP_RTC_ADDRESS + ((vީ *)0xfd180000) + + ) + +93 + #SCORE603E_JP1_JP2_PROM_BASE + 0xfff00000 + + ) + +94 + #SCORE603E_NOT_JP1_2_FLASH_BASE + 0xff800000 + + ) + +96 #i( +SCORE603E_USE_SDS +| ( +SCORE603E_USE_OPEN_FIRMWARE +| ( +SCORE603E_USE_NONE +) + +97 + #SCORE603E_VME_A16_OFFSET + 0x04000000 + + ) + +98 #i( +SCORE603E_USE_DINK +) + +99 + #SCORE603E_VME_A16_OFFSET + 0x11000000 + + ) + +100 + #SCORE603E_VME_A24_OFFSET + 0x10000000 + + ) + +101 + #BSP_VME_A24_BASE + ( +BSP_PCI_MEM_BASE ++ +SCORE603E_VME_A24_OFFSET +) + + ) + +106 + #BSP_VME_A16_BASE + ( +BSP_PCI_MEM_BASE ++ +SCORE603E_VME_A16_OFFSET +) + + ) + +114 + #ICM1770_CRYSTAL_FREQ_32K + 0x00 + + ) + +115 + #ICM1770_CRYSTAL_FREQ_1M + 0x01 + + ) + +116 + #ICM1770_CRYSTAL_FREQ_2M + 0x02 + + ) + +117 + #ICM1770_CRYSTAL_FREQ_4M + 0x03 + + ) + +119 + #BSP_RTC_FREQUENCY + +ICM1770_CRYSTAL_FREQ_32K + + + ) + +124 + #SCORE603E_85C30_0_CLOCK + 14745600 + + ) + +125 + #SCORE603E_85C30_0_CLOCK_X + 16 + + ) + +130 + #SCORE603E_85C30_1_CLOCK + 16000000 + + ) + +131 + #SCORE603E_85C30_1_CLOCK_X + 16 + + ) + +136 + #SCORE603E_85C30_PMC_CLOCK + 16000000 + + ) + +137 + #SCORE603E_85C30_PMC_CLOCK_X + 16 + + ) + +139 + #SCORE603E_85C30_2_CLOCK + +SCORE603E_85C30_PMC_CLOCK + + + ) + +140 + #SCORE603E_85C30_3_CLOCK + +SCORE603E_85C30_PMC_CLOCK + + + ) + +141 + #SCORE603E_85C30_4_CLOCK + +SCORE603E_85C30_PMC_CLOCK + + + ) + +142 + #SCORE603E_85C30_5_CLOCK + +SCORE603E_85C30_PMC_CLOCK + + + ) + +143 + #SCORE603E_85C30_2_CLOCK_X + +SCORE603E_85C30_PMC_CLOCK_X + + + ) + +144 + #SCORE603E_85C30_3_CLOCK_X + +SCORE603E_85C30_PMC_CLOCK_X + + + ) + +145 + #SCORE603E_85C30_4_CLOCK_X + +SCORE603E_85C30_PMC_CLOCK_X + + + ) + +146 + #SCORE603E_85C30_5_CLOCK_X + +SCORE603E_85C30_PMC_CLOCK_X + + + ) + +148 + #SCORE603E_UNIVERSE_CHIP_ID + 0x000010E3 + + ) + +153 + #SCORE603E_FPGA_VECT_DATA + ((vީ +ut16_t +*)0xfd000040) + + ) + +154 + #SCORE603E_FPGA_BIT1_15_0 + ((vީ +ut16_t +*)0xfd000044) + + ) + +155 + #SCORE603E_FPGA_MASK_DATA + ((vީ +ut16_t +*)0xfd000048) + + ) + +156 + #SCORE603E_FPGA_IRQ_INPUT + ((vީ +ut16_t +*)0xfd00004c) + + ) + +161 + #BSP_PMC_STATUS_ADDRESS + ( + `BSP_PMC_SERIAL_ADDRESS + (0)) + + ) + +162 + #Is_PMC_85C30_4_IRQ + +_us + ) (_u& 0x80 + + ) + +163 + #Is_PMC_85C30_2_IRQ + +_us + ) (_u& 0x40 + + ) + +164 + #Is_PMC_85C30_5_IRQ + +_us + ) (_u& 0x20 + + ) + +165 + #Is_PMC_85C30_3_IRQ + +_us + ) (_u& 0x08 + + ) + +167 + #SCORE603E_PMC_CONTROL_ADDRESS + + `BSP_PMC_SERIAL_ADDRESS +(0x100000) + + ) + +168 + #SCORE603E_PMC_SCC_232_LOOPBACK + ( +_wd +(_wd|0x20) + + ) + +170 + #PMC_SET_232_LOOPBACK +( +_wd +(_wd | 0x02) + + ) + +171 + #PMC_CLEAR_232_LOOPBACK +( +_wd +(_wd & 0xfd) + + ) + +172 + #PMC_SET_422_LOOPBACK +( +_wd +(_wd | 0x01) + + ) + +173 + #PMC_CLEAR_422_LOOPBACK +( +_wd +(_wd & 0x) + + ) + +185 + #BSP_TIMER_AVG_OVERHEAD + 4 + + ) + +187 + #BSP_TIMER_LEAST_VALID + 1 + + ) + +201 + #BSP_Cvt_deemr + +_vue + ) \ + +202 (((( +_vue +* 4000/ 6667) + + ) + +204 #ifde +__lulus + + + @include/tm27.h + +16 #ide +_RTEMS_TMTEST27 + + +20 #ide +__tm27_h + + +21 + #__tm27_h + + + ) + +23 + ~<b/q.h +> + +29 + #MUST_WAIT_FOR_INTERRUPT + 1 + + ) + +31 + $nuFunc +({ + } +} + +33 +ems_q_c_da + + gockIrqDa + = { +BSP_DECREMENTER +, + +35 ( +ems_q_ab +) +nuFunc +, + +36 ( +ems_q_dib +) +nuFunc +, + +37 ( +ems_q_is_abd + +nuFunc +}; + +38 +Inl_tm27_ve +( (* +_hdr +)()) + +40 +ockIrqDa +. +hdl + = +_hdr +; + +41 i(! + `BSP_l_ems_q_hdr + (& +ockIrqDa +)) { + +42 + `tk +("Error installing clock interrupt handler!\n"); + +43 + `ems_l_r_occued +(1); + +45 + } +} + +47 + #Cau_tm27_ +() \ + +49 +ut32_t + +_icks + = 8; \ + +50 +__asm__ + vީe"mtde%0" : "" (( +_icks +)) : "r" ((_clicks)) ); \ + +51 } 0) + + ) + +53 + #Cˬ_tm27_ +() \ + +55 +ut32_t + +_icks + = 0xffffffff; \ + +56 +__asm__ + vީe"mtde%0" : "" (( +_icks +)) : "r" ((_clicks)) ); \ + +57 } 0) + + ) + +59 + #Low_tm27_ +() \ + +61 +ut32_t + +_m + = 0; \ + +62 + `_ISR_S_v +( 0 ); \ + +63 +__asm__ + vީe"mfm %0 ;" : "" ( +_m +) : "r" (_msr) ); \ + +64 +_m + |= 0x8002; \ + +65 +__asm__ + vީe"mtm %0 ;" : "" ( +_m +) : "r" (_msr) ); \ + +66 } 0) + + ) + + @irq/FPGA.c + +14 + ~<b.h +> + +15 + ~<b/q.h +> + +16 + ~<rg.h +> + +17 + ~<f.h +> + +18 + ~<as.h +> + +20 + ~<ems/libio.h +> + +21 + ~<ems/libcsut.h +> + +22 + ~<ems/bIo.h +> + +27 + $lize_PCI_bridge + ( ) + +32 + } +} + +34 + $t_q_mask +( + +35 +ut16_t + +vue + + +38 vީ +ut16_t + * +loc +; + +40 +loc + = ( +ut16_t +*) +SCORE603E_FPGA_MASK_DATA +; + +42 * +loc + = +vue +; + +43 + } +} + +45 +ut16_t + + $g_q_mask +( ) + +47 vީ +ut16_t + * +loc +; + +48 +ut16_t + +vue +; + +50 +loc + = ( +ut16_t +*) +SCORE603E_FPGA_MASK_DATA +; + +52 +vue + = * +loc +; + +54 +vue +; + +55 + } +} + +57 + $mask_q +( + +58 +ut16_t + +q_idx + + +61 +ut16_t + +vue +; + +62 +ut32_t + +mask_idx + = +q_idx +; + +64 +vue + = + `g_q_mask +(); + +66 #i( +HAS_PMC_PSC8 +) + +67 +q_idx + + +Sce_IRQ_F + ) { + +68 +SCORE603E_85C30_4_IRQ +: + +69 +SCORE603E_85C30_2_IRQ +: + +70 +SCORE603E_85C30_5_IRQ +: + +71 +SCORE603E_85C30_3_IRQ +: + +72 +mask_idx + = +SCORE603E_PCI_IRQ_0 + - +Sce_IRQ_F +; + +79 +vue + |(0x1 << +mask_idx +); + +80 + `t_q_mask + +vue + ); + +81 + } +} + +83 + $unmask_q +( + +84 +ut16_t + +q_idx + + +87 +ut16_t + +vue +; + +88 +ut32_t + +mask_idx + = +q_idx +; + +90 +vue + = + `g_q_mask +(); + +92 #i( +HAS_PMC_PSC8 +) + +93 +q_idx + + +Sce_IRQ_F + ) { + +94 +SCORE603E_85C30_4_IRQ +: + +95 +SCORE603E_85C30_2_IRQ +: + +96 +SCORE603E_85C30_5_IRQ +: + +97 +SCORE603E_85C30_3_IRQ +: + +98 +mask_idx + = +SCORE603E_PCI_IRQ_0 + - +Sce_IRQ_F +; + +105 +vue + &(~(0x1 << +mask_idx +)); + +106 + `t_q_mask + +vue + ); + +107 + } +} + +109 + $_q_da_gi +( ) + +111 +ut32_t + +dex +; + +112 +ut32_t + +i +; + +114 + `t_q_mask +( 0xffff ); + +119 +i +=0; i<20; i++) { + +120 +dex + = (* +SCORE603E_FPGA_VECT_DATA +); + +121 i( +dex +&0x10) != 0x10 ) + +124 + } +} + +126 +ut16_t + + $ad_d_r_PMC_q +( + +127 +ut16_t + +q + + +130 +ut16_t + +us_wd + = +q +; + +132 +us_wd + = (* +BSP_PMC_STATUS_ADDRESS +); + +134 +us_wd +; + +135 + } +} + +137 +bo + + $Is_PMC_IRQ +( + +138 +ut32_t + +pmc_q +, + +139 +ut16_t + +us_wd + + +142 +bo + +su + = +l +; + +144 +pmc_q +) { + +145 +SCORE603E_85C30_4_IRQ +: + +146 +su + = + `Is_PMC_85C30_4_IRQ + +us_wd + ) ? +ue + : +l +; + +148 +SCORE603E_85C30_2_IRQ +: + +149 +su + = + `Is_PMC_85C30_2_IRQ + +us_wd + ) ? +ue + : +l +; + +151 +SCORE603E_85C30_5_IRQ +: + +152 +su + = + `Is_PMC_85C30_5_IRQ + +us_wd + ) ? +ue + : +l +; + +154 +SCORE603E_85C30_3_IRQ +: + +155 +su + = + `Is_PMC_85C30_3_IRQ + +us_wd + ) ? +ue + : +l +; + +158 + `as +( 0 ); + +162 +su +; + +163 + } +} + +165 +ut16_t + + $ad_d_r_q +( ) + +167 +ut16_t + +q +; + +170 +q + = (* +SCORE603E_FPGA_VECT_DATA +); + +171 + `Pross_Synchrize +(); + +172 i(( +q + & 0xffff0) != 0x10) { + +173 + `tk +"ad_d_r_q:: ERROR==>nq d0x%x\n", +q +); + +174 ( +q + | 0x80); + +177 +q + &=0xf; + +178 +q + + +Sce_IRQ_F +; + +179 +q +; + +180 + } +} + + @irq/irq.c + +11 + ~<dlib.h +> + +13 + ~<b.h +> + +14 + ~<b/q.h +> + +15 + ~<b/VME.h +> + +16 + ~<ems/sce/xt.h +> + +17 + ~<libu/io.h +> + +18 + ~<b/ves.h +> + +19 + ~<dlib.h +> + +20 + ~<ems/bIo.h +> + +25 +ems_q_c_da + + gdeu_ems_y +; + +31 +ems_q_glob_gs +* + g_cfig +; + +32 +ems_q_c_da +* + gems_hdl_tbl +; + +37 +le + + $is_i_q +(cڡ +ems_q_numb + +qLe +) + +39 ((( +qLe + < +BSP_ISA_IRQ_MAX_OFFSET +) & + +40 (( +qLe + > +BSP_ISA_IRQ_LOWEST_OFFSET +) + +42 + } +} + +47 +le + + $is_pci_q +(cڡ +ems_q_numb + +qLe +) + +49 ((( +qLe + < +BSP_PCI_IRQ_MAX_OFFSET +) & + +50 (( +qLe + > +BSP_PCI_IRQ_LOWEST_OFFSET +) + +52 + } +} + +57 +le + + $is_oss_q +(cڡ +ems_q_numb + +qLe +) + +59 ((( +qLe + < +BSP_PROCESSOR_IRQ_MAX_OFFSET +) & + +60 (( +qLe + > +BSP_PROCESSOR_IRQ_LOWEST_OFFSET +) + +62 + } +} + +73 + $isVidIru +( +q +) + +75 i( +q + < +BSP_LOWEST_OFFSET +|| (q > +BSP_MAX_OFFSET +)) + +78 + } +} + +83 + $BSP_l_ems_shed_q_hdr + (cڡ +ems_q_c_da +* +q +) + +85 +ems_u_v + +v +; + +86 +ems_q_c_da +* +vcha +; + +88 + `tk +(" BSP_l_ems_shed_q_hd˸%d\n", +q +-> +me + ); + +90 i(! + `isVidIru +( +q +-> +me +)) { + +91 + `tk +("Invid iru ve %d\n", +q +-> +me +); + +95 + `ems_u_dib +( +v +); + +97 i() +ems_hdl_tbl +[ +q +-> +me +]. +xt_hdr + == -1 ) { + +98 + `ems_u_ab +( +v +); + +99 + `tk +("IRQ ve %d̗dy cedت unshed hdr\n", +q +-> +me +); + +103 +vcha + = ( +ems_q_c_da +*) + `mloc +((rtems_irq_connect_data)); + +106 +vcha +[0] +ems_hdl_tbl +[ +q +-> +me +]; + +111 +ems_hdl_tbl +[ +q +-> +me +] = *irq; + +114 +ems_hdl_tbl +[ +q +-> +me +]. +xt_hdr + = ( *) +vcha +; + +119 i( + `is_pci_q +( +q +-> +me +)) { + +122 i( + `is_oss_q +( +q +-> +me +)) { + +130 i( +q +-> + +) + +131 +q +-> + ` +(irq); + +133 + `ems_u_ab +( +v +); + +136 + } +} + +141 +ems_us_code + + $b_u_ve_dib + +ems_ve_numb + +qLe +) + +145 + `tk +("b_u_ve_dib: 0x%x\n", +qLe + ); + +146 +RTEMS_SUCCESSFUL +; + +147 + } +} + +149 +ems_us_code + + $b_u_ve_ab + +ems_ve_numb + +qLe +) + +152 + `tk +("b_u_ve_ab: 0x%x\n", +qLe + ); + +154 +RTEMS_SUCCESSFUL +; + +155 + } +} + +163 + $BSP_l_ems_q_hdr + (cڡ +ems_q_c_da +* +q +) + +165 +ems_u_v + +v +; + +167 + `tk +(" BSP_l_ems_q_hd˸%d\n", +q +-> +me + ); + +169 i(! + `isVidIru +( +q +-> +me +)) { + +170 + `tk +("Invid iru ve %d\n", +q +-> +me +); + +180 + `ems_u_dib +( +v +); + +181 i( +ems_hdl_tbl +[ +q +-> +me +]. +hdl + ! +deu_ems_y +.hdl) { + +182 + `ems_u_ab +( +v +); + +183 + `tk +("IRQ ve %d̗dy ced\n", +q +-> +me +); + +190 +ems_hdl_tbl +[ +q +-> +me +] = *irq; + +191 +ems_hdl_tbl +[ +q +-> +me +]. +xt_hdr + = ( *)-1; + +194 i( + `is_pci_q +( +q +-> +me +)) { + +198 + `tk +("is_pci_irq = TRUE - FIX THIS!\n"); + +201 i( + `is_oss_q +( +q +-> +me +)) { + +205 + `tk +("is_processor_irq = TRUE : Fix This\n"); + +211 i( +q +-> + +) { + +212 + `tk +("C0x%x\n", +q +-> + + ); + +213 +q +-> + ` +(irq); + +216 + `ems_u_ab +( +v +); + +219 + } +} + +221 + $BSP_g_cut_ems_q_hdr + ( +ems_q_c_da +* +q +) + +223 +ems_u_v + +v +; + +225 + `tk +(" BSP_g_cut_ems_q_hd˸%d\n", +q +-> +me + ); + +226 i(! + `isVidIru +( +q +-> +me +)) { + +229 + `ems_u_dib +( +v +); + +230 * +q + = +ems_hdl_tbl +[q-> +me +]; + +231 + `ems_u_ab +( +v +); + +233 + } +} + +235 + $BSP_move_ems_q_hdr + (cڡ +ems_q_c_da +* +q +) + +237 +ems_q_c_da + * +pcha + +NULL +, * +vcha + = NULL; + +238 +ems_u_v + +v +; + +240 + `tk +(" BSP_move_ems_q_hd˸%d\n", +q +-> +me + ); + +241 i(! + `isVidIru +( +q +-> +me +)) { + +251 + `ems_u_dib +( +v +); + +252 i( +ems_hdl_tbl +[ +q +-> +me +]. +hdl + != irq->hdl) { + +253 + `ems_u_ab +( +v +); + +257 if() +ems_hdl_tbl +[ +q +-> +me +]. +xt_hdr + != -1 ) + +259 +found + = 0; + +261 ( +pcha + +NULL +, +vcha + = & +ems_hdl_tbl +[ +q +-> +me +]); + +262 ( +vcha +-> +hdl + ! +deu_ems_y +.hdl); + +263 ( +pcha + +vcha +, vcha = ( +ems_q_c_da +*)vcha-> +xt_hdr +) ) + +265 if +vcha +-> +hdl + = +q +->hdl ) + +267 +found += -1; ; + +271 if! +found + ) + +273 + `ems_u_ab +( +v +); + +279 i( +ems_hdl_tbl +[ +q +-> +me +]. +hdl + != irq->hdl) + +281 + `ems_u_ab +( +v +); + +287 i( + `is_pci_q +( +q +-> +me +)) { + +292 i( + `is_oss_q +( +q +-> +me +)) { + +301 i( +q +-> +off +) + +302 +q +-> + `off +(irq); + +307 if! +vcha + ) + +310 +ems_hdl_tbl +[ +q +-> +me +] = +deu_ems_y +; + +314 if +pcha + ) + +317 +pcha +-> +xt_hdr + = +vcha +->next_handler; + +324 +ems_hdl_tbl +[ +q +-> +me +]* +vcha +; + +326 + ` +( +vcha +); + +329 + `ems_u_ab +( +v +); + +332 + } +} + +338 + $BSP_ems_q_mngt_t +( +ems_q_glob_gs +* +cfig +) + +340 +i +; + +341 +ems_u_v + +v +; + +346 +_cfig + = +cfig +; + +347 +deu_ems_y + = +cfig +-> +deuEry +; + +348 +ems_hdl_tbl + = +cfig +-> +qHdlTbl +; + +350 + `tk +(" BSP_rtems_irq_mngt_set\n"); + +352 + `ems_u_dib +( +v +); + +360 +i += +BSP_PCI_IRQ_LOWEST_OFFSET +; i < BSP_PCI_IRQ_LOWEST_OFFSET + +BSP_PCI_IRQ_NUMBER + ; i++) { + +361 i( +ems_hdl_tbl +[ +i +]. +hdl + ! +deu_ems_y +.hdl) { + +363 +ems_q_c_da +* +vcha +; + +364 +vcha + = & +ems_hdl_tbl +[ +i +]; + +365 (() +vcha + !-1 && vcha-> +hdl + ! +deu_ems_y +.hdl); + +366 +vcha + = ( +ems_q_c_da +*)vcha-> +xt_hdr + ) + +368 i( +vcha +-> + +) + +369 +vcha +-> + ` +(vchain); + +377 +ems_q_c_da +* +vcha +; + +378 +vcha + = & +ems_hdl_tbl +[ +i +]; + +379 (() +vcha + !-1 && vcha-> +hdl + ! +deu_ems_y +.hdl); + +380 +vcha + = ( +ems_q_c_da +*)vcha-> +xt_hdr + ) + +382 i( +vcha +-> +off +) + +383 +vcha +-> + `off +(vchain); + +391 +i += +BSP_PROCESSOR_IRQ_LOWEST_OFFSET +; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET+ +BSP_PROCESSOR_IRQ_NUMBER +; i++){ + +392 i( +ems_hdl_tbl +[ +i +]. +hdl + ! +deu_ems_y +.hdl) { + +394 +ems_q_c_da +* +vcha +; + +395 +vcha + = & +ems_hdl_tbl +[ +i +]; + +396 (() +vcha + !-1 && vcha-> +hdl + ! +deu_ems_y +.hdl); + +397 +vcha + = ( +ems_q_c_da +*)vcha-> +xt_hdr + ) + +399 i( +vcha +-> + +) + +400 +vcha +-> + ` +(vchain); + +407 +ems_q_c_da +* +vcha +; + +408 +vcha + = & +ems_hdl_tbl +[ +i +]; + +409 (() +vcha + !-1 && vcha-> +hdl + ! +deu_ems_y +.hdl); + +410 +vcha + = ( +ems_q_c_da +*)vcha-> +xt_hdr + ) + +412 i( +vcha +-> +off +) + +413 +vcha +-> + `off +(vchain); + +419 + `ems_u_ab +( +v +); + +421 + } +} + +423 + $BSP_ems_q_mngt_g +( +ems_q_glob_gs +** +cfig +) + +425 * +cfig + = +_cfig +; + +427 + } +} + +429 + gBSP_uriousIr + = 0; + +434 + $C_dich_q_hdr + ( +CPU_Iru_ame + * +ame +, +excNum +) + +436 +q +; + +437 +m +; + +438 +w_m +; + +440 i( +excNum + = +ASM_DEC_VECTOR +) { + +441 + `_CPU_MSR_GET +( +m +); + +442 +w_m + = +m + | +MSR_EE +; + +443 + `_CPU_MSR_SET +( +w_m +); + +445 +ems_hdl_tbl +[ +BSP_DECREMENTER +]. + `hdl +ԋms_hdl_tbl[BSP_DECREMENTER]. +hd +); + +447 + `_CPU_MSR_SET +( +m +); + +452 +q + = + `ad_d_r_q +(); + +453 + `_CPU_MSR_GET +( +m +); + +454 +w_m + = +m + | +MSR_EE +; + +455 + `_CPU_MSR_SET +( +w_m +); + +459 +ems_q_c_da +* +vcha +; + +460 +vcha + = & +ems_hdl_tbl +[ +q +]; + +461 (() +vcha + !-1 && vcha-> +hdl + ! +deu_ems_y +.hdl); + +462 +vcha + = ( +ems_q_c_da +*)vcha-> +xt_hdr + ) + +464 +vcha +-> + `hdl +(vcha-> +hd +); + +468 + `_CPU_MSR_SET +( +m +); + +471 + } +} + +473 +ems_us_code + + $b_u_cy_lize +( ) + +476 i( + `c_exc_t_hdr + +ASM_EXT_VECTOR +, +C_dich_q_hdr +)) { + +477 +RTEMS_IO_ERROR +; + +479 i( + `c_exc_t_hdr + +ASM_DEC_VECTOR +, +C_dich_q_hdr +)) { + +480 +RTEMS_IO_ERROR +; + +482 i( + `c_exc_t_hdr + +ASM_E300_SYSMGMT_VECTOR +, +C_dich_q_hdr +)) { + +483 +RTEMS_IO_ERROR +; + +486 +RTEMS_SUCCESSFUL +; + +487 + } +} + +489 + $b_u_hdr_deu + +ems_ve_numb + +ve + ) + +491 i( +ve + ! +BSP_DECREMENTER +) { + +492 + `tk +"Spuriouu: 0x%08x\n", +ve +); + +494 + } +} + + @irq/irq.h + +20 #ide +BSP_POWERPC_IRQ_H + + +21 + #BSP_POWERPC_IRQ_H + + + ) + +23 + #BSP_SHARED_HANDLER_SUPPORT + 1 + + ) + +24 + ~<ems/q.h +> + +26 #ide +ASM + + +28 #ifde +__lulus + + +40 + #BSP_ISA_IRQ_NUMBER + (16) + + ) + +41 + #BSP_ISA_IRQ_LOWEST_OFFSET + (0) + + ) + +42 + #BSP_ISA_IRQ_MAX_OFFSET + ( +BSP_ISA_IRQ_LOWEST_OFFSET + + +BSP_ISA_IRQ_NUMBER + - 1) + + ) + +47 + #BSP_PCI_IRQ_NUMBER + (16) + + ) + +48 + #BSP_PCI_IRQ_LOWEST_OFFSET + ( +BSP_ISA_IRQ_NUMBER +) + + ) + +49 + #BSP_PCI_IRQ_MAX_OFFSET + ( +BSP_PCI_IRQ_LOWEST_OFFSET + + +BSP_PCI_IRQ_NUMBER + - 1) + + ) + +54 + #BSP_PMC_IRQ_NUMBER + (4) + + ) + +55 + #BSP_PMC_IRQ_LOWEST_OFFSET + ( +BSP_PCI_IRQ_MAX_OFFSET + + 1) + + ) + +56 + #BSP_PMC_IRQ_MAX_OFFSET + ( +BSP_PMC_IRQ_LOWEST_OFFSET + + +BSP_PMC_IRQ_NUMBER + - 1) + + ) + +63 + #BSP_PROCESSOR_IRQ_NUMBER + (1) + + ) + +64 + #BSP_PROCESSOR_IRQ_LOWEST_OFFSET + ( +BSP_PMC_IRQ_MAX_OFFSET + + 1) + + ) + +65 + #BSP_PROCESSOR_IRQ_MAX_OFFSET + ( +BSP_PROCESSOR_IRQ_LOWEST_OFFSET + + +BSP_PROCESSOR_IRQ_NUMBER + - 1) + + ) + +69 + #BSP_MISC_IRQ_NUMBER + (8) + + ) + +70 + #BSP_MISC_IRQ_LOWEST_OFFSET + ( +BSP_PROCESSOR_IRQ_MAX_OFFSET + + 1) + + ) + +71 + #BSP_MISC_IRQ_MAX_OFFSET + ( +BSP_MISC_IRQ_LOWEST_OFFSET + + +BSP_MISC_IRQ_NUMBER + - 1) + + ) + +75 + #BSP_IRQ_NUMBER + ( +BSP_MISC_IRQ_MAX_OFFSET + + 1) + + ) + +76 + #BSP_LOWEST_OFFSET + ( +BSP_ISA_IRQ_LOWEST_OFFSET +) + + ) + +77 + #BSP_MAX_OFFSET + ( +BSP_MISC_IRQ_MAX_OFFSET +) + + ) + +82 + #BSP_DECREMENTER + ( +BSP_PROCESSOR_IRQ_LOWEST_OFFSET +) + + ) + +87 + #Sce_IRQ_F + ( +BSP_PCI_IRQ_LOWEST_OFFSET + ) + + ) + +92 + #SCORE603E_IRQ00 + ( +Sce_IRQ_F + + 0 ) + + ) + +93 + #SCORE603E_IRQ01 + ( +Sce_IRQ_F + + 1 ) + + ) + +94 + #SCORE603E_IRQ02 + ( +Sce_IRQ_F + + 2 ) + + ) + +95 + #SCORE603E_IRQ03 + ( +Sce_IRQ_F + + 3 ) + + ) + +96 + #SCORE603E_IRQ04 + ( +Sce_IRQ_F + + 4 ) + + ) + +97 + #SCORE603E_IRQ05 + ( +Sce_IRQ_F + + 5 ) + + ) + +98 + #SCORE603E_IRQ06 + ( +Sce_IRQ_F + + 6 ) + + ) + +99 + #SCORE603E_IRQ07 + ( +Sce_IRQ_F + + 7 ) + + ) + +100 + #SCORE603E_IRQ08 + ( +Sce_IRQ_F + + 8 ) + + ) + +101 + #SCORE603E_IRQ09 + ( +Sce_IRQ_F + + 9 ) + + ) + +102 + #SCORE603E_IRQ10 + ( +Sce_IRQ_F + + 10 ) + + ) + +103 + #SCORE603E_IRQ11 + ( +Sce_IRQ_F + + 11 ) + + ) + +104 + #SCORE603E_IRQ12 + ( +Sce_IRQ_F + + 12 ) + + ) + +105 + #SCORE603E_IRQ13 + ( +Sce_IRQ_F + + 13 ) + + ) + +106 + #SCORE603E_IRQ14 + ( +Sce_IRQ_F + + 14 ) + + ) + +107 + #SCORE603E_IRQ15 + ( +Sce_IRQ_F + + 15 ) + + ) + +109 + #SCORE603E_TIMER1_IRQ + +SCORE603E_IRQ00 + + + ) + +110 + #SCORE603E_TIMER2_IRQ + +SCORE603E_IRQ01 + + + ) + +111 + #SCORE603E_TIMER3_IRQ + +SCORE603E_IRQ02 + + + ) + +112 + #SCORE603E_85C30_1_IRQ + +SCORE603E_IRQ03 + + + ) + +113 + #SCORE603E_85C30_0_IRQ + +SCORE603E_IRQ04 + + + ) + +114 + #SCORE603E_RTC_IRQ + +SCORE603E_IRQ05 + + + ) + +115 + #SCORE603E_PCI_IRQ_0 + +SCORE603E_IRQ06 + + + ) + +116 + #SCORE603E_PCI_IRQ_1 + +SCORE603E_IRQ07 + + + ) + +117 + #SCORE603E_PCI_IRQ_2 + +SCORE603E_IRQ08 + + + ) + +118 + #SCORE603E_PCI_IRQ_3 + +SCORE603E_IRQ09 + + + ) + +119 + #SCORE603E_UNIVERSE_IRQ + +SCORE603E_IRQ10 + + + ) + +120 + #SCORE603E_1553_IRQ + +SCORE603E_IRQ11 + + + ) + +121 + #SCORE603E_MAIL_BOX_IRQ_0 + +SCORE603E_IRQ12 + + + ) + +122 + #SCORE603E_MAIL_BOX_IRQ_1 + +SCORE603E_IRQ13 + + + ) + +123 + #SCORE603E_MAIL_BOX_IRQ_2 + +SCORE603E_IRQ14 + + + ) + +124 + #SCORE603E_MAIL_BOX_IRQ_3 + +SCORE603E_IRQ15 + + + ) + +131 + #SCORE603E_IRQ16 + ( +Sce_IRQ_F + + 16 ) + + ) + +132 + #SCORE603E_IRQ17 + ( +Sce_IRQ_F + + 17 ) + + ) + +133 + #SCORE603E_IRQ18 + ( +Sce_IRQ_F + + 18 ) + + ) + +134 + #SCORE603E_IRQ19 + ( +Sce_IRQ_F + + 19 ) + + ) + +139 + #SCORE603E_85C30_4_IRQ + +SCORE603E_IRQ16 + + + ) + +140 + #SCORE603E_85C30_2_IRQ + +SCORE603E_IRQ17 + + + ) + +141 + #SCORE603E_85C30_5_IRQ + +SCORE603E_IRQ18 + + + ) + +142 + #SCORE603E_85C30_3_IRQ + +SCORE603E_IRQ19 + + + ) + +144 + #MAX_BOARD_IRQS + +SCORE603E_IRQ19 + + + ) + +146
+BSP_ems_q_mng_ +( +uId +); + +148 #ifde +__lulus + + + @irq/irq_init.c + +19 + ~<libu/io.h +> + +20 + ~<libu/r.h +> + +21 + ~<b/pci.h +> + +22 + ~<b/sidu.h +> + +23 + ~<b/q.h +> + +24 + ~<b.h +> + +25 + ~<b/ves.h +> + +26 + ~<ems/bIo.h +> + +28 + #SHOW_ISA_PCI_BRIDGE_SETTINGS + 1 + + ) + +29 + #SCAN_PCI_PRINT + 1 + + ) + +30 + #TRACE_IRQ_INIT + 0 + + ) + +33 + mbus +; + +34 + mdevi +; + +35 + mfuni +; + +36 } + tpci_i_bridge_devi +; + +38 +pci_i_bridge_devi +* + gv_82c586 + = 0; + +40
+ex_exi_ve_og_code_size +[]; + +41
+ex_exi_ve_og_code +( ); + +42
+deemr_exi_ve_og_code_size +[]; + +43
+deemr_exi_ve_og_code +( ); + +45 + $IRQ_Deu_ems_q_hdl +( + +46 +ems_q_hdl_m + +r + + +49 + } +} + +51 + $IRQ_Deu_ems_q_ab +( + +52 cڡ +__ems_q_c_da__ + * +r + + +55 + } +} + +57 + $IRQ_Deu_ems_q_dib +( + +58 cڡ +__ems_q_c_da__ + * +r + + +61 + } +} + +63 + $IRQ_Deu_ems_q_is_abd +( + +64 cڡ +__ems_q_c_da__ + * +r +) + +67 + } +} + +69 +ems_q_c_da + + gemsIrq +[ +BSP_IRQ_NUMBER +]; + +70 +ems_q_glob_gs + + gl_cfig +; + +72 +ems_q_c_da + + gdeuIrq + = { + +73 . +me + = 0, + +74 . + ghdl + = +IRQ_Deu_ems_q_hdl +, + +75 . + ghd + = +NULL +, + +76 . + g + = +IRQ_Deu_ems_q_ab +, + +77 . + g + = +IRQ_Deu_ems_q_dib +, + +78 . + gisOn + = +IRQ_Deu_ems_q_is_abd + + +81 +ems_q_io + + gqPrioTab +[ +BSP_IRQ_NUMBER +]; + +89 + $BSP_ems_q_mng_ +( +uId +) + +91 +i +; + +103 +i + = 0; i < +BSP_IRQ_NUMBER +; i++) { + +104 +qPrioTab +[ +i +] = 8; + +105 +emsIrq +[ +i +] = +deuIrq +; + +106 +emsIrq +[ +i +]. +me + = i; + +107 #ifde +BSP_SHARED_HANDLER_SUPPORT + + +108 +emsIrq +[ +i +]. +xt_hdr + = +NULL +; + +115 +l_cfig +. +qNb + = +BSP_IRQ_NUMBER +; + +116 +l_cfig +. +deuEry + = +deuIrq +; + +117 +l_cfig +. +qHdlTbl + = +emsIrq +; + +118 +l_cfig +. +qBa + = +BSP_LOWEST_OFFSET +; + +119 +l_cfig +. +qPrioTbl + = +qPrioTab +; + +121 i(! + `BSP_ems_q_mngt_t +(& +l_cfig +)) { + +125 + `BSP_nic +("Unableo initialize RTEMS interrupt Management!!! Systemocked\n"); + +128 #ifde +TRACE_IRQ_INIT + + +129 + `tk +("RTEMS IRQ management isow operational\n"); + +131 + } +} + + @irq/no_pic.c + +13 + ~<ems.h +> + +14 + ~<b.h +> + +15 + ~<b/q.h +> + +16 + ~<b/q_su.h +> + +17 + ~<b/ves.h +> + +19 +ems_q_c_da + * + gems_hdl_tbl +; + +20 +ems_q_c_da + + gdt_y +; + +25 + $C_dich_q_hdr +( + +26 +BSP_Exi_ame + * +ame +, + +27 +excNum + + +30 +q +; + +31 #i( +HAS_PMC_PSC8 +) + +32 +ut16_t + +check_q +; + +33 +ut16_t + +us_wd +; + +36 i( +excNum + = +ASM_DEC_VECTOR +) { + +37 + `b_q_dich_li +( +ems_hdl_tbl +, +BSP_DECREMENTER +, +dt_y +. +hdl +); + +41 +q + = + `ad_d_r_q +(); + +43 #i( +HAS_PMC_PSC8 +) + +44 i( +q + = +SCORE603E_PCI_IRQ_0 +) { + +45 +us_wd + = + `ad_d_r_PMC_q + +q + ); + +46 +check_q += +SCORE603E_IRQ16 +; check_q<= +SCORE603E_IRQ19 +; check_irq++) { + +47 i + `Is_PMC_IRQ + +check_q +, +us_wd + )) { + +48 + `b_q_dich_li_ba +( +ems_hdl_tbl +, +check_q +, +dt_y +. +hdl +); + +54 + `b_q_dich_li_ba +( +ems_hdl_tbl +, +q +, +dt_y +. +hdl +); + +58 + } +} + +61 + $BSP_ab_q__pic +(cڡ +ems_q_numb + +q +) + +63 +ut16_t + +vec_idx + = +q + - +Sce_IRQ_F +; + +64 + `unmask_q + +vec_idx + ); + +65 + } +} + +68 + $BSP_dib_q__pic +(cڡ +ems_q_numb + +q +) + +70 +ut16_t + +vec_idx + = +q + - +Sce_IRQ_F +; + +71 + `unmask_q + +vec_idx + ); + +73 + } +} + +76 + $BSP_tup_the_pic +( +ems_q_glob_gs + * +cfig +) + +78 +dt_y + = +cfig +-> +deuEry +; + +79 +ems_hdl_tbl + = +cfig +-> +qHdlTbl +; + +80 + `_q_da_gi +(); + +82 + } +} + + @startup/Hwr_init.c + +11 + ~<b.h +> + +13 + #PPC603e_SPR_HID0 + 1008 + + ) + +14 + #PPC603e_SPR_HID1 + 1009 + + ) + +15 + #PPC603e_SPR_IBAT0U + 528 + + ) + +16 + #PPC603e_SPR_IBAT0L + 529 + + ) + +17 + #PPC603e_SPR_DBAT0U + 536 + + ) + +18 + #PPC603e_SPR_DBAT0L + 537 + + ) + +19 + #PPC603e_SPR_IBAT1U + 530 + + ) + +20 + #PPC603e_SPR_IBAT1L + 531 + + ) + +21 + #PPC603e_SPR_DBAT1U + 538 + + ) + +22 + #PPC603e_SPR_DBAT1L + 539 + + ) + +23 + #PPC603e_SPR_IBAT2U + 532 + + ) + +24 + #PPC603e_SPR_IBAT2L + 533 + + ) + +25 + #PPC603e_SPR_DBAT2U + 540 + + ) + +26 + #PPC603e_SPR_DBAT2L + 541 + + ) + +27 + #PPC603e_SPR_IBAT3U + 534 + + ) + +28 + #PPC603e_SPR_IBAT3L + 535 + + ) + +29 + #PPC603e_SPR_DBAT3U + 542 + + ) + +30 + #PPC603e_SPR_DBAT3L + 543 + + ) + +31 + #PPC603e_SPR_DMISS + 976 + + ) + +32 + #PPC603e_SPR_DCMP + 977 + + ) + +33 + #PPC603e_SPR_HASH1 + 978 + + ) + +34 + #PPC603e_SPR_HASH2 + 979 + + ) + +35 + #PPC603e_SPR_IMISS + 980 + + ) + +36 + #PPC603e_SPR_ICMP + 981 + + ) + +37 + #PPC603e_SPR_RPA + 982 + + ) + +38 + #PPC603e_SPR_SDR1 + 25 + + ) + +39 + #PPC603e_SPR_PVR + 287 + + ) + +40 + #PPC603e_SPR_DAR + 19 + + ) + +41 + #PPC603e_SPR_SPRG0 + 272 + + ) + +42 + #PPC603e_SPR_SPRG1 + 273 + + ) + +43 + #PPC603e_SPR_SPRG2 + 274 + + ) + +44 + #PPC603e_SPR_SPRG3 + 275 + + ) + +45 + #PPC603e_SPR_DSISR + 18 + + ) + +46 + #PPC603e_SPR_SRR0 + 26 + + ) + +47 + #PPC603e_SPR_SRR1 + 27 + + ) + +48 + #PPC603e_SPR_TBL_WRITE + 284 + + ) + +49 + #PPC603e_SPR_TBU_WRITE + 285 + + ) + +50 + #PPC603e_SPR_DEC + 22 + + ) + +51 + #PPC603e_SPR_IABR + 1010 + + ) + +52 + #PPC603e_SPR_EAR + 282 + + ) + +54 + #PCI_MEM_CMD + ( +SCORE603E_PCI_MEM_BASE + >> 16) + + ) + +57 +ut32_t + + mcou_1_100 +; + +58 +ut32_t + + mcou_hours +; + +59 +ut32_t + + mcou_m +; + +60 +ut32_t + + mcou_c +; + +61 +ut32_t + + mcou_mth +; + +62 +ut32_t + + mcou_de +; + +63 +ut32_t + + mcou_yr +; + +64 +ut32_t + + mcou_day_of_wk +; + +66 +ut32_t + + mRAM_1_100 +; + +67 +ut32_t + + mRAM_hours +; + +68 +ut32_t + + mRAM_mth +; + +69 +ut32_t + + mRAM_de +; + +70 +ut32_t + + mRAM_yr +; + +71 +ut32_t + + mRAM_day_of_wk +; + +73 +ut32_t + + mru_us_mask +; + +74 +ut32_t + + mcommd_gi +; + +75 } + tHris_RTC +; + +77 + $_RTC +( ) + +79 vީ +Hris_RTC + * +the_RTC +; + +81 +the_RTC + = (vީ +Hris_RTC + *) +BSP_RTC_ADDRESS +; + +83 +the_RTC +-> +commd_gi + = 0x0; + +84 + } +} + +86 + $_PCI +( ) + +90 + } +} + +92 + #PPC_G_HID0 + +_vue + ) \ + +94 +_vue + = 0; \ + +95 +__asm__ + volatile( \ + +98 : "" ( +_vue +) \ + +99 : "0" ( +_vue +) \ + +101 } 0) + + ) + +103 + #PPC_S_HID0 + +_vue + ) \ + +105 +__asm__ + volatile( \ + +109 : "" ( +_vue +) \ + +110 : "0" ( +_vue +) \ + +112 } 0) + + ) + +114 + $rui_che_ab + ( ) + +116 +ut32_t + +vue +; + +122 + `PPC_G_HID0 + +vue + ); + +124 +vue + |= 0x00008000; + +126 + `PPC_S_HID0 + +vue + ); + +127 + } +} + +129 + $da_che_ab + ( ) + +131 +ut32_t + +vue +; + +137 + `PPC_G_HID0 + +vue + ); + +139 +vue + |= 0x00004000; + +141 + `PPC_S_HID0 + +vue + ); + +142 + } +} + + @startup/bspstart.c + +14 + ~<rg.h +> + +16 + ~<b.h +> + +17 + ~<b/bord.h +> + +18 + ~<ems/libio.h +> + +19 + ~<ems/libcsut.h +> + +20 + ~<ems/bIo.h +> + +21 + ~<ems/cou.h +> + +22 + ~<libu/uIdt.h +> + +23 + ~<b/q.h +> + +25 + #DEBUG + 0 + + ) + +30 + gBSP_hp_t +; + +35 + gBSP_bus_equcy +; + +40 + gBSP_oss_equcy +; + +47 + gBSP_time_ba_divis + = 3960; + +52 +ut32_t + + gb_icks_r_uc +; + +57
+RamSize +[]; + +58 +ut32_t + + gBSP_mem_size +; + +60
+__ems_d +[]; + +62 + $BSP_nic +(* +s +) + +64 + `tk +("%PANIC %s\n", +_RTEMS_vsi +, +s +); + +65 +__asm__ + + `__vީe + ("sc"); + +66 + } +} + +68 + $_BSP_F_r +( +v +) + +70 + `tk +("%PANIC ERROR %x\n", +_RTEMS_vsi +, +v +); + +71 +__asm__ + + `__vީe + ("sc"); + +72 + } +} + +79 +_RTC +( ); + +80 +lize_PMC +( ); + +82 + $b_edriv_hook +( ) + +84 + `_PCI +(); + +85 + `lize_univ +(); + +87 #i +DEBUG + + +88 + `tk +("bsp_predriver_hook: initialize_PCI_bridge\n"); + +90 + `lize_PCI_bridge + (); + +92 #i( +HAS_PMC_PSC8 +) + +93 #i +DEBUG + + +94 + `tk +("bsp_predriver_hook: initialize_PMC\n"); + +96 + `lize_PMC +(); + +99 #i +DEBUG + + +100 + `tk +("bsp_predriver_hook: End ofoutine\n"); + +103 + } +} + +110 + $lize_PMC +( ) { + +111 vީ +ut32_t + * +PMC_addr +; + +112 +ut32_t + +da +; + +117 +PMC_addr + = + `BSP_PCI_DEVICE_ADDRESS +( 0x4 ); + +118 * +PMC_addr + = 0x020080cc; + +119 #i +DEBUG + + +120 + `tk +("lize_PMC: 0x%x = 0x%x\n", +PMC_addr +, 0x020080cc); + +126 +PMC_addr + = + `BSP_PCI_DEVICE_ADDRESS +( 0x14 ); + +127 * +PMC_addr + = ( +BSP_PCI_REGISTER_BASE + >> 24) & 0x3f; + +128 #i +DEBUG + + +129 + `tk +("lize_PMC: 0x%x = 0x%x\n", +PMC_addr +, (( +BSP_PCI_REGISTER_BASE + >> 24) & 0x3f)); + +132 +PMC_addr + = (vީ +ut32_t +*) + +133 + `BSP_PMC_SERIAL_ADDRESS +( 0x100000 ); + +134 +da + = * +PMC_addr +; + +135 #i +DEBUG + + +136 + `tk +("lize_PMC: Rd 0x%x (0x%x)\n", +PMC_addr +, +da + ); + +137 + `tk +("lize_PMC: Rd 0x%x (0x%x)\n", +PMC_addr +, +da + & 0xfc ); + +139 * +PMC_addr + = +da + & 0xfc; + +140 + } +} + +149 + $b_t +( ) + +151 +m_vue + = 0x0000; + +152 +u_t + +SckS +; + +153 +u_t + +SckSize +; + +154 +c_u_id_t + +myCpu +; + +155 +c_u_visi_t + +myCpuRevisi +; + +157 + `ems_b_day +( 1000 ); + +162 #i +DEBUG + + +163 + `tk +("bsp_start: Zero outots of memory\n"); + +166 +BSP_oss_equcy + = 266000000; + +167 +BSP_bus_equcy + = 66000000; + +174 +myCpu + = + `g_c_u_ty +(); + +175 +myCpuRevisi + = + `g_c_u_visi +(); + +176 + `tk +("Cpu: 0x%x Revisi: %d\n", +myCpu +, +myCpuRevisi +); + +177 + `tk +("Cpu %s\n", + `g_c_u_ty_me +( +myCpu +) ); + +182 +SckS + = ( +u_t + +__ems_d +; + +183 +SckSize + = + `ems_cfiguti_g_u_ack_size +(); + +184 + `tk +("Interrupt Stack Start: 0x%x Size: 0x%x Heap Start: 0x%x\n", + +185 +SckS +, +SckSize +, +BSP_hp_t + + +188 +BSP_mem_size + = ( +ut32_t + +RamSize +; + +189 + `tk +("BSP_mem_size: %p\n", +RamSize + ); + +194 + `c_exc_lize +( +SckS +, +SckSize +); + +196 +m_vue + = 0x2030; + +197 + `_CPU_MSR_SET + +m_vue + ); + +198 +__asm__ + volatile("sync; isync"); + +203 #i +DEBUG + + +204 + `tk +("bsp_start: set clicksoer usec\n"); + +206 +b_icks_r_uc + = 66 / 4; + +207 + `ems_cou_lize_cvr +( +b_icks_r_uc + * 1000000); + +209 #i +BSP_DATA_CACHE_ENABLED + + +210 #i +DEBUG + + +211 + `tk +("bsp_start: cache_enable\n"); + +213 + `rui_che_ab + (); + +214 + `da_che_ab + (); + +215 #i +DEBUG + + +216 + `tk +("bsp_start: END BSP_DATA_CACHE_ENABLED\n"); + +223 #i +DEBUG + + +224 + `tk +("bspstart: Call BSP_rtems_irq_mng_init\n"); + +226 + `BSP_ems_q_mng_ +(0); + +228 #i +DEBUG + + +229 + `tk +("bsp_start:nd BSPSTART\n"); + +230 + `ShowBATS +(); + +232 + } +} + + @startup/genpvec.c + +13 + ~<b.h +> + +14 + ~<ems/cha.h +> + +15 + ~<ems/bIo.h +> + +16 + ~<as.h +> + +18 + ~<dio.h +> + +24 +ems_i + +ex_exi_ISR + ( + +25 +ems_ve_numb + +ve + + +28 + #NUM_LIRQ_HANDLERS + 20 + + ) + +29 + #NUM_LIRQ + ( +MAX_BOARD_IRQS + - +PPC_IRQ_LAST + ) + + ) + +37 +ems_cha_node + + mNode +; + +38 +ems_i_y + + mhdr +; + +39 +ems_ve_numb + + mve +; + +40 } + tEE_ISR_Ty +; + +45 +EE_ISR_Ty + + gISR_Nodes + [ +NUM_LIRQ_HANDLERS +]; + +46 +ut16_t + + gNodes_Ud +; + +47 +ems_cha_cڌ + + gISR_Aay + [ +NUM_LIRQ +]; + +50 +_q_da_gi +( ); + +52 + $In_EE_mask_ +( ) + +54 + } +} + +60 +ems_i_y + + $t_EE_ve +( + +61 +ems_i_y + +hdr +, + +62 +ems_ve_numb + +ve + + +65 +ut16_t + +vec_idx + = +ve + - +Sce_IRQ_F +; + +66 +ut32_t + +dex +; + +68 + `as + ( +Nodes_Ud + < +NUM_LIRQ_HANDLERS +); + +75 +dex +=0 ; index < +Nodes_Ud + ; index++ ) { + +76 i +ISR_Nodes +[ +dex +]. +ve + == vector && + +77 +ISR_Nodes +[ +dex +]. +hdr + == handler ) + +78 +NULL +; + +85 +Nodes_Ud +++; + +87 +dex + = +Nodes_Ud + - 1; + +89 +ISR_Nodes +[ +dex +]. +hdr + = handler; + +90 +ISR_Nodes +[ +dex +]. +ve + = vector; + +95 + `ems_cha_nd +& +ISR_Aay +[ +vec_idx +], & +ISR_Nodes +[ +dex +]. +Node + ); + +100 + `unmask_q + +vec_idx + ); + +102 +NULL +; + +103 + } +} + +108 +ems_i + + $ex_exi_ISR + ( + +109 +ems_ve_numb + +ve + + +112 +ut16_t + +dex +; + +113 +EE_ISR_Ty + * +node +; + +114 +ut16_t + +vue +; + +115 #i( +HAS_PMC_PSC8 +) + +116 +ut16_t + +PMC_q +; + +117 +ut16_t + +check_q +; + +118 +ut16_t + +us_wd +; + +121 +dex + = + `ad_d_r_q +(); + +122 i +dex + > +NUM_LIRQ + ) { + +123 + `tk +"ERROR:: Invid iruumb (%02x)\n", +dex + ); + +127 #i( +HAS_PMC_PSC8 +) + +128 +PMC_q + = +SCORE603E_PCI_IRQ_0 + - +SCORE603E_IRQ00 +; + +130 i( +dex + = +PMC_q +) { + +131 +us_wd + = + `ad_d_r_PMC_q + +dex + ); + +133 +check_q += +SCORE603E_IRQ16 +; check_q<= +SCORE603E_IRQ19 +; check_irq++) { + +134 i + `Is_PMC_IRQ + +check_q +, +us_wd + )) { + +135 +dex + = +check_q + - +SCORE603E_IRQ00 +; + +136 +node + = ( +EE_ISR_Ty + *)( +ISR_Aay +[ +dex + ]. +f +); + +138 i + `ems_cha_is_ +& +ISR_Aay +[ +dex + ], ( *) +node + ) ) { + +139 + `tk + ("ERROR:: check %d iru %02d hani\n", +check_q +, +dex +); + +140 +vue + = + `g_q_mask +(); + +141 + `tk +(" Mask = %02x\n", +vue +); + +143 ! + `ems_cha_is_ +& +ISR_Aay +[ +dex + ], ( *) +node + ) ) { + +144 (* +node +-> +hdr +)node-> +ve + ); + +145 +node + = ( +EE_ISR_Ty + *node-> +Node +. +xt +; + +153 +node + = ( +EE_ISR_Ty + *)( +ISR_Aay +[ +dex + ]. +f +); + +154 i + `ems_cha_is_ +& +ISR_Aay +[ +dex + ], ( *) +node + ) ) { + +155 + `tk +"ERROR:: iru %02x hani\n", +dex +); + +156 +vue + = + `g_q_mask +(); + +157 + `tk +(" Mask = %02x\n", +vue +); + +160 ! + `ems_cha_is_ +& +ISR_Aay +[ +dex + ], ( *) +node + ) ) { + +161 (* +node +-> +hdr +)node-> +ve + ); + +162 +node + = ( +EE_ISR_Ty + *node-> +Node +. +xt +; + +166 + } +} + + @startup/vmeintr.c + +14 + ~<ems.h +> + +15 + ~<b.h +> + +16 + ~<ems/vme.h +> + +21 + $VME_u_Dib +( + +22 +VME_u_Mask + +mask + + +25 vީ +ut8_t + * +VME_u_ab +; + +26 +ut8_t + +vue +; + +28 +VME_u_ab + = 0; + +29 +vue + = * +VME_u_ab +; + +30 +vue + &~ +mask +; + +31 * +VME_u_ab + = +vue +; + +32 + } +} + +37 + $VME_u_Eb +( + +38 +VME_u_Mask + +mask + + +41 vީ +ut8_t + * +VME_u_ab +; + +42 +ut8_t + +vue +; + +44 +VME_u_ab + = 0; + +45 +vue + = * +VME_u_ab +; + +46 +vue + | +mask +; + +47 * +VME_u_ab + = +vue +; + +48 + } +} + + @timer/timer.c + +18 + ~<as.h +> + +20 + ~<b.h +> + +21 + ~<ems/btim.h +> + +23 +ut64_t + + gTim_driv_S_time +; + +25 +bo + + gbchmk_tim_fd_avage_ovhd +; + +31 + $bchmk_tim_lize +() + +38 +Tim_driv_S_time + = + `PPC_G_timeba_gi +(); + +39 + } +} + +45 +bchmk_tim_t + + $bchmk_tim_ad +() + +47 +ut64_t + +icks +; + +48 +ut64_t + +tٮ64 +; + +49 +ut32_t + +tٮ +; + +53 +icks + = + `PPC_G_timeba_gi +(); + +55 + `as + +icks + > +Tim_driv_S_time + ); + +57 +tٮ64 + = +icks + - +Tim_driv_S_time +; + +59 + `as + +tٮ64 + <= 0xffffffff ); + +61 +tٮ + = ( +ut32_t + +tٮ64 +; + +63 i +bchmk_tim_fd_avage_ovhd + = +ue + ) + +64 +tٮ +; + +66 i +tٮ + < +BSP_TIMER_LEAST_VALID + ) + +69 + `BSP_Cvt_deemr +( +tٮ + - +BSP_TIMER_AVG_OVERHEAD +); + +70 + } +} + +72 + $bchmk_tim_dib_subag_avage_ovhd +( + +73 +bo + +fd_ag + + +76 +bchmk_tim_fd_avage_ovhd + = +fd_ag +; + +77 + } +} + + @tod/tod.c + +14 + ~<ems.h +> + +15 + ~<tod.h +> + +16 + ~<b.h +> + +22 + #ICM1770_CRYSTAL_FREQ_32K + 0x00 + + ) + +23 + #ICM1770_CRYSTAL_FREQ_1M + 0x01 + + ) + +24 + #ICM1770_CRYSTAL_FREQ_2M + 0x02 + + ) + +25 + #ICM1770_CRYSTAL_FREQ_4M + 0x03 + + ) + +27 +ICM7170_GTOD +( + +28 vީ * +imc1770_gs +, + +29 +ut8_t + +icm1770_eq +, + +30 +ems_time_of_day + * +c_tod + + +32 +ICM7170_STOD +( + +33 vީ * +imc1770_gs +, + +34 +ut8_t + +icm1770_eq +, + +35 +ems_time_of_day + * +c_tod + + +43 + $tRlTimeToRTEMS +() + +45 +ems_time_of_day + +c_tod +; + +47 + `ICM7170_GTOD + +BSP_RTC_ADDRESS +, +BSP_RTC_FREQUENCY +, & +c_tod + ); + +48 + `ems_ock_t +& +c_tod + ); + +49 + } +} + +51 + $tRlTimeFromRTEMS +() + +53 +ems_time_of_day + +ems_tod +; + +55 + `ems_ock_g + +RTEMS_CLOCK_GET_TOD +, & +ems_tod + ); + +56 + `ICM7170_STOD + +BSP_RTC_ADDRESS +, +BSP_RTC_FREQUENCY +, & +ems_tod + ); + +57 + } +} + +59 + $checkRlTime +() + +61 +ems_time_of_day + +ems_tod +; + +62 +ems_time_of_day + +c_tod +; + +64 + `ICM7170_GTOD + +BSP_RTC_ADDRESS +, +BSP_RTC_FREQUENCY +, & +c_tod + ); + +65 + `ems_ock_g + +RTEMS_CLOCK_GET_TOD +, & +ems_tod + ); + +67 if +ems_tod +. +yr + = +c_tod +.year && + +68 +ems_tod +. +mth + = +c_tod +.month && + +69 +ems_tod +. +day + = +c_tod +.day ) { + +70 (( +ems_tod +. +hour + - +c_tod +.hour) * 3600) + + +71 (( +ems_tod +. +mu + - +c_tod +.minute) * 60) + + +72 ( +ems_tod +. +cd + - +c_tod +.second); + +75 + } +} + +82 + $ICM7170_GFld +( + +83 vީ * +imc1770_gs +, + +84 +g + + +87 +x +; + +89 +x + = +imc1770_gs +[ +g +*4]; + +91 +x +; + +92 + } +} + +94 + $ICM7170_SFld +( + +95 vީ * +imc1770_gs +, + +96 +g +, + +97 +d + + +100 +imc1770_gs +[ +g +*4] = +d +; + +101 + } +} + +103 + $ICM7170_GTOD +( + +104 vީ * +imc1770_gs +, + +105 +ut8_t + +icm1770_eq +, + +106 +ems_time_of_day + * +c_tod + + +109 +yr +; + +110 +uc +; + +111 +bo + + + = +ue +; + +114 i( + + ) { + +115 + `ICM7170_SFld + +imc1770_gs +, 0x11, (0x0| +icm1770_eq +) ); + +116 + + = +l +; + +122 +uc + = + `ICM7170_GFld + +imc1770_gs +, 0x00 ); + +124 +yr + = + `ICM7170_GFld + +imc1770_gs +, 0x06 ); + +125 i +yr + >= 88 ) + +126 +yr + += 1900; + +128 +yr + += 2000; + +130 +c_tod +-> +yr + = year; + +131 +c_tod +-> +mth + = + `ICM7170_GFld + +imc1770_gs +, 0x04 ); + +132 +c_tod +-> +day + = + `ICM7170_GFld + +imc1770_gs +, 0x05 ); + +133 +c_tod +-> +hour + = + `ICM7170_GFld + +imc1770_gs +, 0x01 ); + +134 +c_tod +-> +mu + = + `ICM7170_GFld + +imc1770_gs +, 0x02 ); + +135 +c_tod +-> +cd + = + `ICM7170_GFld + +imc1770_gs +, 0x03 ); + +136 +c_tod +-> +ticks + = + `ICM7170_GFld + +imc1770_gs +, 0x00 ); + +137 + } +} + +139 + $ICM7170_STOD +( + +140 vީ * +imc1770_gs +, + +141 +ut8_t + +icm1770_eq +, + +142 +ems_time_of_day + * +c_tod + + +145 +yr +; + +147 +yr + = +c_tod +->year; + +148 i +yr + >= 2088 ) + +149 + `ems_l_r_occued +( 0xBAD0BAD0 ); + +151 i +yr + >= 2000 ) + +152 +yr + -= 2000; + +154 +yr + -= 1900; + +156 + `ICM7170_SFld + +imc1770_gs +, 0x11, (0x04 | +icm1770_eq + ) ); + +158 + `ICM7170_SFld + +imc1770_gs +, 0x06, +yr + ); + +159 + `ICM7170_SFld + +imc1770_gs +, 0x04, +c_tod +-> +mth + ); + +160 + `ICM7170_SFld + +imc1770_gs +, 0x05, +c_tod +-> +day + ); + +161 + `ICM7170_SFld + +imc1770_gs +, 0x01, +c_tod +-> +hour + ); + +162 + `ICM7170_SFld + +imc1770_gs +, 0x02, +c_tod +-> +mu + ); + +163 + `ICM7170_SFld + +imc1770_gs +, 0x03, +c_tod +-> +cd + ); + +169 + `ICM7170_SFld + +imc1770_gs +, 0x07, 1 ); + +171 + `ICM7170_SFld + +imc1770_gs +, 0x11, (0x0| +icm1770_eq +) ); + +172 + } +} + + @vme/VMEConfig.h + +1 #ide +RTEMS_BSP_VME_CONFIG_H + + +2 + #RTEMS_BSP_VME_CONFIG_H + + + ) + +63 #unde +BSP_VME_BAT_IDX + + +65 + #_VME_A32_WIN0_ON_PCI + 0x10000000 + + ) + +66 + #_VME_A24_ON_PCI + 0x1f000000 + + ) + +67 + #_VME_A16_ON_PCI + 0x1fff0000 + + ) + +72 + #_VME_A32_WIN0_ON_VME + 0x20000000 + + ) + +78 #unde +_VME_DRAM_OFFSET + + +85 #unde +_VME_CSR_ON_PCI + + +87 #unde +BSP_PCI_VME_DRIVER_DOES_EOI + + +89
+BSP_VMEIn +(); + +90
+BSP_VMEIrqMgrInl +(); + +92 + #BSP_VME_UNIVERSE_INSTALL_IRQ_MGR +( +r +) \ + +94 +r + = + `vmeUnivInlIrqMgr +(0,5,1,6); \ + +95 } 0) + + ) + + @ +1 +. +0 +24 +370 +PCI_bus/PCI.c +PCI_bus/PCI.h +PCI_bus/flash.c +PCI_bus/universe.c +console/85c30.c +console/85c30.h +console/console.c +console/consolebsp.h +console/tbl85c30.c +include/bsp.h +include/gen2.h +include/tm27.h +irq/FPGA.c +irq/irq.c +irq/irq.h +irq/irq_init.c +irq/no_pic.c +startup/Hwr_init.c +startup/bspstart.c +startup/genpvec.c +startup/vmeintr.c +timer/timer.c +tod/tod.c +vme/VMEConfig.h diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h index f6e3c5abce..dc78498a47 100644 --- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h @@ -1,8 +1,9 @@ -/* bsp.h - * +/* * This include file contains all board IO definitions. - * - * COPYRIGHT (c) 1989-2009. + */ + +/* + * COPYRIGHT (c) 1989-2014. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -123,68 +124,55 @@ rtems_isr_entry set_EE_vector( rtems_isr_entry handler, /* isr routine */ rtems_vector_number vector /* vector number */ ); -void initialize_external_exception_vector (); +void initialize_external_exception_vector(void); /* * Hwr_init.c */ -void init_PCI(); -void instruction_cache_enable (); -void data_cache_enable (); +void init_PCI(void); +void init_RTC(void); +void instruction_cache_enable(void); +void data_cache_enable(void); -void initialize_PCI_bridge (); -uint16_t read_and_clear_irq (); -void set_irq_mask( - uint16_t value -); -uint16_t get_irq_mask(); +void initialize_PCI_bridge(void); +uint16_t read_and_clear_irq(void); +void set_irq_mask(uint16_t value); +uint16_t get_irq_mask(void); /* * universe.c */ -void initialize_universe(); - -void set_irq_mask( - uint16_t value -); - -uint16_t get_irq_mask(); - -void unmask_irq( - uint16_t irq_idx -); - -void mask_irq( - uint16_t irq_idx -); - -void init_irq_data_register(); - -uint16_t read_and_clear_PMC_irq( - uint16_t irq -); - -bool Is_PMC_IRQ( - uint32_t pmc_irq, - uint16_t status_word -); - -uint16_t read_and_clear_irq(); +void initialize_universe(void); +void set_irq_mask(uint16_t value); +uint16_t get_irq_mask(void); +void unmask_irq(uint16_t irq_idx); +void mask_irq(uint16_t irq_idx); +void init_irq_data_register(void); +uint16_t read_and_clear_PMC_irq(uint16_t irq); +bool Is_PMC_IRQ( uint32_t pmc_irq, uint16_t status_word); +uint16_t read_and_clear_irq(void); +void set_vme_base_address(uint32_t base_address); +uint32_t get_vme_slave_size(void); +void set_vme_slave_size (uint32_t size); /* * FPGA.c */ -void initialize_PCI_bridge (); +void initialize_PCI_bridge(void); +void init_irq_data_register(void); +uint32_t Read_pci_device_register(uint32_t address); +void Write_pci_device_register(uint32_t address, uint32_t data); /* flash.c */ +unsigned int SCORE603e_FLASH_Disable(uint32_t unused); +unsigned int SCORE603e_FLASH_verify_enable(void); +unsigned int SCORE603e_FLASH_Enable_writes(uint32_t area); -unsigned int SCORE603e_FLASH_Disable( - uint32_t unused -); -unsigned int SCORE603e_FLASH_verify_enable(); -unsigned int SCORE603e_FLASH_Enable_writes( - uint32_t area /* Unused */ -); +/* + * PCI.c + */ +uint32_t PCI_bus_read(volatile uint32_t *_addr); +void PCI_bus_write(volatile uint32_t *_addr, uint32_t _data); #define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area ) #define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area ) diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c index 33e22de886..9c08d1d7de 100644 --- a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c +++ b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c @@ -1,6 +1,9 @@ -/* FPGA.c -- Bridge for second and subsequent generations - * - * COPYRIGHT (c) 1989-2009. +/* + * FPGA.c -- Bridge for second and subsequent generations + */ + +/* + * COPYRIGHT (c) 1989-2014. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -120,7 +123,7 @@ void init_irq_data_register(void) } } -uint16_t read_and_clear_PMC_irq( +uint16_t read_and_clear_PMC_irq( uint16_t irq ) { |