2007-09-07 Kate Feng <feng1@bnl.gov>

	* ChangeLog, Makefile.am, README, README.booting, README.irq,
	preinstall.am, GT64260/MVME5500I2C.c, include/bsp.h, irq/irq.c,
	irq/irq.h, irq/irq_init.c, pci/detect_host_bridge.c, pci/pci.c,
	pci/pci_interface.c, pci/pcifinddevice.c, start/preload.S,
	startup/bspclean.c, startup/bspstart.c, startup/pgtbl_activate.c,
	startup/reboot.c, vectors/bspException.h, vectors/exceptionhandler.c:
	Merge my improvements in this BSP including a new network
	driver for the 1GHz NIC.
	* network/if_100MHz/GT64260eth.c, network/if_100MHz/GT64260eth.h,
	network/if_100MHz/GT64260ethreg.h, network/if_100MHz/Makefile.am,
	network/if_1GHz/Makefile.am, network/if_1GHz/POSSIBLEBUG,
	network/if_1GHz/if_wm.c, network/if_1GHz/if_wmreg.h,
	network/if_1GHz/pci_map.c, network/if_1GHz/pcireg.h: New files.

3 files changed, 449 insertions, 407 deletions

diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c
index 838585b9e7..a4a82448f4 100644
--- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c
@@ -6,14 +6,20 @@
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
+ *  http://www.OARcorp.com/rtems/license.html.
  *
- *  Special acknowledgement to Till Straumann <strauman@slac.stanford.edu>
- *  for providing inputs to the IRQ handling and optimization.
+ *  Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>
+ *  for some inputs.
  *
- *  Modified and added support for the MVME5500 board
- *  Copyright 2003, 2004, Shuchen Kate Feng <feng1@bnl.gov>,
+ *  Copyright 2003, 2004, 2005, 2007  Shuchen Kate Feng <feng1@bnl.gov>,
  *                  NSLS,Brookhaven National Laboratory
+ *  1) Modified and added support for the MVME5500 board.
+ *  2) The implementation of picIsrTable[] is an original work by the
+ *     author to optimize the software IRQ priority scheduling because
+ *     Discovery controller does not provide H/W IRQ priority schedule. 
+ *     It ensures the fastest/faster interrupt service to the
+ *     highest/higher priority IRQ, if pendig.
+ *  3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
  *
  */
   
@@ -23,7 +29,9 @@
 #include <rtems/score/thread.h>
 #include <rtems/score/apiext.h>
 #include <libcpu/raw_exception.h>
+#include <rtems/rtems/intr.h>
 #include <libcpu/io.h>
+#include <libcpu/byteorder.h>
 #include <bsp/vectors.h>
 
 #include <rtems/bspIo.h> /* for printk */
@@ -31,20 +39,35 @@
 
 #define HI_INT_CAUSE 0x40000000
 
-/*#define DEBUG*/
+#define MAX_IRQ_LOOP 30
 
-int gpp_int_error =0;
+#define EDGE_TRIGGER
+
+#define _MSR_GET( _mask) \
+  do { \
+     RTEMS_COMPILER_MEMORY_BARRIER(); \
+     _CPU_MSR_GET( _mask); \
+     RTEMS_COMPILER_MEMORY_BARRIER(); \
+  } while (0);
+
+#define _MSR_SET( _mask) \
+  do { \
+     RTEMS_COMPILER_MEMORY_BARRIER(); \
+     _CPU_MSR_SET( _mask); \
+     RTEMS_COMPILER_MEMORY_BARRIER(); \
+  } while (0);
+
+/* #define DEBUG_IRQ*/
 
 /*
  * pointer to the mask representing the additionnal irq vectors
  * that must be disabled when a particular entry is activated.
- * They will be dynamically computed from teh prioruty table given
+ * They will be dynamically computed from the table given
  * in BSP_rtems_irq_mngt_set();
  * CAUTION : this table is accessed directly by interrupt routine
  * 	     prologue.
  */
-static unsigned int irq_prio_maskLO_tbl[BSP_MAIN_IRQ_NUMBER];
-static unsigned int irq_prio_maskHI_tbl[BSP_MAIN_IRQ_NUMBER];
+static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];
 
 /*
  * default handler connected on each irq after bsp initialization
@@ -58,26 +81,55 @@ static rtems_irq_connect_data	default_rtems_entry;
 static rtems_irq_global_settings* 	internal_config;
 static rtems_irq_connect_data*		rtems_hdl_tbl;
 
-static unsigned int irqCAUSE[20], irqLOW[20], irqHIGH[20];
-static int irqIndex=0;
+static volatile unsigned  *BSP_irqMask_reg[3];
+static volatile unsigned  *BSP_irqCause_reg[3];
+static volatile unsigned  BSP_irqMask_cache[3]={0,0,0}; 
 
-/*
- * Check if IRQ is a MAIN CPU internal IRQ 
+
+static int picIsrTblPtr=0;
+static unsigned int GPPIrqInTbl=0;
+static unsigned long long MainIrqInTbl=0;
+
+/* 
+ * The software developers are forbidden to setup picIsrTable[],
+ * as it is a powerful engine for the BSP to find the pending
+ * highest priority IRQ at run time.  It ensures the fastest/faster
+ * interrupt service to the highest/higher priority IRQ, if pendig.
+ *
+ * The picIsrTable[96] is updated dynamically at run time
+ * based on the priority levels set at BSPirqPrioTable[96],
+ * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()
+ * commands are invoked.
+ *
+ * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt 
+ * numbers [0 (lowest)- 95 (highest)] starting from the highest priority
+ * one to the lowest priority one. The highest priority interrupt is
+ * located at picIsrTable[0], and the lowest priority interrupt is located
+ * at picIsrTable[picIsrTblPtr-1].
+ *
+ *
  */
-static inline int is_main_irq(const rtems_irq_number irqLine)
-{
-  return (((int) irqLine <= BSP_MICH_IRQ_MAX_OFFSET) &
-	  ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET)
-	 );
-}
+/* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */ 
+static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={  
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1 };
+
 
 /*
- * Check if IRQ is a GPP IRQ
+ * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ
  */
-static inline int is_gpp_irq(const rtems_irq_number irqLine)
+static inline int is_pic_irq(const rtems_irq_number irqLine)
 {
   return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &
-	  ((int) irqLine >= BSP_GPP_IRQ_LOWEST_OFFSET)
+	  ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET)
 	 );
 }
 
@@ -91,104 +143,14 @@ static inline int is_processor_irq(const rtems_irq_number irqLine)
 	 );
 }
 
-#define GT_GPP_Int1_Cause GT_GPP_Interrupt_Cause+1
-#define GT_GPP_Int2_Cause GT_GPP_Interrupt_Cause+2
-#define GT_GPP_Int3_Cause GT_GPP_Interrupt_Cause+3
-
-void GT_GPP_IntHandler0()
+static inline unsigned int divIrq32(unsigned irq)
 {
-
-  unsigned  gppCause, irqNum, bitNum;
-  int i, found=0;
-
-  gppCause = inb(GT_GPP_Interrupt_Cause) & GT_GPPirq_cache;
-
-  for (i=0; GPP7_0IrqTbl[i]!=-1;i++){
-    bitNum =GPP7_0IrqTbl[i];
-    if (gppCause & (1<<bitNum)) {
-        /* Clear the GPP interrupt cause bit */
-      outb( ~(1<<bitNum), GT_GPP_Interrupt_Cause);/* Till Straumann */
-        found = 1; 
-        irqNum = bitNum+BSP_GPP_IRQ_LOWEST_OFFSET;
-        /* call the necessary interrupt handlers */
-        if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
-	   rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
-        else
-	   gpp_int_error= bitNum; /*GPP interrupt bitNum not connected */
-    }
-  }
-  if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
+  return(irq/32);
 }
 
-void GT_GPP_IntHandler1()
+static inline unsigned int modIrq32(unsigned irq)
 {
-  unsigned  gppCause, irqNum, bitNum;
-  int i, found=0;
-
-  gppCause = inb(GT_GPP_Int1_Cause) & (GT_GPPirq_cache>>8);
-
-  for (i=0; GPP15_8IrqTbl[i]!=-1;i++){
-    bitNum =GPP15_8IrqTbl[i];
-    if (gppCause & (1<<bitNum)) {
-        /* Clear the GPP interrupt cause bit */
-        outb( ~(1<<bitNum), GT_GPP_Int1_Cause); /* Till Straumann */
-        found = 1; 
-        irqNum = bitNum+BSP_GPP8_IRQ_OFFSET;
-        /* call the necessary interrupt handlers */
-        if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
-	   rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
-        else
-	   gpp_int_error= bitNum+8; /*GPP interrupt bitNum not connected */
-    }
-  }
-  if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
-}
-void GT_GPP_IntHandler2()
-{
-  unsigned  gppCause, irqNum, bitNum;
-  int i, found=0;
-
-  gppCause = inb(GT_GPP_Int2_Cause) & (GT_GPPirq_cache>>16);
-
-  for (i=0; GPP23_16IrqTbl[i]!=-1;i++){
-    bitNum =GPP23_16IrqTbl[i];
-    if (gppCause & (1<<bitNum)) {
-        /* Clear the GPP interrupt cause bit */
-        outb( ~(1<<bitNum), GT_GPP_Int2_Cause);
-        found = 1; 
-        irqNum = bitNum+BSP_GPP16_IRQ_OFFSET;
-        /* call the necessary interrupt handlers */
-        if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
-	    rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
-        else
-	   gpp_int_error= bitNum+16; /*GPP interrupt bitNum not connected */
-    }
-  }
-  if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
-}
-
-void GT_GPP_IntHandler3()
-{
-  unsigned  gppCause, irqNum, bitNum;
-  int i, found=0;
-
-  gppCause = inb(GT_GPP_Int3_Cause) & (GT_GPPirq_cache>>24);
-
-  for (i=0; GPP31_24IrqTbl[i]!=-1;i++){
-    bitNum=GPP31_24IrqTbl[i];
-    if (gppCause & (1<<bitNum)) {
-        /* Clear the GPP interrupt cause bit */
-        outb(~(1<<bitNum), GT_GPP_Int3_Cause);
-        found = 1; 
-        irqNum = bitNum+BSP_GPP24_IRQ_OFFSET;
-        /* call the necessary interrupt handlers */
-        if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
-	    rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
-        else
-	   gpp_int_error= bitNum+24; /*GPP interrupt bitNum not connected */
-    }
-  }
-  if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
+   return(irq%32);
 }
 
 /*
@@ -200,33 +162,253 @@ void GT_GPP_IntHandler3()
  * is already set and that the tables it contains are still valid
  * and accessible.
  */
-static void compute_GT64260int_masks_from_prio ()
+static void compute_pic_masks_from_prio()
 {
-  int i,j;
+  int i,j, k;
   unsigned long long irq_prio_mask=0;
 
   /*
    * Always mask at least current interrupt to prevent re-entrance
    */
-  for (i=0; i <BSP_MAIN_IRQ_NUMBER; i++) {
-    irq_prio_mask = (unsigned long long) (1LLU << i);
+  for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) {
+    switch(i) {
+      case BSP_MAIN_GPP7_0_IRQ:
+      case BSP_MAIN_GPP15_8_IRQ:
+      case BSP_MAIN_GPP23_16_IRQ:
+      case BSP_MAIN_GPP31_24_IRQ:
+	for (k=0; k< 3; k++)
+	    BSP_irq_prio_mask_tbl[k][i]=0;
+
+        irq_prio_mask =0;
+        break;
+      default : 
+        irq_prio_mask = (unsigned long long) (1LLU << i);
+	break;
+    }
+    
+    if (irq_prio_mask) {
     for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
-      /*
-       * Mask interrupts at GT64260int level that have a lower priority
-       * or <Till Straumann> a equal priority. 
-       */
-      if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j]) {
-	 irq_prio_mask |= (unsigned long long)(1LLU << j);
-      }
+        /*
+         * Mask interrupts at PIC level that have a lower priority
+         * or <Till Straumann> a equal priority. 
+         */
+        if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
+	   irq_prio_mask |= (unsigned long long)(1LLU << j);
     }
+    
 
-    irq_prio_maskLO_tbl[i] = irq_prio_mask & 0xffffffff;
-    irq_prio_maskHI_tbl[i] = (irq_prio_mask>>32) & 0xffffffff;
+    BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
+    BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
 #ifdef DEBUG
-    printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,irq_prio_maskHI_tbl[i],
-	   irq_prio_maskLO_tbl[i]);
-#endif  
+    printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
+	   BSP_irq_prio_mask_tbl[0][i]);
+#endif 
+
+    BSP_irq_prio_mask_tbl[2][i] = 1<<i;
+    /* Compute for the GPP priority interrupt mask */
+    for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {      
+      if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
+	   BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET); 
+    }
+    }
+  }
+}
+
+
+static void UpdateMainIrqTbl(int irqNum)
+{
+  int i=0, j, shifted=0;
+
+  switch (irqNum) {
+    case BSP_MAIN_GPP7_0_IRQ:
+    case BSP_MAIN_GPP15_8_IRQ:
+    case BSP_MAIN_GPP23_16_IRQ:
+    case BSP_MAIN_GPP31_24_IRQ:  
+      return;  /* Do nothing, let GPP take care of it */
+      break;
   }
+#ifdef SHOW_MORE_INIT_SETTINGS
+  unsigned long val2, val1;
+#endif
+
+  /* If entry not in table*/
+  if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) && 
+        (!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) ||
+       ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && 
+        (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
+  { 
+      while ( picIsrTable[i]!=-1) {
+        if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {
+          /* all other lower priority entries shifted right */
+          for (j=picIsrTblPtr;j>i; j--) 
+              picIsrTable[j]=picIsrTable[j-1];
+          picIsrTable[i]=irqNum;
+          shifted=1;
+          break;
+       }
+       i++;
+     }
+     if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;
+     if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
+        GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 
+     else      
+        MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
+     picIsrTblPtr++;
+  }
+#ifdef SHOW_MORE_INIT_SETTINGS
+  val2 = (MainIrqInTbl>>32) & 0xffffffff;
+  val1 = MainIrqInTbl&0xffffffff;
+  printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1); 
+  BSP_printPicIsrTbl();
+#endif
+
+}
+
+
+static void CleanMainIrqTbl(int irqNum)
+{
+  int i, j;
+
+  switch (irqNum) {
+    case BSP_MAIN_GPP7_0_IRQ:
+    case BSP_MAIN_GPP15_8_IRQ:
+    case BSP_MAIN_GPP23_16_IRQ:
+    case BSP_MAIN_GPP31_24_IRQ: 
+      return;  /* Do nothing, let GPP take care of it */
+      break;  
+  }
+  if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) && 
+        ((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) ||
+       ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && 
+        (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))
+  { /* If entry in table*/
+     for (i=0; i<64; i++) {
+       if (picIsrTable[i]==irqNum) {/*remove it from the entry */
+          /* all other lower priority entries shifted left */
+          for (j=i;j<picIsrTblPtr; j++) 
+              picIsrTable[j]=picIsrTable[j+1];
+          if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
+            GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 
+          else      
+            MainIrqInTbl &= ~(1LLU << irqNum);
+          picIsrTblPtr--;
+          break;
+       }
+     }
+  }
+}
+
+void BSP_enable_pic_irq(const rtems_irq_number irqNum)
+{
+  unsigned bitNum, regNum;
+  unsigned int level;
+
+  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+
+  rtems_interrupt_disable(level); 
+
+  UpdateMainIrqTbl((int) irqNum);
+  BSP_irqMask_cache[regNum] |= (1 << bitNum);
+
+  out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
+  while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
+
+  rtems_interrupt_enable(level);
+}
+
+void BSP_disable_pic_irq(const rtems_irq_number irqNum)
+{
+  unsigned bitNum, regNum;
+  unsigned int level;
+
+  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+
+  rtems_interrupt_disable(level); 
+
+  CleanMainIrqTbl((int) irqNum);
+  BSP_irqMask_cache[regNum] &=  ~(1 << bitNum);
+
+  out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
+  while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
+
+  rtems_interrupt_enable(level);
+}
+
+int BSP_setup_the_pic()  /* adapt the same name as shared/irq */
+{
+    int i;
+
+    /* Get ready for discovery BSP */
+    BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);
+    BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);
+    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);
+
+    BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);
+    BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);
+    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);
+
+#ifdef EDGE_TRIGGER
+
+    /* Page 401, Table 598:
+     * Comm Unit Arbiter Control register :
+     * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
+     * We set the GPP interrupts to be edge sensitive.
+     * MOTload default is set as level sensitive(1).
+     */
+    outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
+#else
+    outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);
+#endif
+
+#if 0
+    printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 
+	   in_le32(BSP_irqMask_reg[0]),
+	   in_le32(BSP_irqCause_reg[0]));
+    printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", 
+	   in_le32(BSP_irqMask_reg[1]),
+	   in_le32(BSP_irqCause_reg[1]));
+    printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", 
+	   in_le32(BSP_irqMask_reg[2]),
+	   in_le32(BSP_irqCause_reg[2]));
+#endif
+
+    /* Initialize the interrupt related GT64260 registers */
+    for (i=0; i<3; i++) {
+      out_le32(BSP_irqCause_reg[i], 0);
+      out_le32(BSP_irqMask_reg[i], 0);
+    }         
+    in_le32(BSP_irqMask_reg[2]);
+    compute_pic_masks_from_prio();
+
+#if 0
+    printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 
+	   in_le32(BSP_irqMask_reg[0]),
+	   in_le32(BSP_irqCause_reg[0]));
+    printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", 
+	   in_le32(BSP_irqMask_reg[1]),
+	   in_le32(BSP_irqCause_reg[1]));
+    printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", 
+	   in_le32(BSP_irqMask_reg[2]),
+	   in_le32(BSP_irqCause_reg[2]));
+#endif
+
+    /*
+     * 
+     */
+    for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
+      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+	BSP_enable_pic_irq(i);
+	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
+      }
+      else {
+	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
+	BSP_disable_pic_irq(i);
+      }
+    }
+
+    return(1);
 }
 
 /*
@@ -247,7 +429,7 @@ static int isValidInterrupt(int irq)
 
 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
-    rtems_interrupt_level       level;
+    unsigned int level;
   
     if (!isValidInterrupt(irq->name)) {
       printk("Invalid interrupt vector %d\n",irq->name);
@@ -271,33 +453,31 @@ int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
      * store the data provided by user
      */
     rtems_hdl_tbl[irq->name] = *irq;
+#ifdef BSP_SHARED_HANDLER_SUPPORT
+    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
+#endif
 
-    if (is_main_irq(irq->name)) {
+    if (is_pic_irq(irq->name)) {
       /*
-       * Enable (internal ) Main Interrupt Cause Low and High
+       * Enable PIC  irq : Main Interrupt Cause Low and High & GPP external
        */
 #ifdef DEBUG_IRQ
-      printk("main irq %d\n",irq->name);
+      printk("PIC irq %d\n",irq->name);
 #endif
-      BSP_enable_main_irq(irq->name);
-    }
-    
-    if (is_gpp_irq(irq->name)) {
-      /*
-       * Enable (external) GPP[x] interrupt 
-       */
-      BSP_enable_gpp_irq((int) irq->name);
+      BSP_enable_pic_irq(irq->name);
     }
+    else {
+      if (is_processor_irq(irq->name)) {
+         /*
+          * Enable exception at processor level
+          */
 
-    if (is_processor_irq(irq->name)) {
-      /*
-       * Enable exception at processor level
-       */
+       }
     }
     /*
      * Enable interrupt on device
-     
-    irq->on(irq);*/
+     */
+    irq->on(irq);
     
     rtems_interrupt_enable(level);
 
@@ -316,7 +496,7 @@ int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
 
 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
-    rtems_interrupt_level       level;
+    unsigned int level;
   
     if (!isValidInterrupt(irq->name)) {
       return 0;
@@ -333,22 +513,17 @@ int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
     }
     rtems_interrupt_disable(level);
 
-    if (is_main_irq(irq->name)) {
-      /*
-       * disable CPU main interrupt
-       */
-      BSP_disable_main_irq(irq->name);
-    }
-    if (is_gpp_irq(irq->name)) {
-      /*
-       * disable external interrupt
-       */
-      BSP_disable_gpp_irq(irq->name);
-    }
-    if (is_processor_irq(irq->name)) {
-      /*
-       * disable exception at processor level
-       */
+    /*
+     * disable PIC interrupt
+     */
+    if (is_pic_irq(irq->name))
+      BSP_disable_pic_irq(irq->name);
+    else {
+      if (is_processor_irq(irq->name)) {
+         /*
+          * disable exception at processor level
+          */
+       }
     }    
 
     /*
@@ -361,6 +536,7 @@ int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
      */
     rtems_hdl_tbl[irq->name] = default_rtems_entry;
 
+
     rtems_interrupt_enable(level);
 
     return 1;
@@ -372,60 +548,26 @@ int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 
 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
 {
-    int                    i;
-    rtems_interrupt_level  level;
+    unsigned int level;
+    int i;
 
-    /*
-     * Store various code accelerators
-     */
+   /*
+    * Store various code accelerators
+    */
     internal_config 		= config;
     default_rtems_entry 	= config->defaultEntry;
     rtems_hdl_tbl 		= config->irqHdlTbl;
 
     rtems_interrupt_disable(level);
-    compute_GT64260int_masks_from_prio();
 
-    /*
-     * set up internal tables used by rtems interrupt prologue
-     */
-    /*
-     * start with MAIN CPU IRQ
-     */
-    for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_GPP_IRQ_LOWEST_OFFSET ; i++) {
-      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-	BSP_enable_main_irq(i);
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-      }
-      else {
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-	BSP_disable_main_irq(i);
-      }
-    }
-    /*
-     * continue with  external IRQ
-     */
-    for (i=BSP_GPP_IRQ_LOWEST_OFFSET; i<BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i++) {
-      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-	BSP_enable_gpp_irq(i);
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-      }
-      else {
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-	BSP_disable_gpp_irq(i);
-      }
+    if ( !BSP_setup_the_pic() ) {
+       printk("PIC setup failed; leaving IRQs OFF\n");
+       return 0;
     }
 
-    /*
-     * finish with Processor exceptions handled like IRQ
-     */
-    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_MAX_OFFSET+1; i++) {
-      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-      }
-      else {
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-      }
-    }
+    for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++) 
+      BSP_enable_pic_irq(i);
+
     rtems_interrupt_enable(level);
     return 1;
 }
@@ -436,85 +578,74 @@ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
     return 0;
 }    
 
-int _BSP_vme_bridge_irq = -1;
-
 /*
  * High level IRQ handler called from shared_raw_irq_code_entry
  */
+
 void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
 {
-  register unsigned msr;
-  register unsigned new_msr;
-  unsigned mainCause[2];
-  register unsigned selectCause;
-  register unsigned oldMask[2]={0,0};
-  unsigned i, regNum, irq, bitNum, startIrqNum=0;
+  register unsigned msr, new_msr;
+  unsigned long irqCause[3]={0, 0,0};
+  register unsigned long selectCause;
+  unsigned oldMask[3]={0,0,0};
+  register unsigned i=0, j, irq=0, bitmask=0, group=0;
 
   if (excNum == ASM_DEC_VECTOR) {
-    _CPU_MSR_GET(msr);
+    _MSR_GET(msr);
     new_msr = msr | MSR_EE;
-    _CPU_MSR_SET(new_msr);
+    _MSR_SET(new_msr);
     
     rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
 
-    _CPU_MSR_SET(msr);
+    _MSR_SET(msr);
     return;
     
   }
-  selectCause = inl( GT_CPU_SEL_CAUSE); 
-  if (selectCause & HI_INT_CAUSE ) {
-    mainCause[1]= selectCause & inl(GT_CPU_INT_MASK_HI);
-    startIrqNum=32;
+
+  for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
+
+  if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){
+    irqCause[1] = (selectCause & BSP_irqMask_cache[1]);
+    irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
   }
   else {
-    mainCause[0] =inl(GT_MAIN_INT_CAUSE_LO)&inl(GT_CPU_INT_MASK_LO);
-    mainCause[1] =inl(GT_MAIN_INT_CAUSE_HI)&inl(GT_CPU_INT_MASK_HI);
+    irqCause[0] = (selectCause & BSP_irqMask_cache[0]);
+    if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))
+       irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
   }
-
-#if 0
-  /* very bad practice to put printk here, use only if for debug */
-  printk("main 0 %x, main 1 %x \n", mainCause[0],mainCause[1]);
+  
+  while ((irq = picIsrTable[i++])!=-1)
+  {
+    if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {
+      for (j=0; j<3; j++)
+        BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
+
+      RTEMS_COMPILER_MEMORY_BARRIER();
+      out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);
+      out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);
+      out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);
+      in_le32((volatile unsigned *)0xf100f10c);
+
+#ifdef EDGE_TRIGGER
+      if (irq > BSP_MICH_IRQ_MAX_OFFSET)
+         out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */
 #endif
-  oldMask[0]= GT_MAINirqLO_cache;
-  oldMask[1]= GT_MAINirqHI_cache;
-
-  for (i=0;mainIrqTbl[i]!=-1;i++) {
-    irq=mainIrqTbl[i];
-    if ( irq < startIrqNum ) continue;
-    regNum = irq/32;
-    bitNum = irq % 32;
-    if ( mainCause[regNum] & (1<<bitNum)) {
-      GT_MAINirqLO_cache=oldMask[0]&(~irq_prio_maskLO_tbl[irq]);
-      outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO);
-      __asm __volatile("sync");
-      GT_MAINirqHI_cache=oldMask[1]&(~irq_prio_maskHI_tbl[irq]);
-      outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI);
-      __asm __volatile("sync");
-
-      /* <skf> It seems that reading back is necessary to ensure the 
-       * interrupt mask updated. Otherwise, spurious interrupt will
-       * happen.  However, I do not want to use "while loop" to risk 
-       * the CPU stuck.  I wound rather keep track of the interrupt
-       * mask if not updated.
-       */
-      if (((irqLOW[irqIndex]= inl(GT_CPU_INT_MASK_LO))!=GT_MAINirqLO_cache)||
-          ((irqHIGH[irqIndex]= inl(GT_CPU_INT_MASK_HI))!=GT_MAINirqHI_cache)){
-         irqIndex++;
-         irqIndex %=20;
-         irqCAUSE[irqIndex] = irq;
-      }
-      _CPU_MSR_GET(msr);
+
+      _MSR_GET(msr);
       new_msr = msr | MSR_EE;
-      _CPU_MSR_SET(new_msr);
+      _MSR_SET(new_msr); 
       rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
-      _CPU_MSR_SET(msr);
+      _MSR_SET(msr);
+      
+      for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
       break;
     }
   }
-  GT_MAINirqLO_cache=oldMask[0];
-  outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO);
-  GT_MAINirqHI_cache=oldMask[1];
-  outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI);
+
+  out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);
+  out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);
+  out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);
+  in_le32((volatile unsigned *)0xf100f10c);
 }
 
 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
@@ -536,10 +667,15 @@ void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    */
 }
 
-void BSP_printIRQMask()
+/* Only print part of the entries for now */
+void BSP_printPicIsrTbl()
 {
   int i;
 
-  for (i=0; i< 20; i++)
-    printk("IRQ%d : 0x%x %x \n", irqCAUSE[i], irqHIGH[i],irqLOW[i]);
+  printk("picIsrTable[12]={");
+  for (i=0; i<12; i++)
+    printk("%d,", picIsrTable[i]);
+  printk("}\n");
+
+  printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
 }
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h
index e89ddf3220..9b7c21367e 100644
--- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h
@@ -15,12 +15,13 @@
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- * Copyright 2004, Brookhaven National Laboratory and
+ * Copyright 2004, 2005 Brookhaven National Laboratory and
  *                 Shuchen Kate Feng <feng1@bnl.gov> 
  *
  *    - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC)
  *    - Discovery GT64260 interrupt controller instead of 8259.
  *    - Added support for software IRQ priority levels. 
+ *    - modified to optimize the IRQ latency and handling
  *
  *  $Id$
  */
@@ -28,13 +29,14 @@
 #ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
 #define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
 
+/*#define BSP_SHARED_HANDLER_SUPPORT      1*/
 #include <rtems/irq.h>
 
 #define BSP_ASM_IRQ_VECTOR_BASE 0x0
 
 #ifndef ASM
 
-#define DynamicIrqTbl 1
+#define OneTierIrqPrioTbl 1
 
 /*
  * Symbolic IRQ names and related definitions.
@@ -83,7 +85,8 @@
    * Summary
    */
 #define BSP_IRQ_NUMBER			(BSP_MISC_IRQ_MAX_OFFSET + 1)
-#define BSP_MAIN_IRQ_NUMBER            (64)
+#define BSP_MAIN_IRQ_NUMBER             (64)
+#define BSP_PIC_IRQ_NUMBER              (96)
 #define BSP_LOWEST_OFFSET		(BSP_MICL_IRQ_LOWEST_OFFSET)
 #define BSP_MAX_OFFSET			(BSP_MISC_IRQ_MAX_OFFSET)
 
@@ -109,6 +112,7 @@
 #define BSP_MAIN_GPP31_24_IRQ         (BSP_MICH_IRQ_LOWEST_OFFSET+27)
 
   /* on the MVME5500, these are the GT64260B external GPP0 interrupt */
+#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_GPP_IRQ_LOWEST_OFFSET)
 #define BSP_UART_COM2_IRQ		(BSP_GPP_IRQ_LOWEST_OFFSET)
 #define BSP_UART_COM1_IRQ		(BSP_GPP_IRQ_LOWEST_OFFSET)
 #define BSP_GPP8_IRQ_OFFSET		(BSP_GPP_IRQ_LOWEST_OFFSET+8)
@@ -129,29 +133,7 @@
    */
 #define BSP_DECREMENTER		(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
 
-typedef unsigned int rtems_GTirq_masks;
-
-extern rtems_GTirq_masks GT_GPPirq_cache;
-extern rtems_GTirq_masks GT_MAINirqLO_cache, GT_MAINirqHI_cache;
-
-void BSP_enable_main_irq(unsigned irqNum);
-void BSP_disable_main_irq(unsigned irqNum);
-void BSP_enable_gpp_irq(unsigned irqNum);
-void BSP_disable_gpp_irq(unsigned irqNum); 
- 
 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
-extern int gpp_int_error;
-#if  DynamicIrqTbl
-extern int MainIrqTblPtr;
-extern unsigned long long MainIrqInTbl;
-extern unsigned char GPPinMainIrqTbl[4];
-#endif
-extern unsigned int mainIrqTbl[64];
-extern unsigned int GPP7_0IrqTbl[8];
-extern unsigned int GPP15_8IrqTbl[8];
-extern unsigned int GPP23_16IrqTbl[8];
-extern unsigned int GPP31_24IrqTbl[8];
 
 #endif
-
 #endif
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c
index f3d2dc21ae..a56158067f 100644
--- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c
@@ -5,16 +5,13 @@
  *
  * CopyRight (C) 1999 valette@crf.canon.fr
  *
- * Special acknowledgement to Till Straumann <strauman@slac.stanford.edu>
- * for providing inputs to the IRQ optimization.
- * 
  * Modified and added support for the MVME5500.
- * Copyright 2003, 2004, Brookhaven National Laboratory and
+ * Copyright 2003, 2004, 2005, Brookhaven National Laboratory and
  *                 Shuchen Kate Feng <feng1@bnl.gov>
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
+ * http://www.rtems.com/license/LICENSE
  * 
  */
 #include <libcpu/io.h>
@@ -22,14 +19,12 @@
 #include <bsp/irq.h>
 #include <bsp.h>
 #include <libcpu/raw_exception.h>  /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */
+/*#define  TRACE_IRQ_INIT*/
 
 extern unsigned int external_exception_vector_prolog_code_size[];
 extern void external_exception_vector_prolog_code();
 extern unsigned int decrementer_exception_vector_prolog_code_size[];
 extern void decrementer_exception_vector_prolog_code();
-extern void GT_GPP_IntHandler0(), GT_GPP_IntHandler1();
-extern void GT_GPP_IntHandler2(), GT_GPP_IntHandler3();
-extern void BSP_GT64260INT_init();
 
 /*
  * default on/off function
@@ -47,116 +42,49 @@ static int connected() {return 1;}
 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
 static rtems_irq_connect_data     	defaultIrq = {
-  /* vectorIdex,	 hdl		, handle	, on		, off		, isOn */
-  0, 			 nop_func	, NULL		, nop_func	, nop_func	, not_connected
+  /* vectorIdex,	 hdl	  , handle	, on		, off		, isOn */
+  0, 			 nop_func  , NULL	, nop_func	, nop_func	, not_connected
 };
 
-rtems_irq_prio BSPirqPrioTable[BSP_MAIN_IRQ_NUMBER]={
+rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
   /*
    * This table is where the developers can change the levels of priority
    * based on the need of their applications.
    *
-   * actual priorities for CPU MAIN interrupts 0-63:
+   * actual priorities for CPU MAIN and GPP interrupts (0-95) 
+   *
    *	0   means that only current interrupt is masked (lowest priority)
-   *	255 means all other interrupts are masked
+   *	255 is only used by bits 24, 25, 26 and 27 of the CPU high
+   *        interrupt Mask: (e.g. GPP7_0, GPP15_8, GPP23_16, GPP31_24). 
+   *        The IRQs of those four bits are always enabled. When it's used,
+   *        the IRQ number is never listed in the dynamic picIsrTable[96].
+   *
+   *        The priorities of GPP interrupts were decided by their own
+   *        value set at  BSPirqPrioTable.
+   *            
    */
   /* CPU Main cause low interrupt */
   /* 0-15 */
-  0, 0, 0, 0, 0, 0, 0, 0, 4/*Timer*/, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 64/*Timer*/, 0, 0, 0, 0, 0, 0, 0,
    /* 16-31 */
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
   /* CPU Main cause high interrupt */
   /* 32-47 */
-  1/*10/100MHZ*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  2/*10/100MHZ*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
   /* 48-63 */
-  0, 0, 0, 0, 0, 0, 0, 0, 0/*serial*/, 3/*VME*/, 2/*1GHZ*/, 5/*WD*/, 0, 0, 0, 0
+  0, 0, 0, 0, 0, 0, 0, 0, 
+  255 /*GPP0-7*/, 255/*GPP8-15*/, 255/*GPP16-23*/, 255/*GPP24-31*/, 0, 0, 0, 0,
+  /* GPP interrupts */
+  /* GPP0-7 */
+  1/*serial*/,0, 0, 0, 0, 0, 0, 0,
+  /* GPP8-15 */
+  47/*PMC1A*/,46/*PMC1B*/,45/*PMC1C*/,44/*PMC1D*/,30/*VME0*/, 29/*VME1*/,3,1,
+  /* GPP16-23 */
+  37/*PMC2A*/,36/*PMC2B*/,35/*PMC2C*/,34/*PMC2D*/,23/*1GHZ*/, 0,0,0,  
+  /* GPP24-31 */
+  7/*watchdog*/, 0,0,0,0,0,0,0
 };
 
-/* The mainIrqTbl[64] lists the enabled CPU main interrupt
- * numbers [0-63] starting from the highest priority one
- * to the lowest priority one.
- *
- * The highest priority interrupt is located at mainIrqTbl[0], and 
- * the lowest priority interrupt is located at 
- * mainIrqTbl[MainIrqTblPtr-1].
- */
-
-#if DynamicIrqTbl
-/* The mainIrqTbl[64] is updated dynamically based on the priority
- * levels set at BSPirqPrioTable[64], as the BSP_enable_main_irq() and
- * BSP_disable_main_irq() commands are invoked.
- *
- * Caveat: The eight GPP IRQs for each BSP_MAIN_GPPx_y_IRQ group are set
- * at the same main priority in the BSPirqPrioTable, while the 
- * sub-priority levels for the eight GPP in each group  are sorted 
- * statically by developers in the GPPx_yIrqTbl[8] from the highest
- * priority to the lowest one.
- */
-int MainIrqTblPtr=0;
-unsigned long long MainIrqInTbl=0;
-unsigned char GPPinMainIrqTbl[4]={0,0,0,0};
-/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ 
-unsigned int mainIrqTbl[BSP_MAIN_IRQ_NUMBER]={  
-                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1};
-#else
-/* Pre-sorted for IRQ optimization, and prioritization 
- * The interrupts sorted are :
-
- 1. Watchdog timer      (GPP #25)
- 2. Timers 0-1          (Main interrupt low cause, bit 8)
- 3. VME interrupt       (GPP #12)
- 4. 1 GHZ ethernet      (GPP #20)
- 5. 10/100 MHZ ethernet (Main interrupt high cause, bit 0)
- 6. COM1/COM2           (GPP #0)
-
-*/ 
-/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ 
-unsigned int mainIrqTbl[64]={ BSP_MAIN_GPP31_24_IRQ, /* 59:watchdog timer */
-			       BSP_MAIN_TIMER0_1_IRQ, /* 8:Timers 0-1 */
-			       BSP_MAIN_GPP15_8_IRQ,  /* 57:VME interrupt */
-			       BSP_MAIN_GPP23_16_IRQ, /* 58: 1 GHZ ethernet */
-			       BSP_MAIN_ETH0_IRQ,  /* 32:10/100 MHZ ethernet */
-			       BSP_MAIN_GPP7_0_IRQ, /* 56:COM1/COM2 */
-			       -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-			       -1, -1, -1, -1};
-#endif
-
-unsigned int GPP7_0IrqTbl[8]={0, /* COM1/COM2 */
-                               -1, -1, -1, -1, -1, -1, -1};
-unsigned int GPP15_8IrqTbl[8]={ 4, 5, 6, 7,  /* VME interrupt 0-3 */
-				0, 1, 2, 3   /* PMC1 INT A, B, C, D */};
-unsigned int GPP23_16IrqTbl[8]={4, /* 82544 1GHZ ethernet (20-16=4)*/
-				0, 1, 2, 3, /* PMC2 INT A, B, C, D */
-			     	-1, -1, -1};
-unsigned int GPP31_24IrqTbl[8]={1, /* watchdog timer (25-24=1) */
-				-1, -1, -1, -1, -1, -1, -1};
-
-static int
-doit(unsigned intNum, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*))
-{
-	rtems_irq_connect_data d={0};
-	d.name = intNum;
-	d.isOn = connected;
-	d.hdl  = handler;
-	return p(&d);
-}
-
-int BSP_GT64260_install_isr(unsigned intNum,rtems_irq_hdl handler)
-{
-  return doit(intNum, handler, BSP_install_rtems_irq_handler);
-}
-
 /*
  * This code assumes the exceptions management setup has already
  * been done. We just need to replace the exceptions that will
@@ -174,7 +102,6 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
 #ifdef TRACE_IRQ_INIT  
   printk("Initializing the interrupt controller of the GT64260\n");
 #endif       
-  BSP_GT64260INT_init();
 
 #ifdef TRACE_IRQ_INIT  
   printk("Going to re-initialize the rtemsIrq table %d\n",BSP_IRQ_NUMBER);
@@ -186,8 +113,8 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
    * re-init the rtemsIrq table
    */
   for (i = 0; i < BSP_IRQ_NUMBER; i++) {
-      rtemsIrq[i]      = defaultIrq;
-      rtemsIrq[i].name = i;
+    rtemsIrq[i]      = defaultIrq;    
+    rtemsIrq[i].name = i;
   }
 
   /*
@@ -209,13 +136,10 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
        */
       BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
   }
+#ifdef TRACE_IRQ_INIT  
+  printk("Done setup irq mngt configuration\n");
+#endif      
 
-  /* Connect the GPP int handler to each of the associated main cause bits */
-  BSP_GT64260_install_isr(BSP_MAIN_GPP7_0_IRQ, GT_GPP_IntHandler0); /* COM1 & COM2, .... */
-  BSP_GT64260_install_isr(BSP_MAIN_GPP15_8_IRQ, GT_GPP_IntHandler1);
-  BSP_GT64260_install_isr(BSP_MAIN_GPP23_16_IRQ, GT_GPP_IntHandler2);
-  BSP_GT64260_install_isr(BSP_MAIN_GPP31_24_IRQ, GT_GPP_IntHandler3);
- 
   /*
    * We must connect the raw irq handler for the two
    * expected interrupt sources : decrementer and external interrupts.