Add MVME550 BSP

8 files changed, 1809 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c
new file mode 100644
index 0000000000..aca7619086
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c
@@ -0,0 +1,210 @@
+/* GT64260TWSI.c : Two-Wire Serial Interface (TWSI) support for the GT64260
+ *
+ * Copyright (c) 2004, Brookhaven National Laboratory and
+ *                 Shuchen Kate Feng <feng1@bnl.gov>
+ * All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution.
+ *
+ * See section 24:TWSI interface of "the GT-64260B System Controller
+ * for powerPc Processors Data Sheet".
+ *
+ * For full TWSI protocol description look in Philips Semiconductor
+ * TWSI spec.
+ *
+ * We need it to read out I2C devices used for the MVME5500 
+ * (eg. the memory SPD and VPD). 
+ *
+ */
+#include <libcpu/spr.h>  /*registers.h included here for rtems_bsp_delay()*/
+#include <libcpu/io.h>
+#include <rtems/bspIo.h>	    /* printk */
+
+#include "bsp/gtreg.h"
+#include "bsp/GT64260TWSI.h"
+
+#define MAX_LOOP 100
+
+#define TWSI_DEBUG 0
+
+int TWSI_initFlg = 0;	/* TWSI Initialization Flag */
+
+void GT64260TWSIinit()
+{
+
+  if ( !TWSI_initFlg) {
+#if TWSI_DEBUG
+     printk("GT64260TWSIinit(");
+#endif
+     outl( 0, TWSI_SFT_RST); /* soft reset */
+     rtems_bsp_delay(1000);
+
+     /* See 24.2.5 : Assume bus speed is 133MHZ
+      * Try to be close to the default frequency : 62.5KHZ
+      * value 0x2c: 69.27 KHz TWSI bus clock 
+      */  
+     outl(0x2c, TWSI_BAUDE_RATE);
+     rtems_bsp_delay(1000);
+
+     /* Set Acknowledge and enable TWSI in the Control register */
+     outl(0x44, TWSI_CTRL);
+     rtems_bsp_delay(4000);
+     TWSI_initFlg = 1;
+#if TWSI_DEBUG
+     printk(")\n");
+#endif
+  }     
+}
+
+/* return the interrupt flag */
+int GT64260TWSIintFlag() 
+{
+  unsigned int loop;
+
+  for (loop = 0; loop < MAX_LOOP; loop++ ) {
+    /* Return 1 if the interrupt flag is set */
+      if (inl(TWSI_CTRL) & TWSI_INTFLG) return(1);
+      rtems_bsp_delay(1000);
+  }
+  return(0);
+}
+
+int GT64260TWSIstop() 
+{
+
+#if TWSI_DEBUG
+  printk("GT64260TWSIstop(");
+#endif
+
+  outl((inl(TWSI_CTRL) | TWSI_STOP), TWSI_CTRL);
+  rtems_bsp_delay(1000);
+
+  /* Check if interrupt flag bit is set*/
+  if (GT64260TWSIintFlag()) {
+     outl((inl( TWSI_CTRL) & ~TWSI_INTFLG), TWSI_CTRL);
+     rtems_bsp_delay(1000);
+#if TWSI_DEBUG
+     printk(")\n");
+#endif
+     return(0);
+  }
+#if TWSI_DEBUG
+     printk("NoIntFlag\n");
+#endif
+  return(-1);
+}
+
+int GT64260TWSIstart()
+{
+  unsigned int loop;	
+  unsigned int status;	
+
+#if TWSI_DEBUG
+  printk("GT64260TWSIstart(");
+#endif
+  /* Initialize the TWSI interface */
+  GT64260TWSIinit();
+
+  /* set the start bit */
+  outl((TWSI_START | TWSI_TWSIEN), TWSI_CTRL);
+  rtems_bsp_delay(1000);
+
+  if (GT64260TWSIintFlag()) {
+     /* Check for completion of START sequence */
+     for (loop = 0; loop<MAX_LOOP; loop++ ) {
+         /* if (start condition transmitted) || 
+          *    (repeated start condition transmitted )
+          */
+         if (((status= inl( TWSI_STATUS)) == 8) || (status == 0x10)) {
+#if TWSI_DEBUG
+             printk(")");
+#endif
+             return(0);
+         }
+         rtems_bsp_delay(1000);
+     }
+  }
+  /* if loop ends or intFlag ==0 */
+  GT64260TWSIstop();
+  return(-1);
+}
+
+int GT64260TWSIread(unsigned char * pData,int lastByte) 
+{
+  unsigned int loop;		
+
+#if TWSI_DEBUG
+  printk("GT64260TWSIread(");
+#endif
+  /* Clear INTFLG and set ACK and ENABLE bits */
+  outl((TWSI_ACK | TWSI_TWSIEN), TWSI_CTRL);
+  rtems_bsp_delay(1000);
+
+  if (GT64260TWSIintFlag()) {
+     for (loop = 0; loop< MAX_LOOP; loop++) {
+       /* if Master received read data, acknowledge transmitted */
+       if ( (inl( TWSI_STATUS) == 0x50)) {
+	   *pData = (unsigned char) inl( TWSI_DATA); 
+   	   rtems_bsp_delay(1500);
+
+           /* Clear INTFLAG and set Enable bit only */
+	   if (lastByte) outl(TWSI_TWSIEN, TWSI_CTRL);
+	   rtems_bsp_delay(1500);
+#if TWSI_DEBUG
+  printk(")\n");
+#endif
+	   return(0);
+	}
+	rtems_bsp_delay(1000);
+     } /* end for */
+  }
+  /* if loop ends or intFlag ==0 */
+  GT64260TWSIstop();
+  return(-1);
+}
+
+/* do a TWSI write cycle on the TWSI bus*/
+int GT64260TWSIwrite(unsigned char Data) 
+{
+  unsigned int loop;		
+  unsigned int status;	
+
+#if TWSI_DEBUG
+  printk("GT64260TWSIwrite(");
+#endif
+  /* Write data into the TWSI data register */
+  outl(((unsigned int) Data), TWSI_DATA); 
+  rtems_bsp_delay(1000);
+
+  /* Clear INTFLG in the control register to drive data onto TWSI bus */
+  outl(0, TWSI_CTRL);
+  rtems_bsp_delay(1000);
+
+  if (GT64260TWSIintFlag() ) {
+     for (loop = 0; loop< MAX_LOOP; loop++) {
+	 rtems_bsp_delay(1000);
+	 /* if address + write bit transmitted, acknowledge not received */
+	 if ( (status = inl( TWSI_STATUS)) == 0x20) {
+            /* No device responding, generate STOP and return -1 */
+	   printk("no device responding\n");
+	    GT64260TWSIstop();
+	    return(-1);
+	 }
+         /* if (address + write bit transmitted, acknowledge received)
+	  *    (Master transmmitted data byte, acknowledge received) 
+          *    (address + read bit transmitted, acknowledge received)
+          */
+	 if ((status == 0x18)||(status == 0x28)||(status == 0x40)) {
+#if TWSI_DEBUG
+	      printk(")\n");
+#endif
+	      return(0);
+         }
+	 rtems_bsp_delay(1000);
+     } /* end for */
+  }
+  printk("No correct status, timeout\n");
+  GT64260TWSIstop();
+  return(-1);
+}
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h
new file mode 100644
index 0000000000..5623f65b7c
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h
@@ -0,0 +1,9 @@
+/* GT64260TWSI.h -  header for the GT64260 Two-Wire Serial Interface */
+
+/* TWSI Control Register Bits */
+#define TWSI_ACK	   4
+#define TWSI_INTFLG	   8
+#define TWSI_STOP       0x10
+#define TWSI_START      0x20
+#define TWSI_TWSIEN     0x40
+#define TWSI_INTEN      0x80
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c
new file mode 100644
index 0000000000..ff64924485
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c
@@ -0,0 +1,100 @@
+/* MVME5500I2C.c
+ *
+ * Copyright (c) 2003, 2004 Brookhaven National Laboratory
+ * Author:    S. Kate Feng <feng1@bnl.gov>
+ * All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution.
+ *
+ * To read inoformation of the EEPROM via the I2C
+ *
+ */
+
+#include <rtems/bspIo.h>	    /* printk */
+#include "bsp/GT64260TWSI.h"
+
+/* #define I2C_DEBUG*/
+typedef unsigned int u32;
+typedef unsigned char unchar;
+
+unchar I2cAddrPack(unchar busAddr,u32 offset)
+{
+  return(busAddr | ((offset & 0x700) >> 7));
+}
+unchar I2cDevByteAddr(u32 devA2A1A0, unchar byteNum)
+{
+  return(( devA2A1A0 >>(byteNum*8)) & 0xff);
+}
+/****************************************************************************
+* I2Cread_eeprom - read EEPROM VPD from the I2C
+*/
+int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,unchar *pBuff,u32 numBytes)
+{
+  int status=0, lastByte=0;
+
+  switch (AddrBytes) {
+    case 1:
+      if ((status=GT64260TWSIstart()) != -1) {
+	if ((status=GT64260TWSIwrite(I2cAddrPack(I2cBusAddr,devA2A1A0)))!= -1){
+	  if ((status=GT64260TWSIwrite(devA2A1A0))!=-1){
+	    if ((status=GT64260TWSIstart())!=-1)
+	        status=GT64260TWSIwrite(I2cAddrPack((I2cBusAddr|0x01),devA2A1A0));
+	  }
+        }
+      }
+      break;
+    case 2:
+      if ((status=GT64260TWSIstart())!=-1) {
+	if ((status=GT64260TWSIwrite(I2cBusAddr))!= -1) {
+	  if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,1)))!=-1) {
+	    if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,0)))!= -1){
+	      if ((status=GT64260TWSIstart()) != -1) {
+		status = GT64260TWSIwrite((I2cBusAddr | 0x01));
+              }
+            }
+          }
+        }
+      }
+      break;
+    case 3:
+      if ((status = GT64260TWSIstart())!= -1) {
+	if ((status = GT64260TWSIwrite(I2cBusAddr))!= -1) {
+	  if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,2)))!= -1){
+	    if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,1)))!= -1){
+	      if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,0)))!= -1){
+  	        if ((status=GT64260TWSIstart())!= -1) {
+		  status = GT64260TWSIwrite(I2cBusAddr | 0x01);
+                }
+              }
+            }
+          }
+        }
+      }
+      break;
+    default: 
+      status=-1;
+      break;  
+  }
+  if (status !=-1) {
+#ifdef I2C_DEBUG
+     printk("\n");
+#endif
+     /* read data from device */
+     for ( ; numBytes > 0; numBytes-- ) {      
+       if ( numBytes == 1) lastByte=1;
+       if (GT64260TWSIread(pBuff,lastByte) == -1) return (-1);
+#ifdef I2C_DEBUG
+       printk("%2x ", *pBuff);
+       if ( (numBytes % 20)==0 ) printk("\n");
+#endif
+       pBuff++;	
+     }
+#ifdef I2C_DEBUG
+     printk("\n");
+#endif
+     if (GT64260TWSIstop() == -1) return (-1);
+  }
+  return (status);
+}
+
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/Makefile.am b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/Makefile.am
new file mode 100644
index 0000000000..567c3d427c
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/Makefile.am
@@ -0,0 +1,52 @@
+##
+## $Id: Makefile.am, S. Kate Feng /12/03
+##
+
+VPATH = @srcdir@:
+
+INCLUDES = -I @srcdir@/../GT64260
+
+C_FILES = GT64260TWSI.c MVME5500I2C.c
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS = bspMvme5500.h gtreg.h GT64260TWSI.h VPD.h
+
+H_FILES = bspMvme5500.h gtreg.h GT64260TWSI.h VPD.h
+
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
+
+EXTRA_DIST = GT64260TWSI.c MVME5500I2C.c
+
+OBJS = $(C_O_FILES)
+
+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PROJECT_INCLUDE)/bsp:
+	$(mkinstalldirs) $<
+
+$(PROJECT_INCLUDE)/bsp/bspMvme5500.h: bspMvme5500.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/gtreg.h: gtreg.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/GT64260TWSI.h: GT64260TWSI.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/VPD.h: VPD.h
+	$(INSTALL_DATA) $< $@
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+PREINSTALL_FILES = $(PROJECT_INCLUDE)/bsp $(PROJECT_INCLUDE)/bsp/bspMvme5500.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gtreg.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260TWSI.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VPD.h
+
+all-local: $(ARCH) $(PREINSTALL_FILES) $(OBJS)
+
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/Makefile.in b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/Makefile.in
new file mode 100644
index 0000000000..4a99976a5c
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/Makefile.in
@@ -0,0 +1,601 @@
+# Makefile.in generated by automake 1.7.2 from Makefile.am.
+# @configure_input@
+
+# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+# Free Software Foundation, Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+top_builddir = ..
+
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+INSTALL = @INSTALL@
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+host_triplet = @host@
+
+VPATH = @srcdir@:
+ACLOCAL = @ACLOCAL@
+AMDEP_FALSE = @AMDEP_FALSE@
+AMDEP_TRUE = @AMDEP_TRUE@
+AMTAR = @AMTAR@
+
+AR = @AR@
+
+# OBSOLETE: Don't use
+AS = $(CC)
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BARE_CPU_CFLAGS = @BARE_CPU_CFLAGS@
+BARE_CPU_MODEL = @BARE_CPU_MODEL@
+
+CC = @CC@ $(GCCSPECS)
+
+CCAS = $(CC)
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @RTEMS_CFLAGS@ $(XCFLAGS)
+CFLAGS_DEBUG_V = @CFLAGS_DEBUG_V@
+CFLAGS_OPTIMIZE_V = @CFLAGS_OPTIMIZE_V@
+CFLAGS_PROFILE_V = @CFLAGS_PROFILE_V@
+CPP = @CPP@ $(GCCSPECS)
+
+CPPFLAGS = @CPPFLAGS@ $(CPU_DEFINES) $(DEFINES) $(XCPPFLAGS)
+
+CPU_CFLAGS = @CPU_CFLAGS@
+CYGPATH_W = @CYGPATH_W@
+
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+ENDIF = @ENDIF@
+EXEEXT = @EXEEXT@
+GCC_SPECS = @GCC_SPECS@
+HAS_MP = @HAS_MP@
+HAS_NETWORKING = @HAS_NETWORKING@
+HAS_NETWORKING_FALSE = @HAS_NETWORKING_FALSE@
+HAS_NETWORKING_TRUE = @HAS_NETWORKING_TRUE@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+
+LD = @LD@
+LDFLAGS = @LDFLAGS@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@
+MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
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+MAKEINFO = @MAKEINFO@
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+MULTILIB_TRUE = @MULTILIB_TRUE@
+NM = @NM@
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+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
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+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PACKHEX = @PACKHEX@
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+PROJECT_RELEASE = @PROJECT_RELEASE@
+PROJECT_ROOT = @PROJECT_ROOT@
+PROJECT_TOPdir = @PROJECT_TOPdir@
+RANLIB = @RANLIB@
+RTEMS_BSP = @RTEMS_BSP@
+RTEMS_BSP_FAMILY = @RTEMS_BSP_FAMILY@
+RTEMS_BSP_SPECS = @RTEMS_BSP_SPECS@
+RTEMS_CFLAGS = @RTEMS_CFLAGS@
+RTEMS_CPPFLAGS = @RTEMS_CPPFLAGS@
+RTEMS_CPU = @RTEMS_CPU@
+RTEMS_CPU_MODEL = @RTEMS_CPU_MODEL@
+RTEMS_HAS_NETWORKING = @RTEMS_HAS_NETWORKING@
+RTEMS_HOST = @RTEMS_HOST@
+RTEMS_ROOT = @RTEMS_ROOT@
+RTEMS_TOPdir = @RTEMS_TOPdir@
+RTEMS_USE_GCC_FALSE = @RTEMS_USE_GCC_FALSE@
+RTEMS_USE_GCC_TRUE = @RTEMS_USE_GCC_TRUE@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SIZE = @SIZE@
+STRIP = @STRIP@
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+am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
+am__include = @am__include@
+am__quote = @am__quote@
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+bsplibdir = @bsplibdir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+datadir = @datadir@
+exceptions = @exceptions@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+oldincludedir = @oldincludedir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+sysconfdir = @sysconfdir@
+target = @target@
+target_alias = @target_alias@
+target_cpu = @target_cpu@
+target_os = @target_os@
+target_vendor = @target_vendor@
+
+INCLUDES = -I @srcdir@/../GT64260
+
+C_FILES = GT64260TWSI.c MVME5500I2C.c
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS = bspMvme5500.h gtreg.h GT64260TWSI.h VPD.h
+
+H_FILES = bspMvme5500.h gtreg.h GT64260TWSI.h VPD.h
+
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
+
+EXTRA_DIST = GT64260TWSI.c MVME5500I2C.c
+
+OBJS = $(C_O_FILES)
+
+@RTEMS_USE_GCC_TRUE@GCCSPECS = $(GCC_SPECS) $(RTEMS_BSP_SPECS)
+# CXXFLAGS = @RTEMS_CXXFLAGS@ $(XCXXFLAGS)
+CXXFLAGS = @RTEMS_CFLAGS@ $(XCXXFLAGS)
+ASFLAGS = $(CPU_ASFLAGS) $(CPU_CFLAGS) $(XASFLAGS)
+
+LINK_LIBS = $(LD_LIBS)
+
+
+#
+# Client compiler and support tools
+#
+
+#
+# How to compile stuff into ${ARCH} subdirectory
+#
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
+        $(AM_LDFLAGS) $(LDFLAGS) -o $@
+
+
+CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+	$(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
+
+CXXLD = $(CXX)
+CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) \
+	$(AM_LDFLAGS) $(LDFLAGS) -o $@
+
+CCASCOMPILE = $(CCAS) $(AM_CCASFLAGS) $(CCASFLAGS)
+ASCOMPILE = $(AS) $(AM_ASFLAGS) $(ASFLAGS)
+
+
+# Dependency files for use by gmake
+# NOTE: we don't put them into $(ARCH)
+#       so that 'make clean' doesn't blow it away
+DEPEND = Depends-${ARCH}
+
+
+# spell out all the LINK_FILE's, rather than using -lbsp, so
+#  that $(LINK_FILES) can be a dependency
+LINK_OBJS = \
+    $(OBJS) \
+    $(MANAGERS_NOT_WANTED:%=$(PROJECT_RELEASE)/lib/no-%$(LIB_VARIANT).rel)
+
+
+LINK_FILES = \
+    $(START_FILE) \
+    $(OBJS) \
+    $(MANAGERS_NOT_WANTED:%=$(PROJECT_RELEASE)/lib/no-%$(LIB_VARIANT).rel)
+
+
+VARIANT = OPTIMIZE
+
+VARIANT_OPTIMIZE_V = OPTIMIZE
+VARIANT_DEBUG_V = DEBUG
+VARIANT_PROFILE_V = PROFILE
+VARIANT_optimize_V = OPTIMIZE
+VARIANT_debug_V = DEBUG
+VARIANT_profile_V = PROFILE
+
+VARIANT_V = $(VARIANT_$(VARIANT)_V)
+
+ARCH_OPTIMIZE_V = o-optimize
+ARCH_DEBUG_V = o-debug
+ARCH_PROFILE_V = o-profile
+
+ARCH__V = $(ARCH_OPTIMIZE_V)
+ARCH = $(ARCH_$(VARIANT_V)_V)
+
+LIBSUFFIX_OPTIMIZE_V = 
+LIBSUFFIX_DEBUG_V = _g
+LIBSUFFIX_PROFILE_V = _p
+LIBSUFFIX__V = $(LIBSUFFIX_OPTIMIZE_V)
+
+LIB_VARIANT = $(LIBSUFFIX_$(VARIANT_V)_V)
+CFLAGS__V = $(CFLAGS_OPTIMIZE_V)
+
+@RTEMS_USE_GCC_TRUE@RTEMS_CFLAGS_OPTIMIZE_V = 
+@RTEMS_USE_GCC_TRUE@RTEMS_CFLAGS_DEBUG_V = -qrtems_debug -Wno-unused
+@RTEMS_USE_GCC_TRUE@RTEMS_CFLAGS_PROFILE_V = -pg
+
+RTEMS_CFLAGS__V = $(RTEMS_CFLAGS_OPTIMIZE_V)
+CXX = @CXX@ $(GCCSPECS)
+
+AM_CPPFLAGS = $(RTEMS_CPPFLAGS)
+AM_CFLAGS = 
+AM_CXXFLAGS = 
+AM_CCASFLAGS = $(CPU_CFLAGS) $(RTEMS_CPPFLAGS) $(RTEMS_CCASFLAGS)
+
+ARFLAGS = ruv
+
+TMPINSTALL_FILES = $(PROJECT_RELEASE)/lib
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+PREINSTALL_FILES = $(PROJECT_INCLUDE)/bsp $(PROJECT_INCLUDE)/bsp/bspMvme5500.h $(PROJECT_INCLUDE)/bsp/gtreg.h $(PROJECT_INCLUDE)/bsp/GT64260TWSI.h $(PROJECT_INCLUDE)/bsp/VPD.h
+
+PROJECT_TOOLS = $(PROJECT_RELEASE)/build-tools
+subdir = GT64260
+mkinstalldirs = $(SHELL) $(top_srcdir)/../../../../../../mkinstalldirs
+CONFIG_HEADER = $(top_builddir)/include/bspopts.tmp
+CONFIG_CLEAN_FILES =
+DIST_SOURCES =
+HEADERS = $(include_bsp_HEADERS)
+
+DIST_COMMON = $(include_bsp_HEADERS) \
+	$(top_srcdir)/../../../../../../automake/compile.am \
+	$(top_srcdir)/../../../../../../automake/lib.am \
+	$(top_srcdir)/../../../../../../automake/local.am Makefile.am \
+	Makefile.in
+all: all-am
+
+.SUFFIXES:
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ Makefile.am $(top_srcdir)/../../../../../../automake/compile.am $(top_srcdir)/../../../../../../automake/lib.am $(top_srcdir)/../../../../../../automake/local.am $(top_srcdir)/configure.ac $(ACLOCAL_M4)
+	cd $(top_srcdir) && \
+	  $(AUTOMAKE) --foreign  GT64260/Makefile
+Makefile: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.in  $(top_builddir)/config.status
+	cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)
+uninstall-info-am:
+include_bspHEADERS_INSTALL = $(INSTALL_HEADER)
+install-include_bspHEADERS: $(include_bsp_HEADERS)
+	@$(NORMAL_INSTALL)
+	$(mkinstalldirs) $(DESTDIR)$(include_bspdir)
+	@list='$(include_bsp_HEADERS)'; for p in $$list; do \
+	  if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+	  f="`echo $$p | sed -e 's|^.*/||'`"; \
+	  echo " $(include_bspHEADERS_INSTALL) $$d$$p $(DESTDIR)$(include_bspdir)/$$f"; \
+	  $(include_bspHEADERS_INSTALL) $$d$$p $(DESTDIR)$(include_bspdir)/$$f; \
+	done
+
+uninstall-include_bspHEADERS:
+	@$(NORMAL_UNINSTALL)
+	@list='$(include_bsp_HEADERS)'; for p in $$list; do \
+	  f="`echo $$p | sed -e 's|^.*/||'`"; \
+	  echo " rm -f $(DESTDIR)$(include_bspdir)/$$f"; \
+	  rm -f $(DESTDIR)$(include_bspdir)/$$f; \
+	done
+
+ETAGS = etags
+ETAGSFLAGS =
+
+CTAGS = ctags
+CTAGSFLAGS =
+
+tags: TAGS
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+	list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+	unique=`for i in $$list; do \
+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+	  done | \
+	  $(AWK) '    { files[$$0] = 1; } \
+	       END { for (i in files) print i; }'`; \
+	mkid -fID $$unique
+
+TAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
+		$(TAGS_FILES) $(LISP)
+	tags=; \
+	here=`pwd`; \
+	list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
+	unique=`for i in $$list; do \
+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+	  done | \
+	  $(AWK) '    { files[$$0] = 1; } \
+	       END { for (i in files) print i; }'`; \
+	test -z "$(ETAGS_ARGS)$$tags$$unique" \
+	  || $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+	     $$tags $$unique
+
+ctags: CTAGS
+CTAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
+		$(TAGS_FILES) $(LISP)
+	tags=; \
+	here=`pwd`; \
+	list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
+	unique=`for i in $$list; do \
+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+	  done | \
+	  $(AWK) '    { files[$$0] = 1; } \
+	       END { for (i in files) print i; }'`; \
+	test -z "$(CTAGS_ARGS)$$tags$$unique" \
+	  || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+	     $$tags $$unique
+
+GTAGS:
+	here=`$(am__cd) $(top_builddir) && pwd` \
+	  && cd $(top_srcdir) \
+	  && gtags -i $(GTAGS_ARGS) $$here
+
+distclean-tags:
+	-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+
+top_distdir = ..
+distdir = $(top_distdir)/$(PACKAGE)-$(VERSION)
+
+distdir: $(DISTFILES)
+	$(mkinstalldirs) $(distdir)/../../../../../../../automake
+	@srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \
+	topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \
+	list='$(DISTFILES)'; for file in $$list; do \
+	  case $$file in \
+	    $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \
+	    $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \
+	  esac; \
+	  if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+	  dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \
+	  if test "$$dir" != "$$file" && test "$$dir" != "."; then \
+	    dir="/$$dir"; \
+	    $(mkinstalldirs) "$(distdir)$$dir"; \
+	  else \
+	    dir=''; \
+	  fi; \
+	  if test -d $$d/$$file; then \
+	    if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+	      cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \
+	    fi; \
+	    cp -pR $$d/$$file $(distdir)$$dir || exit 1; \
+	  else \
+	    test -f $(distdir)/$$file \
+	    || cp -p $$d/$$file $(distdir)/$$file \
+	    || exit 1; \
+	  fi; \
+	done
+check-am: all-am
+check: check-am
+all-am: Makefile $(HEADERS) all-local
+
+installdirs:
+	$(mkinstalldirs) $(DESTDIR)$(include_bspdir)
+
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+	@$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+	$(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+	  INSTALL_STRIP_FLAG=-s \
+	  `test -z '$(STRIP)' || \
+	    echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+	-rm -f Makefile $(CONFIG_CLEAN_FILES)
+
+maintainer-clean-generic:
+	@echo "This command is intended for maintainers to use"
+	@echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+
+distclean-am: clean-am distclean-generic distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+info: info-am
+
+info-am:
+
+install-data-am: install-include_bspHEADERS
+
+install-exec-am:
+
+install-info: install-info-am
+
+install-man:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am: uninstall-include_bspHEADERS uninstall-info-am
+
+.PHONY: CTAGS GTAGS all all-am all-local check check-am clean \
+	clean-generic clean-local ctags distclean distclean-generic \
+	distclean-tags distdir dvi dvi-am info info-am install \
+	install-am install-data install-data-am install-exec \
+	install-exec-am install-include_bspHEADERS install-info \
+	install-info-am install-man install-strip installcheck \
+	installcheck-am installdirs maintainer-clean \
+	maintainer-clean-generic mostlyclean mostlyclean-generic pdf \
+	pdf-am ps ps-am tags uninstall uninstall-am \
+	uninstall-include_bspHEADERS uninstall-info-am
+
+@RTEMS_USE_GCC_FALSE@include $(CONFIG.CC)
+
+${ARCH}/%.o: %.c
+	${COMPILE} -o $@ -c $<
+
+${ARCH}/%.o: %.cc
+	${CXXCOMPILE} -o $@ -c $<
+
+${ARCH}/%.o: %.S
+	${CCASCOMPILE} -DASM -o $@ -c $<
+
+# We deliberately don't have anything depend on the
+# $(DEPEND) file; otherwise it will get rebuilt even
+# on 'make clean'
+#
+
+@RTEMS_USE_GCC_TRUE@depend-gcc: $(C_FILES) $(CC_FILES) $(S_FILES)
+@RTEMS_USE_GCC_TRUE@	$(COMPILE) -M   $^    |  \
+@RTEMS_USE_GCC_TRUE@	sed -e 's?^\(.*\)\.o[ ]*:?$$(ARCH)/\1.o:?' \
+@RTEMS_USE_GCC_TRUE@	    -e 's?$(ARCH)/?$$(ARCH)/?'   >$(DEPEND).tmp
+@RTEMS_USE_GCC_TRUE@	mv $(DEPEND).tmp $(DEPEND)
+
+# pull in dependencies if they exist  
+@RTEMS_USE_GCC_TRUE@ifeq (${DEPEND},$(wildcard ${DEPEND}))
+@RTEMS_USE_GCC_TRUE@include ${DEPEND}
+@RTEMS_USE_GCC_TRUE@@ENDIF@
+depend: depend-am
+
+@RTEMS_USE_GCC_TRUE@define make-rel
+@RTEMS_USE_GCC_TRUE@	$(LINK) -qnolinkcmds -nostdlib -Wl,-r $(XLDFLAGS) $^
+@RTEMS_USE_GCC_TRUE@endef
+@RTEMS_USE_GCC_FALSE@define make-rel
+@RTEMS_USE_GCC_FALSE@	$(LINK) $(XLDFLAGS) $^
+@RTEMS_USE_GCC_FALSE@endef
+
+${ARCH}:
+	mkdir ${ARCH}
+
+clean-local:
+	$(RM) -r o-optimize o-debug o-profile $(CLEANDIRS)
+	$(RM) Depends-o-optimize.tmp Depends-o-debug.tmp Depends-o-profile.tmp
+
+define make-library
+test -d $(ARCH) || mkdir $(ARCH)
+$(RM) $@
+$(AR) $(ARFLAGS) $@ $^
+$(RANLIB) $@
+endef
+
+$(PROJECT_RELEASE)/lib:
+	@$(mkinstalldirs) $@
+
+.PRECIOUS: $(LIB)
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PROJECT_INCLUDE)/bsp:
+	$(mkinstalldirs) $<
+
+$(PROJECT_INCLUDE)/bsp/bspMvme5500.h: bspMvme5500.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/gtreg.h: gtreg.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/GT64260TWSI.h: GT64260TWSI.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/bsp/VPD.h: VPD.h
+	$(INSTALL_DATA) $< $@
+
+all-local: $(ARCH) $(PREINSTALL_FILES) $(OBJS)
+
+debug:
+	@echo
+	@echo "\"make debug\" is obsolete, instead use:"
+	@echo "	make VARIANT=DEBUG"
+	@echo
+
+.PHONY: debug
+
+profile:
+	@echo
+	@echo "\"make profile\" is obsolete, instead use:"
+	@echo "	make VARIANT=PROFILE"
+	@echo
+
+.PHONY: profile
+
+preinstall-am: $(PREINSTALL_FILES)
+preinstall: preinstall-am
+.PHONY: preinstall preinstall-am
+
+depend-am: depend-gcc
+depend: depend-am
+.PHONY: depend depend-am depend-gcc
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h
new file mode 100644
index 0000000000..4b37de6927
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h
@@ -0,0 +1,11 @@
+/* The mapping of the Configuration VPD
+ *
+ * (C) 2004, NSLS, Brookhaven National Laboratory,
+ *           S. Kate Feng, <feng1@bnl.gov>
+ *
+ */
+
+extern unsigned char ConfVPD_buff[200];
+
+#define VPD_ENET0_OFFSET  0x3c
+#define VPD_ENET1_OFFSET  0x45
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/bspMvme5500.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/bspMvme5500.h
new file mode 100644
index 0000000000..20da5be0ed
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/bspMvme5500.h
@@ -0,0 +1,15 @@
+/* GT64260 register base mapping on the MVME5500
+ *
+ * (C) Shuchen K. Feng <feng1@bnl.gov>,NSLS, 
+ * Brookhaven National Laboratory, 2003
+ *
+ */
+#define _256M           0x10000000
+#define _512M           0x20000000
+
+#define GT64260_REG_BASE	0xf1000000  /* Base of GT64260 Reg Space */
+#define GT64260_REG_SPACE_SIZE	0x10000     /* 64Kb Internal Reg Space */
+
+#define GT64260_DEV1_BASE       0xf1100000  /* Device bank1(chip select 1) base
+                                             */
+#define GT64260_DEV1_SIZE 	0x00100000 /* Device bank size */
diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h
new file mode 100644
index 0000000000..b58b086565
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h
@@ -0,0 +1,811 @@
+/*	$NetBSD: gtreg.h,v 1.1 2003/03/05 22:08:22 matt Exp $	*/
+
+/*
+ * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Allegro Networks, Inc., and Wasabi Systems, Inc.
+ * 4. The name of Allegro Networks, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ * 5. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
+ * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DISCOVERY_DEV_GTREG_H_
+#define _DISCOVERY_DEV_GTREG_H_
+
+#define GT__BIT(bit)			(1U << (bit))
+#define GT__MASK(bit)			(GT__BIT(bit) - 1)
+#define	GT__EXT(data, bit, len)		(((data) >> (bit)) & GT__MASK(len))
+#define	GT__CLR(data, bit, len)		((data) &= ~(GT__MASK(len) << (bit)))
+#define	GT__INS(new, bit)		((new) << (bit))
+
+
+/* 
+ * Table 30: CPU Address Decode Register Map
+ */
+#define GT_SCS0_Low_Decode		0x0008 
+#define GT_SCS0_High_Decode		0x0010 
+#define GT_SCS1_Low_Decode		0x0208 
+#define GT_SCS1_High_Decode		0x0210 
+#define GT_SCS2_Low_Decode		0x0018 
+#define GT_SCS2_High_Decode		0x0020 
+#define GT_SCS3_Low_Decode		0x0218 
+#define GT_SCS3_High_Decode		0x0220 
+#define GT_CS0_Low_Decode		0x0028 
+#define GT_CS0_High_Decode		0x0030 
+#define GT_CS1_Low_Decode		0x0228 
+#define GT_CS1_High_Decode		0x0230 
+#define GT_CS2_Low_Decode		0x0248 
+#define GT_CS2_High_Decode		0x0250 
+#define GT_CS3_Low_Decode		0x0038 
+#define GT_CS3_High_Decode		0x0040 
+#define GT_BootCS_Low_Decode		0x0238 
+#define GT_BootCS_High_Decode		0x0240 
+#define GT_PCI0_IO_Low_Decode		0x0048 
+#define GT_PCI0_IO_High_Decode		0x0050 
+#define GT_PCI0_Mem0_Low_Decode		0x0058 
+#define GT_PCI0_Mem0_High_Decode	0x0060 
+#define GT_PCI0_Mem1_Low_Decode		0x0080 
+#define GT_PCI0_Mem1_High_Decode	0x0088 
+#define GT_PCI0_Mem2_Low_Decode		0x0258 
+#define GT_PCI0_Mem2_High_Decode	0x0260 
+#define GT_PCI0_Mem3_Low_Decode		0x0280 
+#define GT_PCI0_Mem3_High_Decode	0x0288 
+#define GT_PCI1_IO_Low_Decode		0x0090 
+#define GT_PCI1_IO_High_Decode		0x0098 
+#define GT_PCI1_Mem0_Low_Decode		0x00a0 
+#define GT_PCI1_Mem0_High_Decode	0x00a8 
+#define GT_PCI1_Mem1_Low_Decode		0x00b0 
+#define GT_PCI1_Mem1_High_Decode	0x00b8 
+#define GT_PCI1_Mem2_Low_Decode		0x02a0 
+#define GT_PCI1_Mem2_High_Decode	0x02a8 
+#define GT_PCI1_Mem3_Low_Decode		0x02b0 
+#define GT_PCI1_Mem3_High_Decode	0x02b8 
+#define GT_Internal_Decode		0x0068 
+#define GT_CPU0_Low_Decode		0x0290 
+#define GT_CPU0_High_Decode		0x0298 
+#define GT_CPU1_Low_Decode		0x02c0 
+#define GT_CPU1_High_Decode		0x02c8 
+#define GT_PCI0_IO_Remap		0x00f0 
+#define GT_PCI0_Mem0_Remap_Low		0x00f8 
+#define GT_PCI0_Mem0_Remap_High		0x0320 
+#define GT_PCI0_Mem1_Remap_Low		0x0100 
+#define GT_PCI0_Mem1_Remap_High		0x0328 
+#define GT_PCI0_Mem2_Remap_Low		0x02f8 
+#define GT_PCI0_Mem2_Remap_High		0x0330 
+#define GT_PCI0_Mem3_Remap_Low		0x0300 
+#define GT_PCI0_Mem3_Remap_High		0x0338 
+#define GT_PCI1_IO_Remap		0x0108 
+#define GT_PCI1_Mem0_Remap_Low		0x0110 
+#define GT_PCI1_Mem0_Remap_High		0x0340 
+#define GT_PCI1_Mem1_Remap_Low		0x0118 
+#define GT_PCI1_Mem1_Remap_High		0x0348 
+#define GT_PCI1_Mem2_Remap_Low		0x0310 
+#define GT_PCI1_Mem2_Remap_High		0x0350 
+#define GT_PCI1_Mem3_Remap_Low		0x0318 
+#define GT_PCI1_Mem3_Remap_High		0x0358 
+
+
+/*
+ * Table 31: CPU Control Register Map
+ */
+#define GT_CPU_Cfg			0x0000 
+#define GT_CPU_Mode			0x0120 
+#define GT_CPU_Master_Ctl		0x0160 
+#define GT_CPU_If_Xbar_Ctl_Low		0x0150 
+#define GT_CPU_If_Xbar_Ctl_High		0x0158 
+#define GT_CPU_If_Xbar_Timeout		0x0168 
+#define GT_CPU_Rd_Rsp_Xbar_Ctl_Low	0x0170 
+#define GT_CPU_Rd_Rsp_Xbar_Ctl_High	0x0178 
+
+/*
+ * Table 32: CPU Sync Barrier Register Map
+ */
+#define	GT_PCI_Sync_Barrier(bus)	(0x00c0 | ((bus) << 3))
+#define GT_PCI0_Sync_Barrier		0x00c0 
+#define GT_PCI1_Sync_Barrier		0x00c8 
+
+/*
+ * Table 33: CPU Access Protection Register Map
+ */
+#define GT_Protect_Low_0		0x0180 
+#define GT_Protect_High_0		0x0188 
+#define GT_Protect_Low_1		0x0190 
+#define GT_Protect_High_1		0x0198 
+#define GT_Protect_Low_2		0x01a0 
+#define GT_Protect_High_2		0x01a8 
+#define GT_Protect_Low_3		0x01b0 
+#define GT_Protect_High_3		0x01b8 
+#define GT_Protect_Low_4		0x01c0 
+#define GT_Protect_High_4		0x01c8 
+#define GT_Protect_Low_5		0x01d0 
+#define GT_Protect_High_5		0x01d8 
+#define GT_Protect_Low_6		0x01e0 
+#define GT_Protect_High_6		0x01e8 
+#define GT_Protect_Low_7		0x01f0 
+#define GT_Protect_High_7		0x01f8 
+
+/*
+ * Table 34: Snoop Control Register Map
+ */
+#define GT_Snoop_Base_0			0x0380 
+#define GT_Snoop_Top_0			0x0388 
+#define GT_Snoop_Base_1			0x0390 
+#define GT_Snoop_Top_1			0x0398 
+#define GT_Snoop_Base_2			0x03a0 
+#define GT_Snoop_Top_2			0x03a8 
+#define GT_Snoop_Base_3			0x03b0 
+#define GT_Snoop_Top_3			0x03b8 
+
+/*
+ * Table 35: CPU Error Report Register Map
+ */
+#define GT_CPU_Error_Address_Low	0x0070 
+#define GT_CPU_Error_Address_High	0x0078 
+#define GT_CPU_Error_Data_Low		0x0128 
+#define GT_CPU_Error_Data_High		0x0130 
+#define GT_CPU_Error_Parity		0x0138 
+#define GT_CPU_Error_Cause		0x0140 
+#define GT_CPU_Error_Mask		0x0148 
+
+#define	GT_DecodeAddr_SET(g, r, v)					\
+	do { 								\
+		gt_read((g), GT_Internal_Decode);			\
+		gt_write((g), (r), ((v) & 0xfff00000) >> 20);		\
+		while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20));	\
+	} while (0)
+
+#define	GT_LowAddr_GET(v)		 (GT__EXT((v), 0, 12) << 20)
+#define	GT_HighAddr_GET(v)		((GT__EXT((v), 0, 12) << 20) | 0xfffff)
+
+#define GT_MPP_Control0			0xf000
+#define GT_MPP_Control1			0xf004
+#define GT_MPP_Control2			0xf008
+#define GT_MPP_Control3			0xf00c
+
+/* <skf> added */
+#define GT_MPP_SerialPortMultiplex      0xf010
+
+#define	GT_GPP_IO_Control		0xf100
+#define	GT_GPP_Level_Control		0xf110
+#define GT_GPP_Value			0xf104
+#define	GT_GPP_Interrupt_Cause		0xf108
+#define GT_GPP_Interrupt_Mask		0xf10c
+/*
+ * Table 36: SCS[0]* Low Decode Address, Offset: 0x008
+ * Table 38: SCS[1]* Low Decode Address, Offset: 0x208
+ * Table 40: SCS[2]* Low Decode Address, Offset: 0x018
+ * Table 42: SCS[3]* Low Decode Address, Offset: 0x218
+ * Table 44: CS[0]*  Low Decode Address, Offset: 0x028
+ * Table 46: CS[1]*  Low Decode Address, Offset: 0x228
+ * Table 48: CS[2]*  Low Decode Address, Offset: 0x248
+ * Table 50: CS[3]*  Low Decode Address, Offset: 0x038
+ * Table 52: BootCS* Low Decode Address, Offset: 0x238
+ * Table 75: CPU 0   Low Decode Address, Offset: 0x290
+ * Table 77: CPU 1   Low Decode Address, Offset: 0x2c0
+ *
+ * 11:00 LowAddr		SCS[0] Base Address
+ * 31:12 Reserved		Must be 0.
+ */
+
+/*
+ * Table 37: SCS[0]* High Decode Address, Offset: 0x010
+ * Table 39: SCS[1]* High Decode Address, Offset: 0x210
+ * Table 41: SCS[2]* High Decode Address, Offset: 0x020
+ * Table 43: SCS[3]* High Decode Address, Offset: 0x220
+ * Table 45: CS[0]*  High Decode Address, Offset: 0x030
+ * Table 47: CS[1]*  High Decode Address, Offset: 0x230
+ * Table 49: CS[2]*  High Decode Address, Offset: 0x250
+ * Table 51: CS[3]*  High Decode Address, Offset: 0x040
+ * Table 53: BootCS* High Decode Address, Offset: 0x240
+ * Table 76: CPU 0   High Decode Address, Offset: 0x298
+ * Table 78: CPU 1   High Decode Address, Offset: 0x2c8
+ *
+ * 11:00 HighAddr		SCS[0] Top Address
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 54: PCI_0 I/O Low Decode Address,      Offset: 0x048
+ * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058
+ * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080
+ * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258
+ * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280
+ * Table 64: PCI_1 I/O Low Decode Address,      Offset: 0x090
+ * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0
+ * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0
+ * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0
+ * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0
+ *
+ * 11:00 LowAddr		PCI IO/Memory Space Base Address
+ * 23:12 Reserved
+ * 26:24 PCISwap		PCI Master Data Swap Control (0: Byte Swap;
+ *				1: No swapping; 2: Both byte and word swap;
+ *				3: Word swap; 4..7: Reserved)
+ * 27:27 PCIReq64		PCI master REQ64* policy (Relevant only when
+ *				configured to 64-bit PCI bus and not I/O)
+ *				0: Assert s REQ64* only when transaction
+ *				   is longer than 64-bits.
+ *				1: Always assert REQ64*.
+ * 31:28 Reserved
+ */
+#define	GT_PCISwap_GET(v)		GT__EXT((v), 24, 3)
+#define	GT_PCISwap_ByteSwap		0
+#define	GT_PCISwap_NoSwap		1
+#define	GT_PCISwap_ByteWordSwap		2
+#define	GT_PCISwap_WordSwap		3
+#define	GT_PCI_LowDecode_PCIReq64	GT__BIT(27)
+
+/*
+ * Table 55: PCI_0 I/O High Decode Address,      Offset: 0x050
+ * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060
+ * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088
+ * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260
+ * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288
+ * Table 65: PCI_1 I/O High Decode Address,      Offset: 0x098
+ * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8
+ * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8
+ * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8
+ * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8
+ *
+ * 11:00 HighAddr		PCI_0 I/O Space Top Address
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 74: Internal Space Decode, Offset: 0x068
+ * 15:00 IntDecode		GT64260 Internal Space Base Address
+ * 23:16 Reserved
+ * 26:24 PCISwap		Same as PCI_0 Memory 0 Low Decode Address.
+ *				NOTE: Reserved for Galileo Technology usage.
+ *				Relevant only for PCI master configuration
+ *				transactions on the PCI bus.
+ * 31:27 Reserved
+ */
+
+/*
+ * Table 79: PCI_0 I/O Address Remap,          Offset: 0x0f0
+ * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8
+ * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100
+ * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8
+ * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300
+ * Table 88: PCI_1 I/O Address Remap,          Offset: 0x108
+ * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110
+ * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118
+ * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310
+ * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318
+ *
+ * 11:00 Remap			PCI IO/Memory Space Address Remap (31:20)
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320
+ * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328
+ * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330
+ * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338
+ * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340
+ * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348
+ * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350
+ * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358
+ *
+ * 31:00 Remap			PCI Memory Address Remap (high 32 bits)
+ */
+
+/*
+ * Table 97: CPU Configuration, Offset: 0x000
+ * 07:00 NoMatchCnt		CPU Address Miss Counter
+ * 08:08 NoMatchCntEn		CPU Address Miss Counter Enable
+ *				NOTE: Relevant only if multi-GT is enabled.
+ *				(0: Disabled; 1: Enabled)
+ * 09:09 NoMatchCntExt		CPU address miss counter MSB
+ * 10:10 Reserved
+ * 11:11 AACKDelay		Address Acknowledge Delay
+ *				0: AACK* is asserted one cycle after TS*.
+ *				1: AACK* is asserted two cycles after TS*.
+ * 12:12 Endianess		Must be 0
+ *				NOTE: The GT64260 does not support the PowerPC
+ *				      Little Endian convention
+ * 13:13 Pipeline		Pipeline Enable
+ *				0: Disabled. The GT64260 will not respond with
+ *				   AACK* to a new CPU transaction, before the
+ *				   previous transaction data phase completes.
+ *				1: Enabled.
+ * 14:14 Reserved
+ * 15:15 TADelay		Transfer Acknowledge Delay
+ *				0: TA* is asserted one cycle after AACK*
+ *				1: TA* is asserted two cycles after AACK*
+ * 16:16 RdOOO			Read Out of Order Completion
+ *				0: Not Supported, Data is always returned in
+ *				   order (DTI[0-2] is always driven
+ *				1: Supported
+ * 17:17 StopRetry		Relevant only if PCI Retry is enabled
+ *				0: Keep Retry all PCI transactions targeted
+ *				   to the GT64260.
+ *				1: Stop Retry of PCI transactions.
+ * 18:18 MultiGTDec		Multi-GT Address Decode
+ *				0: Normal address decoding
+ *				1: Multi-GT address decoding
+ * 19:19 DPValid		CPU DP[0-7] Connection.  CPU write parity ...
+ *				0: is not checked. (Not connected)
+ *				1: is checked (Connected)
+ * 21:20 Reserved
+ * 22:22 PErrProp		Parity Error Propagation
+ *				0: GT64260 always drives good parity on
+ *				   DP[0-7] during CPU reads.
+ *				1: GT64260 drives bad parity on DP[0-7] in case
+ *				   the read response from the target interface
+ *				   comes with erroneous data indication
+ *				   (e.g. ECC error from SDRAM interface).
+ * 25:23 Reserved
+ * 26:26 APValid		CPU AP[0-3] Connection.  CPU address parity ...
+ *				0: is not checked. (Not connected)
+ *				1: is checked (Connected)
+ * 27:27 RemapWrDis		Address Remap Registers Write Control
+ *				0: Write to Low Address decode register.
+ *				   Results in writing of the corresponding
+ *				   Remap register.
+ *				1: Write to Low Address decode register.  No
+ *				   affect on the corresponding Remap register.
+ * 28:28 ConfSBDis		Configuration Read Sync Barrier Disable
+ *				0: enabled; 1: disabled
+ * 29:29 IOSBDis		I/O Read Sync Barrier Disable
+ *				0: enabled; 1: disabled
+ * 30:30 ClkSync		Clocks Synchronization
+ *				0: The CPU interface is running with SysClk,
+ *				   which is asynchronous to TClk.
+ *				1: The CPU interface is running with TClk.
+ * 31:31 Reserved
+ */
+#define	GT_CPUCfg_NoMatchCnt_GET(v)	GT__EXT((v), 0, 8)
+#define	GT_CPUCfg_NoMatchCntEn		GT__BIT( 9)
+#define	GT_CPUCfg_NoMatchCntExt		GT__BIT(10)
+#define	GT_CPUCfg_AACKDelay		GT__BIT(11)
+#define	GT_CPUCfg_Endianess		GT__BIT(12)
+#define	GT_CPUCfg_Pipeline		GT__BIT(13)
+#define	GT_CPUCfg_TADelay		GT__BIT(15)
+#define	GT_CPUCfg_RdOOO			GT__BIT(16)
+#define	GT_CPUCfg_StopRetry		GT__BIT(17)
+#define	GT_CPUCfg_MultiGTDec		GT__BIT(18)
+#define	GT_CPUCfg_DPValid		GT__BIT(19)
+#define	GT_CPUCfg_PErrProp		GT__BIT(22)
+#define	GT_CPUCfg_APValid		GT__BIT(26)
+#define	GT_CPUCfg_RemapWrDis		GT__BIT(27)
+#define	GT_CPUCfg_ConfSBDis		GT__BIT(28)
+#define	GT_CPUCfg_IOSBDis		GT__BIT(29)
+#define	GT_CPUCfg_ClkSync		GT__BIT(30)
+
+/*
+ * Table 98: CPU Mode, Offset: 0x120, Read only
+ * 01:00 MultiGTID		Multi-GT ID
+ *				Represents the ID to which the GT64260 responds
+ *				to during a multi-GT address decoding period.
+ * 02:02 MultiGT		(0: Single; 1: Multiple) GT configuration
+ * 03:03 RetryEn		(0: Don't; 1: Do) Retry PCI transactions
+ * 07:04 CPUType
+ *				0x0-0x3: Reserved
+ *				0x4:     64-bit PowerPC CPU, 60x bus
+ *				0x5:     64-bit PowerPC CPU, MPX bus
+ *				0x6-0xf: Reserved
+ * 31:08 Reserved
+ */
+#define	GT_CPUMode_MultiGTID_GET(v)	GT__EXT(v, 0, 2)
+#define GT_CPUMode_MultiGT		GT__BIT(2)
+#define GT_CPUMode_RetryEn		GT__BIT(3)
+#define	GT_CPUMode_CPUType_GET(v)	GT__EXT(v, 4, 4)
+
+/*
+ * Table 99: CPU Master Control, Offset: 0x160
+ * 07:00 Reserved
+ * 08:08 IntArb			CPU Bus Internal Arbiter Enable
+ *				NOTE: Only relevant to 60x bus mode. When
+ *				      running MPX bus, the GT64260 internal
+ *				      arbiter must be used.
+ *				0: Disabled.  External arbiter is required.
+ *				1: Enabled.  Use the GT64260 CPU bus arbiter.
+ * 09:09 IntBusCtl		CPU Interface Unit Internal Bus Control
+ *				NOTE: This bit must be set to 1. It is reserved
+ *				      for Galileo Technology usage.
+ *				0: Enable internal bus sharing between master
+ *				   and slave interfaces.
+ *				1: Disable internal bus sharing between master
+ *				   and slave interfaces.
+ * 10:10 MWrTrig		Master Write Transaction Trigger
+ *				0: With first valid write data
+ *				1: With last valid write data
+ * 11:11 MRdTrig		Master Read Response Trigger
+ *				0: With first valid read data
+ *				1: With last valid read data
+ * 12:12 CleanBlock		Clean Block Snoop Transaction Support
+ *				0: CPU does not support clean block (603e,750)
+ *				1: CPU supports clean block (604e,G4)
+ * 13:13 FlushBlock		Flush Block Snoop Transaction Support
+ *				0: CPU does not support flush block (603e,750)
+ *				1: CPU supports flush block (604e,G4)
+ * 31:14 Reserved
+ */
+#define GT_CPUMstrCtl_IntArb			GT__BIT(8)
+#define GT_CPUMstrCtl_IntBusCtl			GT__BIT(9)
+#define GT_CPUMstrCtl_MWrTrig			GT__BIT(10)
+#define GT_CPUMstrCtl_MRdTrig			GT__BIT(11)
+#define GT_CPUMstrCtl_CleanBlock		GT__BIT(12)
+#define GT_CPUMstrCtl_FlushBlock		GT__BIT(13)
+
+#define	GT_ArbSlice_SDRAM	0x0	/* SDRAM interface snoop request */
+#define GT_ArbSlice_DEVICE	0x1	/* Device request */
+#define GT_ArbSlice_NULL	0x2	/* NULL request */
+#define GT_ArbSlice_PCI0	0x3	/* PCI_0 access */
+#define GT_ArbSlice_PCI1	0x4	/* PCI_1 access */
+#define GT_ArbSlice_COMM	0x5	/* Comm unit access */
+#define GT_ArbSlice_IDMA0123	0x6	/* IDMA channels 0/1/2/3 access */
+#define GT_ArbSlice_IDMA4567	0x7	/* IDMA channels 4/5/6/7 access */
+					/* 0x8-0xf: Reserved */
+
+/* Pass in the slice number (from 0..16) as 'n'
+ */
+#define	GT_XbarCtl_GET_ArbSlice(v, n)		GT__EXT((v), (((n) & 7)*4, 4)
+
+/*
+ * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150
+ * 03:00 Arb0			Slice  0 of CPU Master pizza Arbiter
+ * 07:04 Arb1			Slice  1 of CPU Master pizza Arbiter
+ * 11:08 Arb2			Slice  2 of CPU Master pizza Arbiter
+ * 15:12 Arb3			Slice  3 of CPU Master pizza Arbiter
+ * 19:16 Arb4			Slice  4 of CPU Master pizza Arbiter
+ * 23:20 Arb5			Slice  5 of CPU Master pizza Arbiter
+ * 27:24 Arb6			Slice  6 of CPU Master pizza Arbiter
+ * 31:28 Arb7			Slice  7 of CPU Master pizza Arbiter
+ */
+
+/*
+ * Table 101: CPU Interface Crossbar Control High, Offset: 0x158
+ * 03:00 Arb8			Slice  8 of CPU Master pizza Arbiter
+ * 07:04 Arb9			Slice  9 of CPU Master pizza Arbiter
+ * 11:08 Arb10			Slice 10 of CPU Master pizza Arbiter
+ * 15:12 Arb11			Slice 11 of CPU Master pizza Arbiter
+ * 19:16 Arb12			Slice 12 of CPU Master pizza Arbiter
+ * 23:20 Arb13			Slice 13 of CPU Master pizza Arbiter
+ * 27:24 Arb14			Slice 14 of CPU Master pizza Arbiter
+ * 31:28 Arb15			Slice 15 of CPU Master pizza Arbiter
+ */
+
+/*
+ * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168
+ * NOTE: Reserved for Galileo Technology usage.
+ * 07:00 Timeout		Crossbar Arbiter Timeout Preset Value
+ * 15:08 Reserved
+ * 16:16 TimeoutEn		Crossbar Arbiter Timer Enable
+ *				(0: Enable; 1: Disable)
+ * 31:17 Reserved
+ */
+
+/*
+ * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170
+ * 03:00 Arb0			Slice  0 of CPU Slave pizza Arbiter
+ * 07:04 Arb1			Slice  1 of CPU Slave pizza Arbiter
+ * 11:08 Arb2			Slice  2 of CPU Slave pizza Arbiter
+ * 15:12 Arb3			Slice  3 of CPU Slave pizza Arbiter
+ * 19:16 Arb4			Slice  4 of CPU Slave pizza Arbiter
+ * 23:20 Arb5			Slice  5 of CPU Slave pizza Arbiter
+ * 27:24 Arb6			Slice  6 of CPU Slave pizza Arbiter
+ * 31:28 Arb7			Slice  7 of CPU Slave pizza Arbiter
+ */
+/*
+ * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178
+ * 03:00 Arb8			Slice  8 of CPU Slave pizza Arbiter
+ * 07:04 Arb9			Slice  9 of CPU Slave pizza Arbiter
+ * 11:08 Arb10			Slice 10 of CPU Slave pizza Arbiter
+ * 15:12 Arb11			Slice 11 of CPU Slave pizza Arbiter
+ * 19:16 Arb12			Slice 12 of CPU Slave pizza Arbiter
+ * 23:20 Arb13			Slice 13 of CPU Slave pizza Arbiter
+ * 27:24 Arb14			Slice 14 of CPU Slave pizza Arbiter
+ * 31:28 Arb15			Slice 15 of CPU Slave pizza Arbiter
+ */ 
+
+/*
+ * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0
+ * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8
+ *   NOTE: The read data is random and should be ignored.
+ * 31:00 SyncBarrier		A CPU read from this register creates a
+ *				synchronization barrier cycle.
+ */
+
+/*
+ * Table 107: CPU Protect Address 0 Low, Offset: 0x180
+ * Table 109: CPU Protect Address 1 Low, Offset: 0x190
+ * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0
+ * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0
+ * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0
+ * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0
+ * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0
+ * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0
+ *
+ * 11:00 LowAddr		CPU Protect Region Base Address
+ *				Corresponds to address bits[31:20].
+ * 15:12 Reserved.		Must be 0
+ * 16:16 AccProtect		CPU Access Protect
+ *				Access is (0: allowed; 1: forbidden)
+ * 17:17 WrProtect		CPU Write Protect
+ *				Writes are (0: allowed; 1: forbidden)
+ * 18:18 CacheProtect		CPU caching protect. 	Caching (block read)
+ *				is (0: allowed; 1: forbidden)
+ * 31:19 Reserved
+ */
+#define GT_CPU_AccProtect			GT__BIT(16)
+#define GT_CPU_WrProtect			GT__BIT(17)
+#define GT_CPU_CacheProtect			GT__BIT(18)
+
+/* 
+ * Table 108: CPU Protect Address 0 High, Offset: 0x188
+ * Table 110: CPU Protect Address 1 High, Offset: 0x198
+ * Table 112: CPU Protect Address 2 High, Offset: 0x1a8
+ * Table 114: CPU Protect Address 3 High, Offset: 0x1b8
+ * Table 116: CPU Protect Address 4 High, Offset: 0x1c8
+ * Table 118: CPU Protect Address 5 High, Offset: 0x1d8
+ * Table 120: CPU Protect Address 6 High, Offset: 0x1e8
+ * Table 122: CPU Protect Address 7 High, Offset: 0x1f8
+ *
+ * 11:00 HighAddr		CPU Protect Region Top Address
+ *				Corresponds to address bits[31:20]
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 123: Snoop Base Address 0, Offset: 0x380
+ * Table 125: Snoop Base Address 1, Offset: 0x390
+ * Table 127: Snoop Base Address 2, Offset: 0x3a0
+ * Table 129: Snoop Base Address 3, Offset: 0x3b0
+ *
+ * 11:00 LowAddr		Snoop Region Base Address [31:20]
+ * 15:12 Reserved		Must be 0.
+ * 17:16 Snoop			Snoop Type
+ *				0x0: No Snoop
+ *				0x1: Snoop to WT region
+ *				0x2: Snoop to WB region
+ *				0x3: Reserved
+ * 31:18 Reserved
+ */
+#define GT_Snoop_GET(v)				GT__EXT((v), 16, 2)
+#define GT_Snoop_INS(v)				GT__INS((v), 16)
+#define	GT_Snoop_None				0
+#define	GT_Snoop_WT				1
+#define	GT_Snoop_WB				2
+
+
+/*
+ * Table 124: Snoop Top Address 0, Offset: 0x388
+ * Table 126: Snoop Top Address 1, Offset: 0x398
+ * Table 128: Snoop Top Address 2, Offset: 0x3a8
+ * Table 130: Snoop Top Address 3, Offset: 0x3b8
+ * 11:00 HighAddr		Snoop Region Top Address [31:20]
+ * 31:12 Reserved
+ */
+
+
+/*
+ * Table 131: CPU Error Address Low, Offset: 0x070, Read Only.
+ *   In case of multiple errors, only the first one is latched.  New error
+ *   report latching is enabled only after the CPU Error Address Low register
+ *   is being read.
+ * 31:00 ErrAddr		Latched address bits [31:0] of a CPU
+ *				transaction in case of:
+ *				o illegal address (failed address decoding)
+ *				o access protection violation
+ *				o bad data parity
+ *				o bad address parity
+ *				Upon address latch, no new address are
+ *				registered (due to additional error condition),
+ *				until the register is being read.
+ */
+
+/*
+ * Table 132: CPU Error Address High, Offset: 0x078, Read Only.
+ *   Once data is latched, no new data can be registered (due to additional
+ *   error condition), until CPU Error Low Address is being read (which
+ *   implies, it should be the last being read by the interrupt handler).
+ * 03:00 Reserved
+ * 07:04 ErrPar			Latched address parity bits in case
+ *				of bad CPU address parity detection.
+ * 31:08 Reserved
+ */
+#define	GT_CPUErrorAddrHigh_ErrPar_GET(v)	GT__EXT((v), 4, 4)
+
+/*
+ * Table 133: CPU Error Data Low, Offset: 0x128, Read only.
+ * 31:00 PErrData		Latched data bits [31:0] in case of bad data
+ *				parity sampled on write transactions or on
+ *				master read transactions.
+ */
+
+/*
+ * Table 134: CPU Error Data High, Offset: 0x130, Read only.
+ * 31:00 PErrData		Latched data bits [63:32] in case of bad data
+ *				parity sampled on write transactions or on
+ *				master read transactions.
+ */
+
+/*
+ * Table 135: CPU Error Parity, Offset: 0x138, Read only.
+ * 07:00 PErrPar		Latched data parity bus in case of bad data
+ *				parity sampled on write transactions or on
+ *				master read transactions.
+ * 31:10 Reserved
+ */
+#define	GT_CPUErrorParity_PErrPar_GET(v)	GT__EXT((v), 0, 8)
+
+/*
+ * Table 136: CPU Error Cause, Offset: 0x140
+ *   Bits[7:0] are clear only. A cause bit is set upon an error condition
+ *   occurrence. Write a 0 value to clear the bit.  Writing a 1 value has
+ *   no affect.
+ * 00:00 AddrOut		CPU Address Out of Range
+ * 01:01 AddrPErr		Bad Address Parity Detected
+ * 02:02 TTErr			Transfer Type Violation.
+ *				The CPU attempts to burst (read or write) to an
+ *				internal register.
+ * 03:03 AccErr			Access to a Protected Region
+ * 04:04 WrErr			Write to a Write Protected Region
+ * 05:05 CacheErr		Read from a Caching protected region
+ * 06:06 WrDataPErr		Bad Write Data Parity Detected
+ * 07:07 RdDataPErr		Bad Read Data Parity Detected
+ * 26:08 Reserved
+ * 31:27 Sel			Specifies the error event currently being
+ *				reported in Error Address, Error Data, and
+ *				Error Parity registers.
+ *				0x0: AddrOut
+ *				0x1: AddrPErr
+ *				0x2: TTErr
+ *				0x3: AccErr
+ *				0x4: WrErr
+ *				0x5: CacheErr
+ *				0x6: WrDataPErr
+ *				0x7: RdDataPErr
+ *				0x8-0x1f: Reserved
+ */
+#define GT_CPUError_AddrOut		GT__BIT(GT_CPUError_Sel_AddrOut)
+#define GT_CPUError_AddrPErr		GT__BIT(GT_CPUError_Sel_AddrPErr)
+#define GT_CPUError_TTErr		GT__BIT(GT_CPUError_Sel_TTErr)
+#define GT_CPUError_AccErr		GT__BIT(GT_CPUError_Sel_AccErr)
+#define GT_CPUError_WrErr		GT__BIT(GT_CPUError_Sel_WrPErr)
+#define GT_CPUError_CacheErr		GT__BIT(GT_CPUError_Sel_CachePErr)
+#define GT_CPUError_WrDataPErr		GT__BIT(GT_CPUError_Sel_WrDataPErr)
+#define GT_CPUError_RdDataPErr		GT__BIT(GT_CPUError_Sel_RdDataPErr)
+
+#define GT_CPUError_Sel_AddrOut		0
+#define GT_CPUError_Sel_AddrPErr	1
+#define GT_CPUError_Sel_TTErr		2
+#define GT_CPUError_Sel_AccErr		3
+#define GT_CPUError_Sel_WrErr		4
+#define GT_CPUError_Sel_CacheErr	5
+#define GT_CPUError_Sel_WrDataPErr	6
+#define GT_CPUError_Sel_RdDataPErr	7
+
+#define	GT_CPUError_Sel_GET(v)		GT__EXT((v), 27, 5)
+
+/*
+ * Table 137: CPU Error Mask, Offset: 0x148
+ * 00:00 AddrOut		If set to 1, enables AddrOut interrupt.
+ * 01:01 AddrPErr		If set to 1, enables AddrPErr interrupt.
+ * 02:02 TTErr			If set to 1, enables TTErr interrupt.
+ * 03:03 AccErr			If set to 1, enables AccErr interrupt.
+ * 04:04 WrErr			If set to 1, enables WrErr interrupt.
+ * 05:05 CacheErr		If set to 1, enables CacheErr interrupt.
+ * 06:06 WrDataPErr		If set to 1, enables WrDataPErr interrupt.
+ * 07:07 RdDataPErr		If set to 1, enables RdDataPErr interrupt.
+ * 31:08 Reserved
+ */
+
+/* Comm Unit Arbiter Control */
+#define GT_CommUnitArb_Ctrl     0xf300    /*<skf>*/
+/*
+ * Comm Unit Interrupt registers
+ */
+#define GT_CommUnitIntr_Cause	0xf310
+#define GT_CommUnitIntr_Mask	0xf314
+#define GT_CommUnitIntr_ErrAddr	0xf318
+
+#define GT_CommUnitIntr_E0	0x00000007
+#define GT_CommUnitIntr_E1	0x00000070
+#define GT_CommUnitIntr_E2	0x00000700
+#define GT_CommUnitIntr_S0	0x00070000
+#define GT_CommUnitIntr_S1	0x00700000
+#define GT_CommUnitIntr_Sel	0x70000000
+
+/*
+ * SDRAM Error Report (ECC) Registers
+ */
+#define GT_ECC_Data_Lo		0x484	/* latched Error Data (low) */
+#define GT_ECC_Data_Hi		0x480	/* latched Error Data (high) */
+#define GT_ECC_Addr		0x490	/* latched Error Address */
+#define GT_ECC_Rec		0x488	/* latched ECC code from SDRAM */
+#define GT_ECC_Calc		0x48c	/* latched ECC code from SDRAM */
+#define GT_ECC_Ctl		0x494	/* ECC Control */
+#define GT_ECC_Count		0x498	/* ECC 1-bit error count */
+
+/*
+ * Watchdog Registers
+ */
+#define GT_WDOG_Config		0xb410
+#define GT_WDOG_Value		0xb414
+#define GT_WDOG_Value_NMI	GT__MASK(24)
+#define GT_WDOG_Config_Preset	GT__MASK(24)
+#define GT_WDOG_Config_Ctl1a	GT__BIT(24)
+#define GT_WDOG_Config_Ctl1b	GT__BIT(25)
+#define GT_WDOG_Config_Ctl2a	GT__BIT(26)
+#define GT_WDOG_Config_Ctl2b	GT__BIT(27)
+#define GT_WDOG_Config_Enb	GT__BIT(31)
+
+#define GT_WDOG_NMI_DFLT	(GT__MASK(24) & GT_WDOG_Value_NMI)
+#define GT_WDOG_Preset_DFLT	(GT__MASK(22) & GT_WDOG_Config_Preset)
+
+/*
+ * Device Bus Interrupts
+ */
+#define GT_DEVBUS_ICAUSE	0x4d0	/* Device Interrupt Cause */
+#define GT_DEVBUS_IMASK		0x4d4	/* Device Interrupt Mask */
+#define GT_DEVBUS_ERR_ADDR	0x4d8	/* Device Error Address */
+
+/*
+ * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK
+ */
+#define GT_DEVBUS_DBurstErr	GT__BIT(0)
+#define GT_DEVBUS_DRdyErr	GT__BIT(1)
+#define GT_DEVBUS_Sel		GT__BIT(27)
+#define GT_DEVBUS_RES	~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel)
+
+/* TWSI Interface - TWSI Interface Registers <skf> */
+#define TWSI_SLV_ADDR		0xc000
+#define TWSI_EXT_SLV_ADDR	0xc010
+#define TWSI_DATA		0xc004
+#define TWSI_CTRL		0xc008
+#define TWSI_STATUS		0xc00c
+#define TWSI_BAUDE_RATE		0xc00c
+#define TWSI_SFT_RST		0xc01c
+
+/* Interrupt Controller - Interrupt Controller Registers */
+/* Section 25.2 : Table 734 <skf> */
+
+#define GT_MAIN_INT_CAUSE_LO	0xc18 /* read Only */
+#define GT_MAIN_INT_CAUSE_HI   0xc68 /* read Only */
+#define GT_CPU_INT_MASK_LO 	0xc1c
+#define GT_CPU_INT_MASK_HI	0xc6c
+#define GT_CPU_SEL_CAUSE	0xc70 /* read Only */
+#define GT_PCI0_INT_MASK_LO	0xc24
+#define GT_PCI0_INT_MASK_HI	0xc64
+#define GT_PCI0_SEL_CAUSE	0xc74 /* read Only */
+#define GT_PCI1_INT_MASK_LO	0xca4
+#define GT_PCI1_INT_MASK_HI	0xce4
+#define GT_PCI1_SEL_CAUSE	0xcf4 /* read Only */
+#define GT_CPU_INT0_MASK	0xe60
+#define GT_CPU_INT1_MASK	0xe64
+#define GT_CPU_INT2_MASK	0xe68
+#define GT_CPU_INT3_MASK	0xe6c
+
+#endif /* !_DISCOVERY_DEV_GTREG_H */