This is a large patch from Eric Valette <valette@crf.canon.fr> that was

described in the message following this paragraph.  This patch also includes
a mcp750 BSP.

From valette@crf.canon.fr Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@crf.canon.fr>
To: joel@oarcorp.com
Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr
Subject: Questions/Suggestion regarding RTEMS PowerPC code (long)


Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

	1) a MPC750 233 MHz processor,
	2) a raven bus bridge/PCI controller that
	implement an OPENPIC compliant interrupt controller,
	3) a VIA 82C586 PCI/ISA bridge that offers a PC
	compliant IO for keyboard, serial line, IDE, and
	the well known PC 8259 cascaded PIC interrupt
	architecture model,
	4) a DEC 21140 Ethernet controller,
	5) the PPCBUG Motorola firmware in flash,
	6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :
	1) on VME board, the DEC PCI bridge is replaced by
	a VME chipset,
	2) the VIA 82C586 PCI/ISA bridge is replaced by
	another bridge that is almost fully compatible
	with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1)  EXCEPTION CODE
-------------------

As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

	a) Except for the decrementer exception (and
	maybe some other on mpc8xx), exceptions are
	not recoverable and the handler just need to print
	the full context and go to the firmware or debugger...
	b) The interrupt switch is only necessary for the
	decrementer and external interrupt (at least on
	6xx,7xx).
	c) The full context for exception is never saved and
	thus cannot be used by debugger... I do understand
	the most important for interrupts low level code
	is to save the minimal context enabling	to call C
	code for performance reasons. On non recoverable
	exception on the other hand, the most important is
	to save the maximum information concerning proc status
	in order to analyze the reason of the fault. At
	least we will need this in order to implement the
	port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code
-----------------------------------------------

I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)
	mfmsr	r5
	mfspr   r6, sprg2
#else
        lwz	r6,msr_initial(r11)
	lis     r5,~PPC_MSR_DISABLE_MASK@ha
        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
	and	r6,r6,r5
	mfmsr	r5
#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

	a) I want the MSR[IR] and MSR[DR] to be set for
	performance reasons and also because I need DBAT
	support to have access to PCI memory space as the
	interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217
 *
 * We need address translation ON when we call our ISR routine

	mtmsr	r5

 */

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation
----------------------------------------------

I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))
-------------------------------------------

I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

	a) registers access routine (e.g GET_MSR_Value),
	b) interrupt masking/unmasking routines,
	c) cache_mngt_routine,
	d) mmu_mngt_routine,
	e) Routines to connect the raw_exception, raw_interrupt
	handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x)  the directory structure
is fine (except maybe the names that are not homogeneous)

	powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

		powerpc

mpc421 	mpc821	...	mpc750	shared wrapup

with the following rules :

	a) "shared" would act as a source container for sources that may
	be shared among processors. Needed files would be compiled inside
	the processor specific directory using the vpath Makefile
	mechanism. "shared" may also contain compilation code
	for routine that are really shared and not worth to inline...
	(did not found many things so far as registers access routine
	ARE WORTH INLINING)... In the case something is compiled there,
	it should create libcpushared.a

	b) layout under processor specific directory is free provided
	that
		1)the result of the compilation process exports :

		libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

		2) each processor specific directory creates
		a library called libcpuspecific.a
	Note that this organization enables to have a file that
	is nearly the same than in shared but that must differ
	because of processor differences...

	c) "wrapup" should create libcpu.a using libcpushared.a
	libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

	1) things are compiled in the wrap directory,
	2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),


5) Interrupt handling API
-------------------------

Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


---------    0  ------
| OPEN	| <-----|8259|
| PIC	|	|    |    2  ------
|(RAVEN)|	|    | <-----|8259|
|	|	|    |	     |    |   11
|	|	|    |	     |    | <----
|	|	|    |	     |    |
|	|	|    |	     |    |
---------       ------	     |    |
    ^			     ------
    |		VIA PCI/ISA bridge
    |  x
    -------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

	1) there is no way to specify priorities among
	interrupts handler. This is REALLY a bad thing.
	For me it is as importnat as having priorities
	for threads...
	2) for my implementation, each ISR should
	contain the code that acknowledge the RAVEN
	and 8259 cascade, modify interrupt mask on both
	chips, and reenable interrupt at processor level,
	..., restore then on interrupt return,.... This code
	is actually similar to code located in some
	genpvec.c powerpc files,
	3) I must update _ISR_Nesting_level because
	irq.inl use it...
	4) the libchip code connects the ISR via set_vector
	but the libchip handler code does not contain any code to
	manipulate external interrupt controller hardware
	in order to acknoledge the interrupt or re-enable
	them (except for the target hardware of course)
	So this code is broken unless set_vector adds an
	additionnal prologue/epilogue before calling/returning
	from in order to acknoledge/mask the raven and the
	8259 PICS... => Anyway already EACH BSP MUST REWRITE
	PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
	SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

	1) Once the driver supplied methods is called the
	only things the ISR has to do is to worry about the
	external hardware that triggered the interrupt.
	Everything on openpic/VIA/processor would have been
	done by the low levels (same things as set-vector)
	2) The caller will need to supply the on/off/isOn
	routine that are fundamental to correctly implements
	debuggers/performance monitoring is a portable way
	3) A globally configurable interrupt priorities
	mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in  other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

	1) Put in a processor specific section,
	2) Should not rely on a global variable,

As :
	a) on symmetric MP, there is one interrupt level
	per CPU,
	b) On processor that have an ISP (e,g 68040),
	this variable is useless (MSR bit testing could
	be used)
	c) On PPC, instead of using the address of the
	variable via __CPU_IRQ_info.Nest_level a dedicated
	SPR could be used.

NOTE:	most of this is also true for _Thread_Dispatch_disable_level


END NOTE
--------

Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :
	1) try to better understand the actual code,
	2) propose concrete ways of enhancing current code
	by providing an alternative implementation for MCP750. I
	will make my best effort to try to brake nothing but this
	is actually hard due to the file layout organisation.
	3) make understandable some changes I will probably make
	if joel let me do them :-)

Any comments/objections are welcomed as usual.



--
   __
  /  `                   	Eric Valette
 /--   __  o _.          	Canon CRF
(___, / (_(_(__         	Rue de la touche lambert
				35517 Cesson-Sevigne  Cedex
				FRANCE
Tel: +33 (0)2 99 87 68 91	Fax: +33 (0)2 99 84 11 30
E-mail: valette@crf.canon.fr

4 files changed, 429 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/Makefile.in b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/Makefile.in
new file mode 100644
index 0000000000..c5175cde3f
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/Makefile.in
@@ -0,0 +1,64 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@:@srcdir@/../console:
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+PGM=${ARCH}/vectors.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=vectors_init 
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/vectors.h
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=vectors 
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+OBJS=$(S_O_FILES) $(C_O_FILES) $(CC_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+all:	${ARCH} $(SRCS) preinstall $(OBJS) $(PGM)
+
+
diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S
new file mode 100644
index 0000000000..7fe6a82f73
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S
@@ -0,0 +1,142 @@
+/*
+ * (c) 1999, Eric Valette valette@crf.canon.fr
+ *
+ *
+ *  This file contains the assembly code for the PowerPC 
+ *  exception veneers for RTEMS.
+ *
+ * $Id$
+ */
+	
+
+
+#include <bsp/vectors.h>
+#include <libcpu/cpu.h>
+#include <rtems/score/targopts.h>
+#include "asm.h"
+	
+
+#define SYNC \
+	sync; \
+	isync
+	
+	PUBLIC_VAR (__rtems_start)
+	.section .entry_point_section,"awx",@progbits
+/*
+ * Entry point information used by bootloader code
+ */
+SYM (__rtems_start):		
+	.long   __rtems_entry_point
+
+	/*
+	 * end of special Entry point section
+	 */	
+	.text
+	.p2align 5	
+		
+PUBLIC_VAR(default_exception_vector_code_prolog)
+SYM (default_exception_vector_code_prolog):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r3, GPR3_OFFSET(r1)
+	stw	r2, GPR2_OFFSET(r1)
+	mflr	r2
+	stw	r2, EXC_LR_OFFSET(r1)
+	bl	0f
+0:	/*
+	 * r3 = exception vector entry point 
+	 * (256 * vector number) + few instructions
+	 */
+	mflr	r3
+	/*
+	 * r3 = r3 >> 8 = vector
+	 */
+	srwi	r3,r3,8
+	ba	push_normalized_frame
+	
+	PUBLIC_VAR (default_exception_vector_code_prolog_size)
+	
+	default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog
+	
+	.p2align 5
+PUBLIC_VAR (push_normalized_frame)	
+SYM (push_normalized_frame):
+	stw	r3, EXCEPTION_NUMBER_OFFSET(r1)
+	stw	r0, GPR0_OFFSET(r1)
+	mfsrr0  r2
+	stw	r2, SRR0_FRAME_OFFSET(r1)
+	mfsrr1  r3
+	stw	r3, SRR1_FRAME_OFFSET(r1)
+	/*
+	 * Save general purpose registers
+	 * Already saved in prolog : R1, R2, R3, LR.
+	 * Saved a few line above  : R0
+	 *
+	 * Manual says that "stmw" instruction may be slower than
+	 * series of individual "stw" but who cares about performance 
+	 * for the DEFAULT exception handler?
+	 */
+	stmw	r4, GPR4_OFFSET(r1)	/* save R4->R31 */
+
+	mfcr	r31
+	stw	r31,  EXC_CR_OFFSET(r1)
+	mfctr	r30
+	stw	r30,  EXC_CTR_OFFSET(r1)
+	mfxer	r28
+	stw	r28,  EXC_XER_OFFSET(r1)
+	/*
+	 * Enable data and instruction address translation, exception nesting
+	 */
+	mfmsr	r3
+	ori     r3,r3, MSR_RI | MSR_IR | MSR_DR
+	mtmsr   r3
+	SYNC
+	
+	/*
+	 * Call C exception handler
+	 */
+	addi	r3, r1, 0x8
+	bl C_exception_handler
+	/*
+	 * Restore registers status
+	 */
+	lwz	r31,  EXC_CR_OFFSET(r1)
+	mtcr	r31
+	lwz	r30,  EXC_CTR_OFFSET(r1)
+	mtctr	r30
+	lwz	r29,  EXC_LR_OFFSET(r1)
+	mtlr	r29
+	lwz	r28,  EXC_XER_OFFSET(r1)
+	mtxer	r28
+
+	lmw	r4, GPR4_OFFSET(r1)
+	lwz	r2, GPR2_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)
+
+	/*
+	 * Disable data and instruction translation. Make path non recoverable...
+	 */
+	mfmsr	r3
+	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
+	mtmsr   r3
+	SYNC
+	/*
+	 * Restore rfi related settings
+	 */
+		 
+	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	mtsrr1	r3
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	mtsrr0	r3
+	
+	lwz	r3, GPR3_OFFSET(r1)
+	addi 	r1,r1, EXCEPTION_FRAME_END
+	SYNC
+	rfi
+
+
+
+
+
diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h
new file mode 100644
index 0000000000..2613ec9b43
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h
@@ -0,0 +1,123 @@
+#ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
+#define LIBBSP_POWERPC_MCP750_VECTORS_H
+
+/*
+ * The callee (high level exception code written in C) 
+ * will store the Link Registers (return address) at entry r1 + 4 !!!.
+ * So let room for it!!!.
+ */ 
+#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
+#define SRR0_FRAME_OFFSET 8
+#define SRR1_FRAME_OFFSET 12
+#define EXCEPTION_NUMBER_OFFSET 16
+#define GPR0_OFFSET 20
+#define GPR1_OFFSET 24
+#define GPR2_OFFSET 28
+#define GPR3_OFFSET 32
+#define GPR4_OFFSET 36
+#define GPR5_OFFSET 40
+#define GPR6_OFFSET 44
+#define GPR7_OFFSET 48
+#define GPR8_OFFSET 52
+#define GPR9_OFFSET 56
+#define GPR10_OFFSET 60
+#define GPR11_OFFSET 64
+#define GPR12_OFFSET 68
+#define GPR13_OFFSET 72
+#define GPR14_OFFSET 76
+#define GPR15_OFFSET 80
+#define GPR16_OFFSET 84
+#define GPR17_OFFSET 88
+#define GPR18_OFFSET 92
+#define GPR19_OFFSET 96
+#define GPR20_OFFSET 100
+#define GPR21_OFFSET 104
+#define GPR22_OFFSET 108
+#define GPR23_OFFSET 112
+#define GPR24_OFFSET 116
+#define GPR25_OFFSET 120
+#define GPR26_OFFSET 124
+#define GPR27_OFFSET 128
+#define GPR28_OFFSET 132
+#define GPR29_OFFSET 136
+#define GPR30_OFFSET 140
+#define GPR31_OFFSET 144
+#define EXC_CR_OFFSET 148
+#define EXC_CTR_OFFSET 152
+#define EXC_XER_OFFSET 156
+#define EXC_LR_OFFSET 160
+#define EXC_DAR_OFFSET 164
+/*
+ * maintain the EABI requested 8 bytes aligment
+ * As SVR4 ABI requires 16, make it 16 (as some
+ * exception may need more registers to be processed...)
+ */
+#define    EXCEPTION_FRAME_END 176
+
+#ifndef ASM
+/*
+ * default raw exception handlers
+ */
+
+extern	void default_exception_vector_code_prolog();
+extern	int  default_exception_vector_code_prolog_size;
+
+/* codemove is like memmove, but it also gets the cache line size
+ * as 4th parameter to synchronize them. If this last parameter is
+ * zero, it performs more or less like memmove. No copy is performed if
+ * source and destination addresses are equal. However the caches
+ * are synchronized. Note that the size is always rounded up to the
+ * next mutiple of 4. 
+ */
+extern void * codemove(void *, const void *, unsigned int, unsigned long);
+extern void initialize_exceptions();
+
+typedef struct {
+  unsigned 	EXC_SRR0;
+  unsigned 	EXC_SRR1;
+  unsigned	_EXC_number;
+  unsigned	GPR0;
+  unsigned	GPR1;
+  unsigned	GPR2;
+  unsigned	GPR3;
+  unsigned	GPR4;
+  unsigned	GPR5;
+  unsigned	GPR6;
+  unsigned	GPR7;
+  unsigned	GPR8;
+  unsigned	GPR9;
+  unsigned	GPR10;
+  unsigned	GPR11;
+  unsigned	GPR12;
+  unsigned	GPR13;
+  unsigned	GPR14;
+  unsigned	GPR15;
+  unsigned	GPR16;
+  unsigned	GPR17;
+  unsigned	GPR18;
+  unsigned	GPR19;
+  unsigned	GPR20;
+  unsigned	GPR21;
+  unsigned	GPR22;
+  unsigned	GPR23;
+  unsigned	GPR24;
+  unsigned	GPR25;
+  unsigned	GPR26;
+  unsigned	GPR27;
+  unsigned	GPR28;
+  unsigned	GPR29;
+  unsigned	GPR30;
+  unsigned	GPR31;
+  unsigned 	EXC_CR;
+  unsigned 	EXC_CTR;
+  unsigned 	EXC_XER;
+  unsigned	EXC_LR;
+  unsigned 	EXC_MSR;
+  unsigned	EXC_DAR;
+} exception_frame;
+
+extern void C_exception_handler(exception_frame* excPtr);
+
+#endif /* ASM */
+
+#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */
diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c
new file mode 100644
index 0000000000..9efc708e4e
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c
@@ -0,0 +1,100 @@
+/*
+ *
+ */
+#include <bsp/vectors.h>
+#include <libcpu/raw_exception.h>
+
+static rtems_raw_except_global_settings exception_config;
+static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
+
+void C_exception_handler(exception_frame* excPtr)
+{
+  int recoverable = 0;
+  
+  printk("exception handler called for exception %d\n", excPtr->_EXC_number);
+  printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0);
+  printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1);
+  printk("\t R0 = %x\n", excPtr->GPR0);
+  printk("\t R1 = %x\n", excPtr->GPR1);
+  printk("\t R2 = %x\n", excPtr->GPR2);
+  printk("\t R3 = %x\n", excPtr->GPR3);
+  printk("\t R4 = %x\n", excPtr->GPR4);
+  printk("\t R5 = %x\n", excPtr->GPR5);
+  printk("\t R6 = %x\n", excPtr->GPR6);
+  printk("\t R7 = %x\n", excPtr->GPR7);
+  printk("\t R8 = %x\n", excPtr->GPR8);
+  printk("\t R9 = %x\n", excPtr->GPR9);
+  printk("\t R10 = %x\n", excPtr->GPR10);
+  printk("\t R11 = %x\n", excPtr->GPR11);
+  printk("\t R12 = %x\n", excPtr->GPR12);
+  printk("\t R13 = %x\n", excPtr->GPR13);
+  printk("\t R14 = %x\n", excPtr->GPR14);
+  printk("\t R15 = %x\n", excPtr->GPR15);
+  printk("\t R16 = %x\n", excPtr->GPR16);
+  printk("\t R17 = %x\n", excPtr->GPR17);
+  printk("\t R18 = %x\n", excPtr->GPR18);
+  printk("\t R19 = %x\n", excPtr->GPR19);
+  printk("\t R20 = %x\n", excPtr->GPR20);
+  printk("\t R21 = %x\n", excPtr->GPR21);
+  printk("\t R22 = %x\n", excPtr->GPR22);
+  printk("\t R23 = %x\n", excPtr->GPR23);
+  printk("\t R24 = %x\n", excPtr->GPR24);
+  printk("\t R25 = %x\n", excPtr->GPR25);
+  printk("\t R26 = %x\n", excPtr->GPR26);
+  printk("\t R27 = %x\n", excPtr->GPR27);
+  printk("\t R28 = %x\n", excPtr->GPR28);
+  printk("\t R29 = %x\n", excPtr->GPR29);
+  printk("\t R30 = %x\n", excPtr->GPR30);
+  printk("\t R31 = %x\n", excPtr->GPR31);
+  printk("\t CR = %x\n", excPtr->EXC_CR);
+  printk("\t CTR = %x\n", excPtr->EXC_CTR);
+  printk("\t XER = %x\n", excPtr->EXC_XER);
+  printk("\t LR = %x\n", excPtr->EXC_LR);
+  printk("\t MSR = %x\n", excPtr->EXC_MSR);
+  if ( (excPtr->_EXC_number == ASM_DEC_VECTOR) ||
+       (excPtr->_EXC_number == ASM_SYS_VECTOR)
+     )
+       recoverable = 1;
+  if (!recoverable) BSP_panic("unrecoverable exception!!! Push reset button\n");
+}
+
+void nop_except_enable(const rtems_raw_except_connect_data* ptr)
+{
+}
+int except_always_enabled(const rtems_raw_except_connect_data* ptr)
+{
+  return 1;
+}
+
+void initialize_exceptions()
+{
+  int i;
+  
+  exception_config.exceptSize 		= LAST_VALID_EXC + 1;
+  exception_config.rawExceptHdlTbl 	= &exception_table[0];
+  exception_config.defaultRawEntry.exceptIndex	= 0;
+  exception_config.defaultRawEntry.hdl.vector	= 0;
+  exception_config.defaultRawEntry.hdl.raw_hdl	= default_exception_vector_code_prolog;
+  /*
+   * Note that next line the '&' before default_exception_vector_code_prolog_size
+   * is not a bug as it is defined a .set directly in asm...
+   */
+  exception_config.defaultRawEntry.hdl.raw_hdl_size = (unsigned) &default_exception_vector_code_prolog_size;
+  for (i=0; i <= exception_config.exceptSize; i++) {
+    if (!mpc750_vector_is_valid (i)) {
+      continue;
+    }
+    exception_table[i].exceptIndex	= i;
+    exception_table[i].hdl		= exception_config.defaultRawEntry.hdl;
+    exception_table[i].hdl.vector	= i;
+    exception_table[i].on		= nop_except_enable;
+    exception_table[i].off		= nop_except_enable;
+    exception_table[i].isOn		= except_always_enabled;
+  }
+  if (!mpc60x_init_exceptions(&exception_config)) {
+    BSP_panic("Exception handling initialization failed\n");
+  }
+  else {
+    printk("Exception handling initialization done\n");
+  }
+}