adapted gen83xx to new board

2 files changed, 18 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
index 043f6da661..5948b9ea7a 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
@@ -1,3 +1,9 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* irq/irq.c:
+	make sure, that the masking operations in 
+	ICTL and MSR are executed in order
+
 2008-05-14	Joel Sherrill <joel.sherrill@OARcorp.com>
 
 	* Makefile.am: Rework to avoid .rel files.
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c
index 19fa082d1a..1a82989567 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c
@@ -472,6 +472,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
       ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT));
       ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask;
     }
+    /* 
+     * make sure, that the masking operations in 
+     * ICTL and MSR are executed in order
+     */
+    asm volatile("sync":::"memory");
+
     _CPU_MSR_GET(msr);
     new_msr = msr | MSR_EE;
     _CPU_MSR_SET(new_msr);
@@ -480,6 +486,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
 
     _CPU_MSR_SET(msr);
 
+    /* 
+     * make sure, that the masking operations in 
+     * ICTL and MSR are executed in order
+     */
+    asm volatile("sync":::"memory");
+
     if (cpmIntr)  {
       irq -= BSP_CPM_IRQ_LOWEST_OFFSET;
       ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq);