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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-04-06 15:52:03 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-04-06 15:52:03 +0000 |
| commit | 35bb69b1cd7d5a54f5727195cc7b5f06a7cb2344 (patch) | |
| tree | d7435f5a462d5e266b113b29ee4ad4ed9e21f4af /c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c | |
| parent | 2001-03-26 Zoltan Kocsi <zoltan@bendor.com.au> (diff) | |
| download | rtems-35bb69b1cd7d5a54f5727195cc7b5f06a7cb2344.tar.bz2 | |
2001-03-30 Eric Valette <valette@crf.canon.fr>
* clock/.cvsignore, clock/Makefile.am, clock/p_clock.c,
include/8xx_immap.h, include/commproc.h, include/mbx.h,
irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h,
irq/irq_asm.S, irq/irq_init.c, vectors/.cvsignore,
vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h,
vectors/vectors_init.c: New files.
* Makefile.am, configure.in, console/console.c,
include/Makefile.am, network/network.c, startup/Makefile.am,
startup/bspstart.c, startup/imbx8xx.c, startup/linkcmds,
startup/mmutlbtab.c, startup/start.S, wrapup/Makefile.am:
The modifications to this BSP reflect the conversion of the
mpc8xx CPU to the "new exception processing model."
Diffstat (limited to 'c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c index eca58e56f5..716e86ab61 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @@ -258,7 +258,7 @@ void _InitMBX8xx (void) /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */ m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */ - m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ + m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ /* Initialize the System Clock and Reset Control Register (SCCR) * Set the clock sources and division factors: |