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| author | Thomas Doerfler <thomas.doerfler@embedded-brains.de> | 2012-08-20 10:15:20 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-08-20 10:16:32 +0200 |
| commit | d9af2ed4dd235b15b953f4743d8adbf971208851 (patch) | |
| tree | ceeed058df8ac40c19118483451173b3fb5f4f72 /c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h | |
| parent | libcsupport: Add and use rtems_putc() (diff) | |
| download | rtems-d9af2ed4dd235b15b953f4743d8adbf971208851.tar.bz2 | |
bsp/gen83xx: Add br_uid BSP variant
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h index c97059b2c4..c7c3d2ac14 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @@ -106,6 +106,46 @@ RCWHR_LALE_EARLY | \ RCWHR_LDP_SPC) +#elif defined(MPC83XX_BOARD_BR_UID) +/* + * for BR UID + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 25000000L +#define RCFG_SYSPLL_MF 5 +#define RCFG_COREPLL_MF 5 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L \ + (RCWLR_LBIUCM_1_1 \ + | RCWLR_DDRCM_2_1 \ + | RCWLR_SPMF(RCFG_SYSPLL_MF) \ + | RCWLR_COREPLL(RCFG_COREPLL_MF) \ + | RCWLR_CEVCOD_1_2 \ + | RCWLR_CEPMF(8) \ + ) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_DIS | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + RCWHR_ROMLOC_LB16 | \ + RCWHR_RLEXT_LGCY | \ + RCWHR_ENDIAN_BIG) + #elif defined( HAS_UBOOT) /* TODO */ @@ -258,6 +298,55 @@ #define DDR_SDRAM_INIT_ADDR_VAL 0 #define DDR_SDRAM_INTERVAL_VAL 0x05080000 +#elif defined(MPC83XX_BOARD_BR_UID) +/************************** + * for BR UID + */ + +/* + * working values for various registers, used in start/start.S + */ + +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL bsp_rom_start +#define LBLAWAR0_VAL 0x80000018 +#define DDRLAWBAR0_VAL bsp_ram_start +#define DDRLAWAR0_VAL 0x8000001B + + +/* + * clocking for local bus: + * ALE active for 1 clock + * local bus clock = 1/2 csb clock + */ +#define LCRR_VAL 0x80010002 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80014202 +#define TIMING_CFG_0_VAL 0x00220802 +#define TIMING_CFG_1_VAL 0x26259222 +#define TIMING_CFG_2_VAL 0x111048C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x200F1632 +#define DDR_SDRAM_MODE_2_VAL 0x40006000 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x43100008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x01E8222E + #elif defined( HAS_UBOOT) /* TODO */ |