diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-04-19 11:53:07 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-04-23 09:59:57 +0200 |
commit | 92d80383ff5b83258a111f90e17fb1c6825297b8 (patch) | |
tree | 0cd791cef811c6862e4dfab41c037224d8762481 /c/src/lib/libbsp/powerpc/gen5200 | |
parent | bsp/mpc5200: Change SDRAM initialization (diff) | |
download | rtems-92d80383ff5b83258a111f90e17fb1c6825297b8.tar.bz2 |
bsp/mpc5200: New BSP variant BRS6L
Diffstat (limited to 'c/src/lib/libbsp/powerpc/gen5200')
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/Makefile.am | 1 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/configure.ac | 14 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/include/bsp.h | 12 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/make/custom/brs6l.cfg | 10 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/start/start.S | 27 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c | 54 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs6l | 15 |
7 files changed, 114 insertions, 19 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen5200/Makefile.am b/c/src/lib/libbsp/powerpc/gen5200/Makefile.am index 68bddd74a1..6bef55db6c 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/Makefile.am +++ b/c/src/lib/libbsp/powerpc/gen5200/Makefile.am @@ -33,6 +33,7 @@ project_lib_DATA += rtems_crti.$(OBJEXT) dist_project_lib_DATA += startup/linkcmds.base project_lib_DATA += startup/linkcmds EXTRA_DIST = startup/linkcmds.brs5l +EXTRA_DIST += startup/linkcmds.brs6l EXTRA_DIST += startup/linkcmds.icecube EXTRA_DIST += startup/linkcmds.pm520_cr825 EXTRA_DIST += startup/linkcmds.pm520_ze30 diff --git a/c/src/lib/libbsp/powerpc/gen5200/configure.ac b/c/src/lib/libbsp/powerpc/gen5200/configure.ac index 373411d9e9..6fd8126edc 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/configure.ac +++ b/c/src/lib/libbsp/powerpc/gen5200/configure.ac @@ -36,7 +36,7 @@ RTEMS_BSPOPTS_HELP([BSP_PRESS_KEY_FOR_RESET], RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[icecube],[1]) RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_*],[1]) -RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs5l],[1]) +RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs*l],[1]) RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[*],[0]) RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT], [If set to !0, reset the board when the application exits.]) @@ -44,8 +44,8 @@ RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT], RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_ze30],[0x037F3F07]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552104]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs5l],[0xb30F0F77]) -RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs5l],[0x91050444]) +RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs*l],[0xb30F0F77]) +RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs*l],[0x91050444]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[dp2],[0x337F3F77]) RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[dp2],[0x03550040]) @@ -68,8 +68,8 @@ set via BSP_GPIOPCR_INITVAL.]) RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_ze30],[0x39]) ## on cr825, we have PSC1/2/3 RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_cr825],[0x07]) -## on brs5l, we have PSC1/2/3 -RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs5l],[0x07]) +## on brs5l and brs6l, we have PSC1/2/3 +RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs*l],[0x07]) ## on icecube, we only have PSC1 RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[icecube],[0x01]) ## dp2: PSC2 (via USB connector), PSC6 (GPS module) @@ -109,6 +109,10 @@ RTEMS_BSPOPTS_SET([MPC5200_BOARD_BRS5L],[brs5l],[1]) RTEMS_BSPOPTS_HELP([MPC5200_BOARD_BRS5L], [enable settings for BRS5L]) +RTEMS_BSPOPTS_SET([MPC5200_BOARD_BRS6L],[brs6l],[1]) +RTEMS_BSPOPTS_HELP([MPC5200_BOARD_BRS6L], +[enable settings for BRS6L]) + RTEMS_BSPOPTS_SET([MPC5200_BOARD_DP2],[dp2],[1]) RTEMS_BSPOPTS_HELP([MPC5200_BOARD_DP2], [enable settings for DP2]) diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h index 0a1f859dba..b8c46dc268 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h @@ -109,6 +109,16 @@ LINKER_SYMBOL(MBAR); #define HAS_NVRAM_93CXX +#elif defined(MPC5200_BOARD_BRS6L) + #define MPC5200_BRS6L_FPGA_BEGIN 0x800000 + #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024) + #define MPC5200_BRS6L_FPGA_END \ + (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE) + + #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000 + #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024) + #define MPC5200_BRS6L_MRAM_END \ + (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE) #elif defined (PM520) /* Nothing special */ @@ -193,7 +203,7 @@ extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig #define IPB_CLOCK (bsp_uboot_board_info.bi_ipbfreq) #define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq) #define G2_CLOCK (bsp_uboot_board_info.bi_intfreq) -#elif defined(MPC5200_BOARD_BRS5L) +#elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L) #define IPB_CLOCK 66000000 /* 66 MHz */ #define XLB_CLOCK 132000000 /* 132 MHz */ #define G2_CLOCK 396000000 /* 396 MHz */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/make/custom/brs6l.cfg b/c/src/lib/libbsp/powerpc/gen5200/make/custom/brs6l.cfg new file mode 100644 index 0000000000..d6e556a183 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen5200/make/custom/brs6l.cfg @@ -0,0 +1,10 @@ +# +# Config file for customer specific MPC5200 board +# + +# +# All GEN5200 configurations share the same base file, only a few +# parameters differ. +# + +include $(RTEMS_ROOT)/make/custom/gen5200.inc diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S index 9f5379d5d6..751e7ff73e 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S +++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S @@ -300,6 +300,8 @@ start: #if defined(MPC5200_BOARD_BRS5L) #define CSBOOTROM_VAL 0x0101D910 +#elif defined(MPC5200_BOARD_BRS6L) + #define CSBOOTROM_VAL 0x0202D910 #endif #ifdef CSBOOTROM_VAL @@ -528,29 +530,54 @@ SDRAM_init: #define SDELAY_VAL 0x00000004 +#if defined(MPC5200_BOARD_BRS6L) + #define CFG1_VAL 0x73722930 +#else /* * Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 * Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ #define CFG1_VAL 0xC4222600 +#endif +#if defined(MPC5200_BOARD_BRS6L) + #define CFG2_VAL 0x47770000 +#else /* Refr.2No-Read delay=0x06, Write latency=0x0 */ /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */ #define CFG2_VAL 0xCCC70004 +#endif #if defined(MPC5200_BOARD_BRS5L) /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ /* Refresh counter=0xFFFF */ #define CTRL_VAL 0xD1470000 +#elif defined(MPC5200_BOARD_BRS6L) + #define CTRL_VAL 0xF15F0F00 #else /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ /* Refresh counter=0xFFFF */ #define CTRL_VAL 0xD04F0000 #endif +#if defined(MPC5200_BOARD_BRS6L) + /* Enable DLL, normal drive strength */ + #define EMODE_VAL 0x40010000 +#endif + +#if defined(MPC5200_BOARD_BRS6L) + /* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation/reset DLL */ + #define MODE_VAL 0x058D0000 +#else /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */ #define MODE_VAL 0x008D0000 +#endif + +#if defined(MPC5200_BOARD_BRS6L) + /* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation */ + #define SECOND_MODE_VAL (MODE_VAL & ~0x04000000) +#endif /* SDRAM initialization according to application note AN3221 */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c index 6a1a810681..1379667cd3 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c @@ -121,7 +121,7 @@ static void cpu_init_bsp(void) { BAT dbat; -#if defined(MPC5200_BOARD_BRS5L) +#if defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L) calc_dbat_regvals( &dbat, (uint32_t) bsp_ram_start, @@ -157,18 +157,6 @@ static void cpu_init_bsp(void) BPP_RW ); SET_DBAT(2,dbat.batu,dbat.batl); - - calc_dbat_regvals( - &dbat, - (uint32_t) bsp_dpram_start, - 128 * 1024, - false, - true, - false, - true, - BPP_RW - ); - SET_DBAT(3,dbat.batu,dbat.batl); #elif defined (HAS_UBOOT) uint32_t start = 0; @@ -285,6 +273,46 @@ static void cpu_init_bsp(void) BPP_RW ); SET_DBAT(4, dbat.batu, dbat.batl); +#elif defined(MPC5200_BOARD_BRS5L) + calc_dbat_regvals( + &dbat, + (uint32_t) bsp_dpram_start, + 128 * 1024, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT(3,dbat.batu,dbat.batl); +#elif defined(MPC5200_BOARD_BRS6L) + enable_bat_4_to_7(); + + /* FPGA */ + calc_dbat_regvals( + &dbat, + MPC5200_BRS6L_FPGA_BEGIN, + MPC5200_BRS6L_FPGA_SIZE, + false, + true, + false, + true, + BPP_RW + ); + SET_DBAT(3,dbat.batu,dbat.batl); + + /* MRAM */ + calc_dbat_regvals( + &dbat, + MPC5200_BRS6L_MRAM_BEGIN, + MPC5200_BRS6L_MRAM_SIZE, + true, + false, + false, + false, + BPP_RW + ); + SET_DBAT(4,dbat.batu,dbat.batl); #endif } diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs6l b/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs6l new file mode 100644 index 0000000000..3563f49f11 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/linkcmds.brs6l @@ -0,0 +1,15 @@ +/** + * @file + * + * Linker command file for the BRS6L board. + */ + +MEMORY { + /* For the 4k adjustment see cpuinit.c */ + RAM : ORIGIN = 0x0, LENGTH = 128M - 4k + ROM : ORIGIN = 0xff800000, LENGTH = 8M + DPRAM : ORIGIN = 0xff000000, LENGTH = 0 + REGS : ORIGIN = 0xf0000000, LENGTH = 64k +} + +INCLUDE linkcmds.base |