diff options
| author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-29 15:27:07 +0000 |
|---|---|---|
| committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-29 15:27:07 +0000 |
| commit | efdfd48add0e7f5549ce99a3cabf6aed9f170230 (patch) | |
| tree | 396c3c8ae3a969c7fe1b1d3f334e4b2bc442ff37 /c/src/lib/libbsp/powerpc/gen5200 | |
| parent | Whitespace removal. (diff) | |
| download | rtems-efdfd48add0e7f5549ce99a3cabf6aed9f170230.tar.bz2 | |
Whitespace removal.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/gen5200')
29 files changed, 550 insertions, 550 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c index 63916e3d09..42488cb87b 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -52,7 +52,7 @@ static const char* const TaskVersionString = "BestComm API v2.2 20041209"; /* * Hidden API data per task. */ - + static BDIdx BDHead[MAX_TASKS]; static BDIdx BDTail[MAX_TASKS]; @@ -103,7 +103,7 @@ const char *TaskVersion(void) * \returns TASK_ERR_NO_ERR on successful initialization. * or TASK_ERR_API_ALREADY_INITIALIZED. * - * This function is only used with physical addresses. + * This function is only used with physical addresses. * * This function will also initialize API internal variables. The return * value TASK_ERR_API_ALREADY_INITIALIZED is intended to help determine if @@ -116,12 +116,12 @@ int TasksInitAPI(uint8 *MBarRef) * for use by other functions. */ MBarGlobal = MBarRef; - + /* * The offset is 0 if physical and virtual are the same. */ MBarPhysOffsetGlobal = 0; - + /* * IF API has not been initialized yet then... * Make sure all BestComm interrupts are disabled and not pending. @@ -131,7 +131,7 @@ int TasksInitAPI(uint8 *MBarRef) */ return TASK_ERR_NO_ERR; } - + /*! * \brief Initialize the API when virtual memory is used. * \param MBarRef Reference pointer to the device register memory @@ -158,8 +158,8 @@ int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys) * for use by other functions. */ MBarGlobal = MBarRef; - MBarPhysOffsetGlobal = MBarPhys - MBarRef; - + MBarPhysOffsetGlobal = MBarPhys - MBarRef; + /* * If API has not been initialized yet then... * Make sure all BestComm interrupts are disabled and not pending. @@ -169,7 +169,7 @@ int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys) */ return TASK_ERR_NO_ERR; } - + /*! * \brief \em Deprecated * \param sdma Base address of the BestComm register set diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h index 5e06adf21c..f4dfa68fde 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -247,7 +247,7 @@ typedef struct { #include "bestcomm_priv.h" #include "dma_image.capi.h" - + /*! * \brief Initialize a single task. * \param TaskName Type of task to initialize. E.g. PCI transmit, diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h index fa81909f38..1a3d932b5f 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.c index e5df5f841e..60a0f55ac9 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.capi.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.capi.h index d1242fe0b6..6b07cbcb2a 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.capi.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.capi.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.h index 6c5a7ca239..1f8b86cded 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -46,7 +46,7 @@ void init_dma_image_TASK_GEN_DP_BD_0(uint8 *vMem_taskBar, sint64 vMemOffset); void init_dma_image_TASK_GEN_DP_BD_1(uint8 *vMem_taskBar, sint64 vMemOffset); /* MBAR_TASK_TABLE is the first address of task table */ -#ifndef MBAR_TASK_TABLE +#ifndef MBAR_TASK_TABLE #define MBAR_TASK_TABLE 0xf0008000UL #endif diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.reloc.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.reloc.c index c820bbd9ce..8e4aa8c470 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.reloc.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.reloc.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -40,145 +40,145 @@ uint32 taskTable[] = { 0x00000238, 0x00000700, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001000, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task1(TASK_PCI_RX): Start of Entry -> 0xf0008020 */ 0x0000023c, /* Task 0 Descriptor Table */ 0x00000268, 0x00000780, /* Task 0 Variable Table */ 0x00000027, /* No FDT */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001050, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task2(TASK_FEC_TX): Start of Entry -> 0xf0008040 */ 0x0000026c, /* Task 0 Descriptor Table */ 0x000002f8, 0x00000800, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x000010a0, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task3(TASK_FEC_RX): Start of Entry -> 0xf0008060 */ 0x000002fc, /* Task 0 Descriptor Table */ 0x00000358, 0x00000880, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x000010f0, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task4(TASK_LPC): Start of Entry -> 0xf0008080 */ 0x0000035c, /* Task 0 Descriptor Table */ 0x0000038c, 0x00000900, /* Task 0 Variable Table */ 0x00000027, /* No FDT */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001140, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task5(TASK_ATA): Start of Entry -> 0xf00080a0 */ 0x00000390, /* Task 0 Descriptor Table */ 0x000003c4, 0x00000980, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001190, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task6(TASK_CRC16_DP_0): Start of Entry -> 0xf00080c0 */ 0x000003c8, /* Task 0 Descriptor Table */ 0x0000040c, 0x00000a00, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x000011e0, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task7(TASK_CRC16_DP_1): Start of Entry -> 0xf00080e0 */ 0x00000410, /* Task 0 Descriptor Table */ 0x00000454, 0x00000a80, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001230, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task8(TASK_GEN_DP_0): Start of Entry -> 0xf0008100 */ 0x00000458, /* Task 0 Descriptor Table */ 0x00000488, 0x00000b00, /* Task 0 Variable Table */ 0x00000027, /* No FDT */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001280, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task9(TASK_GEN_DP_1): Start of Entry -> 0xf0008120 */ 0x0000048c, /* Task 0 Descriptor Table */ 0x000004bc, 0x00000b80, /* Task 0 Variable Table */ 0x00000027, /* No FDT */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x000012d0, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task10(TASK_GEN_DP_2): Start of Entry -> 0xf0008140 */ 0x000004c0, /* Task 0 Descriptor Table */ 0x000004f0, 0x00000c00, /* Task 0 Variable Table */ 0x00000027, /* No FDT */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001320, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task11(TASK_GEN_DP_3): Start of Entry -> 0xf0008160 */ 0x000004f4, /* Task 0 Descriptor Table */ 0x00000524, 0x00000c80, /* Task 0 Variable Table */ 0x00000027, /* No FDT */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001370, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task12(TASK_GEN_TX_BD): Start of Entry -> 0xf0008180 */ 0x00000528, /* Task 0 Descriptor Table */ 0x00000560, 0x00000d00, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x000013c0, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task13(TASK_GEN_RX_BD): Start of Entry -> 0xf00081a0 */ 0x00000564, /* Task 0 Descriptor Table */ 0x00000594, 0x00000d80, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001410, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task14(TASK_GEN_DP_BD_0): Start of Entry -> 0xf00081c0 */ 0x00000598, /* Task 0 Descriptor Table */ 0x000005cc, 0x00000e00, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x00001460, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task15(TASK_GEN_DP_BD_1): Start of Entry -> 0xf00081e0 */ 0x000005d0, /* Task 0 Descriptor Table */ 0x00000604, 0x00000e80, /* Task 0 Variable Table */ 0x00000f27, /* Task 0 Function Descriptor Table & Flags */ -0x00000000, -0x00000000, +0x00000000, +0x00000000, 0x000014b0, /* Task 0 context save space */ -0x00000000, +0x00000000, /* Task0(TASK_PCI_TX): Start of TDT -> 0xf0008200 */ 0xc080601b, /* 0000(../LIB_incl/hdplx.sc:167): LCDEXT: idx0 = var1, idx1 = var0; ; idx0 += inc3, idx1 += inc3 */ @@ -1047,54 +1047,54 @@ uint32 taskTable[] = { 0x00000000, /* inc[7] */ /* Task0(TASK_PCI_TX): Start of FDT -> 0xf0008f00 */ -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, 0xa0045670, /* load_acc(), EU# 3 */ 0x80045670, /* unload_acc(), EU# 3 */ 0x21800000, /* and(), EU# 3 */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/mgt5200.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/mgt5200.h index ef045b887b..9e4b94cd10 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/mgt5200.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/mgt5200.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -24,7 +24,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * ******************************************************************************/ - + #define MBAR_CS 0x0000 #define MBAR_SDRAM 0x0100 #define MBAR_CDM 0x0200 diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/sdma.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/sdma.h index 1aa0b99d9b..52d84777ad 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/sdma.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/sdma.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -34,10 +34,10 @@ typedef struct sdma_register_set { volatile uint8 IntVect1; /* MBAR_SDMA + 0x10 sdPtd */ volatile uint8 IntVect2; /* MBAR_SDMA + 0x11 sdPtd */ volatile uint16 PtdCntrl; /* MBAR_SDMA + 0x12 sdPtd */ - + volatile uint32 IntPend; /* MBAR_SDMA + 0x14 sdPtd */ volatile uint32 IntMask; /* MBAR_SDMA + 0x18 sdPtd */ - + volatile uint32 TCR01; /* MBAR_SDMA + 0x1c sdPtd */ volatile uint32 TCR23; /* MBAR_SDMA + 0x20 sdPtd */ volatile uint32 TCR45; /* MBAR_SDMA + 0x24 sdPtd */ @@ -46,7 +46,7 @@ typedef struct sdma_register_set { volatile uint32 TCRAB; /* MBAR_SDMA + 0x30 sdPtd */ volatile uint32 TCRCD; /* MBAR_SDMA + 0x34 sdPtd */ volatile uint32 TCREF; /* MBAR_SDMA + 0x38 sdPtd */ - + volatile uint8 IPR0; /* MBAR_SDMA + 0x3c sdPtd */ volatile uint8 IPR1; /* MBAR_SDMA + 0x3d sdPtd */ volatile uint8 IPR2; /* MBAR_SDMA + 0x3e sdPtd */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/ppctypes.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/ppctypes.h index 77f6a70134..ff2aed1997 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/ppctypes.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/ppctypes.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c index 91bb319b67..2c4c96d84c 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -81,6 +81,6 @@ void TasksLoadImage(sdma_regs *sdma) tt->fdt = (sdma->taskBar & 0xFFFFFF00) + tt->fdt; tt->context += sdma->taskBar; } - + SramOffsetGlobal = taskTableBytes; } diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_api_mem.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_api_mem.h index 1cb4345ff2..dc529d6a22 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_api_mem.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_api_mem.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -28,7 +28,7 @@ #include "../include/mgt5200/mgt5200.h" /* - * An extern global variable is used here for the MBAR since it must + * An extern global variable is used here for the MBAR since it must * be passed into the API for processes that use virtual memory. */ extern uint8 *MBarGlobal; diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h index ce596627b4..f4273cdb82 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -26,7 +26,7 @@ ******************************************************************************/ /******************************************************************************* - * Defines to control SmartDMA and its tasks. These defines are used for the + * Defines to control SmartDMA and its tasks. These defines are used for the * task build process to minimize disconnects at the task/driver interface. ******************************************************************************/ @@ -49,7 +49,7 @@ #define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */ #define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */ #define SDMA_BD_BIT_READY 30 /* Status BD ready bit */ -#ifdef SAS_COMPILE +#ifdef SAS_COMPILE #define SDMA_BD_MASK_READY constant(1<<SDMA_BD_BIT_READY) #else #define SDMA_BD_MASK_READY (1<<SDMA_BD_BIT_READY) diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_bdtable.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_bdtable.h index 0ab2baf7cf..7f261d21ee 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_bdtable.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_bdtable.h @@ -4,17 +4,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -65,7 +65,7 @@ typedef struct { * cannot use this to track a task's BD pointer. */ uint16 currBDInUse; /* Current number of buffer descriptors assigned but*/ - /* not released yet. */ + /* not released yet. */ } TaskBDIdxTable_t; typedef enum { @@ -77,7 +77,7 @@ typedef enum { * Allocates BD table if needed and updates the BD index table. * Do we want to hide this from the C API since it operates on task API? */ -void TaskSetup_BDTable(volatile uint32 *BasePtr, +void TaskSetup_BDTable(volatile uint32 *BasePtr, volatile uint32 *LastPtr, volatile uint32 *StartPtr, int TaskNum, uint32 NumBD, uint16 MaxBD, diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_general.h b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_general.h index c163f0a3fd..9db076cfa3 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_general.h +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_general.h @@ -1,17 +1,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -373,7 +373,7 @@ TaskId TASKSETUP_NAME(TASK_API *TaskAPI, *(TaskAPI->DRD[i]) = (*(TaskAPI->DRD[i]) & DRD_INIT_MASK) | (TaskSetupParams->Initiator << DRD_INIT_OFFSET); } - + if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) != 0) { ext = 1; diff --git a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c index 58f5e683ca..a51c63e625 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c +++ b/c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Copyright (c) 2004 Freescale Semiconductor, Inc. -* +* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: -* +* * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. -* +* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/c/src/lib/libbsp/powerpc/gen5200/clock/clock.c b/c/src/lib/libbsp/powerpc/gen5200/clock/clock.c index b77f364f59..53596d3df3 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/clock/clock.c +++ b/c/src/lib/libbsp/powerpc/gen5200/clock/clock.c @@ -147,7 +147,7 @@ void mpc5200_init_gpt(uint32_t gpt_no) struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]); gpt->status = GPT_STATUS_RESET; - gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN | + gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN | GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO; } diff --git a/c/src/lib/libbsp/powerpc/gen5200/i2c/i2c.c b/c/src/lib/libbsp/powerpc/gen5200/i2c/i2c.c index a971e904f5..0723511746 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/i2c/i2c.c +++ b/c/src/lib/libbsp/powerpc/gen5200/i2c/i2c.c @@ -72,7 +72,7 @@ i2c_transfer_wait_sema(i2c_bus_number bus, i2c_message *msg, int nmsg) ); if (sc != RTEMS_SUCCESSFUL) return I2C_RESOURCE_NOT_AVAILABLE; - sc = i2c_transfer(bus, nmsg, msg, + sc = i2c_transfer(bus, nmsg, msg, i2c_transfer_sema_done_func, &sema); if (sc != RTEMS_SUCCESSFUL) { @@ -107,7 +107,7 @@ i2c_transfer_wait_poll(i2c_bus_number bus, i2c_message *msg, int nmsg) volatile bool poll_done_flag; rtems_status_code sc; poll_done_flag = false; - sc = i2c_transfer(bus, nmsg, msg, + sc = i2c_transfer(bus, nmsg, msg, i2c_transfer_poll_done_func,(void *)&poll_done_flag); if (sc != RTEMS_SUCCESSFUL) return sc; diff --git a/c/src/lib/libbsp/powerpc/gen5200/i2c/i2cdrv.c b/c/src/lib/libbsp/powerpc/gen5200/i2c/i2cdrv.c index 9295aded99..bbc29597df 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/i2c/i2cdrv.c +++ b/c/src/lib/libbsp/powerpc/gen5200/i2c/i2cdrv.c @@ -140,7 +140,7 @@ i2cdrv_unload(void) i2cdrv_bus_clock_div_current = i2cdrv_bus_clock_div[qel->bus]; mpc5200mbus_select_clock_divider(&mbus[qel->bus], i2cdrv_bus_clock_div_current); } - sc = mpc5200mbus_i2c_transfer(&mbus[qel->bus], qel->nmsg, qel->msg, + sc = mpc5200mbus_i2c_transfer(&mbus[qel->bus], qel->nmsg, qel->msg, i2cdrv_done,qel); if (sc != RTEMS_SUCCESSFUL) { diff --git a/c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c b/c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c index 23c1345211..0c7dbc5330 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c +++ b/c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c @@ -195,7 +195,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) uint8_t b; switch (bus->state) { - + case STATE_UNINITIALIZED: /* this should never happen. */ mpc5200mbus_machine_error(bus, event); @@ -206,7 +206,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) case EVENT_NEXTMSG: /* Start new message processing */ bus->cmsg++; /* FALLTHRU */ - + case EVENT_TRANSFER: /* Initiate new transfer */ if (bus->cmsg - bus->msg >= bus->nmsg) { @@ -217,7 +217,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) bus->done(bus->done_arg_ptr); break; } - + /* Initiate START or REPEATED START condition on the bus */ if (event == EVENT_TRANSFER) { @@ -227,10 +227,10 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) { mpc5200mbus_rstart(bus); } - + bus->byte = 0; mpc5200mbus_tx_mode(bus); - + /* Initiate slave address sending */ if (bus->cmsg->flags & I2C_MSG_ADDR_10) { @@ -264,13 +264,13 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) mpc5200mbus_send(bus, b); } break; - + default: mpc5200mbus_machine_error(bus, event); break; } break; - + case STATE_ADDR_7: switch (event) { @@ -282,7 +282,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) mpc5200mbus_send_ack(bus); next_state(bus, STATE_RECEIVING); break; - + case EVENT_NACK: mpc5200mbus_error(bus, I2C_NO_DEVICE); next_state(bus, STATE_IDLE); @@ -294,14 +294,14 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) next_state(bus, STATE_IDLE); mpc5200mbus_machine(bus, EVENT_NEXTMSG); break; - + default: mpc5200mbus_machine_error(bus, event); break; } break; - case STATE_ADDR_1_R: + case STATE_ADDR_1_R: case STATE_ADDR_1_W: switch (event) { @@ -325,25 +325,25 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) } break; } - + case EVENT_NACK: mpc5200mbus_error(bus, I2C_NO_DEVICE); next_state(bus, STATE_IDLE); mpc5200mbus_machine(bus, EVENT_NEXTMSG); break; - + case EVENT_ARB_LOST: mpc5200mbus_error(bus, I2C_ARBITRATION_LOST); next_state(bus, STATE_IDLE); mpc5200mbus_machine(bus, EVENT_NEXTMSG); break; - + default: mpc5200mbus_machine_error(bus, event); break; } break; - + case STATE_SENDING: switch (event) { @@ -359,7 +359,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) next_state(bus, STATE_SENDING); } break; - + case EVENT_NACK: if (bus->byte == 0) { @@ -372,20 +372,20 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event) next_state(bus, STATE_IDLE); mpc5200mbus_machine(bus, EVENT_NEXTMSG); break; - + case EVENT_ARB_LOST: mpc5200mbus_error(bus, I2C_ARBITRATION_LOST); next_state(bus, STATE_IDLE); mpc5200mbus_machine(bus, EVENT_NEXTMSG); break; - + default: mpc5200mbus_machine_error(bus, event); break; - + } break; - + case STATE_RECEIVING: switch (event) { @@ -444,7 +444,7 @@ void mpc5200mbus_interrupt_handler(rtems_irq_hdl_param handle) { i2c_event event; mpc5200mbus *bus = handle; - + event = mpc5200mbus_get_event(bus); /* * clear interrupt bit @@ -454,34 +454,34 @@ void mpc5200mbus_interrupt_handler(rtems_irq_hdl_param handle) mpc5200mbus_machine(bus, event); } -/* +/* * mpc5200_mbus_irq_enable * enable irq for mbus */ void mpc5200mbus_irq_enable(const rtems_irq_connect_data* ptr) -{ +{ int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx; mpc5200.i2c_regs[minor].mcr |= MPC5200_I2C_MCR_MIEN; } -/* +/* * mpc5200_mbus_irq_disable * enable irq for mbus */ void mpc5200mbus_irq_disable(const rtems_irq_connect_data* ptr) -{ +{ int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx; mpc5200.i2c_regs[minor].mcr &= ~MPC5200_I2C_MCR_MIEN; } -/* +/* * mpc5200_mbus_isOn - * check, whether irq is enabled + * check, whether irq is enabled */ int mpc5200mbus_irq_isOn(const rtems_irq_connect_data* ptr) -{ +{ int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx; return (0 != (mpc5200.i2c_regs[minor].mcr & MPC5200_I2C_MCR_MIEN)); @@ -527,7 +527,7 @@ mpc5200mbus_select_clock_divider(mpc5200mbus *bus, int divider) int divider; int mbc; } dividers[] ={ - { 20, 0x20 }, { 22, 0x21 }, { 24, 0x22 }, { 26, 0x23 }, + { 20, 0x20 }, { 22, 0x21 }, { 24, 0x22 }, { 26, 0x23 }, { 28, 0x00 }, { 30, 0x01 }, { 32, 0x25 }, { 34, 0x02 }, { 36, 0x26 }, { 40, 0x03 }, { 44, 0x04 }, { 48, 0x05 }, { 56, 0x06 }, { 64, 0x2a }, { 68, 0x07 }, { 72, 0x2B }, @@ -544,7 +544,7 @@ mpc5200mbus_select_clock_divider(mpc5200mbus *bus, int divider) if (bus == NULL) return RTEMS_INVALID_ADDRESS; - + for (i = 0, mbc = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) { mbc = dividers[i].mbc; @@ -578,13 +578,13 @@ mpc5200mbus_initialize(mpc5200mbus *i2c_bus) if (i2c_bus->state != STATE_UNINITIALIZED) /* Check if already initialized */ return RTEMS_RESOURCE_IN_USE; - + i2c_bus->state = STATE_IDLE; i2c_bus->msg = NULL; i2c_bus->cmsg = NULL; i2c_bus->nmsg = 0; i2c_bus->byte = 0; - + /* * install interrupt handler */ @@ -614,7 +614,7 @@ mpc5200mbus_initialize(mpc5200mbus *i2c_bus) mpc5200.i2c_regs[i2c_bus->bus_idx].mcr |= MPC5200_I2C_MCR_MEN; rtems_interrupt_enable(level); - + return RTEMS_SUCCESSFUL; } @@ -639,7 +639,7 @@ mpc5200mbus_i2c_transfer(mpc5200mbus *bus, int nmsg, i2c_message *msg, { if (bus->state == STATE_UNINITIALIZED) return RTEMS_NOT_CONFIGURED; - + bus->done = done; bus->done_arg_ptr = done_arg_ptr; bus->cmsg = bus->msg = msg; @@ -668,7 +668,7 @@ mpc5200mbus_i2c_done(mpc5200mbus *i2c_bus) if (i2c_bus->state == STATE_UNINITIALIZED) return RTEMS_NOT_CONFIGURED; - + mpc5200.i2c_regs[i2c_bus->bus_idx].mcr = 0; return sc; diff --git a/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c b/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c index dc025cc7ff..bf4d71f81d 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c +++ b/c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c @@ -243,7 +243,7 @@ static void pcmcia_ide_recv_dmairq_hdl(rtems_irq_hdl_param unused) bestcomm_glue_irq_disable(TASK_GEN_DP_BD_0); pcmcia_ide_rxInterrupts++; /* Rx int has occurred */ - + if (pcmcia_ide_hdl_task != 0) { rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT); } @@ -258,7 +258,7 @@ static void pcmcia_ide_xmit_dmairq_hdl(rtems_irq_hdl_param unused) bestcomm_glue_irq_disable(TASK_GEN_DP_BD_1); pcmcia_ide_txInterrupts++; /* Tx int has occurred */ - + if (pcmcia_ide_hdl_task != 0) { rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT); } @@ -279,7 +279,7 @@ void mpc5200_pcmciaide_dma_init(int minor) rxParam.NumBD = PCMCIA_IDE_DMA_RD_BD_CNT; rxParam.Size.MaxBuf = PCMCIA_IDE_RD_SECTOR_SIZE; rxParam.Initiator = INITIATOR_ALWAYS; - rxParam.StartAddrSrc = + rxParam.StartAddrSrc = (uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD]; rxParam.IncrSrc = 0; rxParam.SzSrc = sizeof(uint16_t); @@ -302,7 +302,7 @@ void mpc5200_pcmciaide_dma_init(int minor) (uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD]; txParam.IncrDst = 0; txParam.SzDst = sizeof(uint16_t); - + pcmcia_ide_txTaskId = TaskSetup( TASK_GEN_DP_BD_1, &txParam ); /* * FIXME: Init BD rings @@ -313,21 +313,21 @@ void mpc5200_pcmciaide_dma_init(int minor) */ /* * connect interrupt handlers - */ + */ bestcomm_glue_irq_install(TASK_GEN_DP_BD_1,pcmcia_ide_xmit_dmairq_hdl,NULL); bestcomm_glue_irq_install(TASK_GEN_DP_BD_0,pcmcia_ide_recv_dmairq_hdl,NULL); } void mpc5200_pcmciaide_dma_blockop(bool is_write, - int minor, - uint16_t block_size, + int minor, + uint16_t block_size, rtems_blkdev_sg_buffer *bufs, - uint32_t *cbuf, + uint32_t *cbuf, uint32_t *pos) { /* - * Nameing: + * Nameing: * - a block is one unit of data on disk (multiple sectors) * - a buffer is a contignuous chunk of data in memory * a block on disk may be filled with data from several buffers @@ -360,16 +360,16 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, */ while ((rc == RTEMS_SUCCESSFUL) && (bufs_from_dma < bufs_total)) { - - while ((rc == RTEMS_SUCCESSFUL) && - (bufs_to_dma < bufs_total) && + + while ((rc == RTEMS_SUCCESSFUL) && + (bufs_to_dma < bufs_total) && (bds_free > 0)) { /* * fill in BD, set interrupt if needed */ SDMA_CLEAR_IEVENT(&mpc5200.IntPend,(is_write ? TASK_GEN_DP_BD_1 - : TASK_GEN_DP_BD_0)); + : TASK_GEN_DP_BD_0)); if (is_write) { TaskBDAssign(pcmcia_ide_txTaskId , (void *)bufs[bufs_to_dma].buffer, @@ -394,7 +394,7 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, bds_free --; } if (is_write) { - TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE, + TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE, pcmcia_ide_txTaskId, TASK_INTERRUPT_DISABLE ); } else { @@ -407,12 +407,12 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, * enable interrupts, wait for interrupt event */ rtems_task_ident(RTEMS_SELF,0,(rtems_id *)&pcmcia_ide_hdl_task); - bestcomm_glue_irq_enable((is_write - ? TASK_GEN_DP_BD_1 + bestcomm_glue_irq_enable((is_write + ? TASK_GEN_DP_BD_1 : TASK_GEN_DP_BD_0)); - rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT, - RTEMS_WAIT | RTEMS_EVENT_ANY, + rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT, + RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); pcmcia_ide_hdl_task = 0; @@ -429,13 +429,13 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write, } do { - nxt_bd_idx = TaskBDRelease(is_write - ? pcmcia_ide_txTaskId + nxt_bd_idx = TaskBDRelease(is_write + ? pcmcia_ide_txTaskId : pcmcia_ide_rxTaskId); if ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) && (nxt_bd_idx != TASK_ERR_BD_BUSY)) { - (*cbuf)++; - (*pos) += bufs[bufs_from_dma].length; + (*cbuf)++; + (*pos) += bufs[bufs_from_dma].length; bufs_from_dma++; } } while ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) && @@ -455,7 +455,7 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s uint16_t *lbuf = (uint16_t*)((uint8_t*)(bufs[(*cbuf)].buffer)+(*pos)); uint32_t llength = bufs[(*cbuf)].length; bool use_dma; - + #if IDE_USE_STATISTICS mpc5200_pcmciaide_read_block_call_cnt++; #endif @@ -477,7 +477,7 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s * type of transfer mode */ while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t) - (mpc5200.ata_dctr_dasr)) & + (mpc5200.ata_dctr_dasr)) & IDE_REGISTER_STATUS_DRQ) == 0); /* * translate (part of) buffer list into DMA BDs @@ -495,14 +495,14 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s *lbuf++ = GET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*(volatile uint32_t *)(ata_reg)); /* only 16 bit data port */ cnt += 2; (*pos) += 2; - + if((*pos) == llength) { - + (*pos) = 0; (*cbuf)++; lbuf = bufs[(*cbuf)].buffer; llength = bufs[(*cbuf)].length; - + } } #else @@ -512,12 +512,12 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s *lbuf++ = *(volatile uint16_t *)(ata_reg); /* only 16 bit data port */ cnt += 2; (*pos) += 2; - + if((*pos) == llength) { (*pos) = 0; (*cbuf)++; lbuf = bufs[(*cbuf)].buffer; - llength = bufs[(*cbuf)].length; + llength = bufs[(*cbuf)].length; } } #endif @@ -525,12 +525,12 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s *lbuf++ = 0; /* fill buffer with dummy data */ cnt += 2; (*pos) += 2; - + if((*pos) == llength) { (*pos) = 0; (*cbuf)++; lbuf = bufs[(*cbuf)].buffer; - llength = bufs[(*cbuf)].length; + llength = bufs[(*cbuf)].length; } } } @@ -570,7 +570,7 @@ void mpc5200_pcmciaide_write_block(int minor, uint32_t block_size, * type of transfer mode */ while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t) - (mpc5200.ata_dctr_dasr)) & + (mpc5200.ata_dctr_dasr)) & IDE_REGISTER_STATUS_DRQ) == 0); /* * translate (part of) buffer list into DMA BDs @@ -595,28 +595,28 @@ void mpc5200_pcmciaide_write_block(int minor, uint32_t block_size, loop_max = (block_size - cnt); } for (loop_cnt = loop_max/2;loop_cnt > 0;loop_cnt--) { - *(volatile uint32_t *)(ata_reg) = + *(volatile uint32_t *)(ata_reg) = SET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*lbuf++); /* only 16 bit data port */ } cnt += loop_max; (*pos) += loop_max; - + if((*pos) == llength) { - + (*pos) = 0; (*cbuf)++; lbuf = bufs[(*cbuf)].buffer; - llength = bufs[(*cbuf)].length; + llength = bufs[(*cbuf)].length; } } #else - while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr)) - & IDE_REGISTER_STATUS_DRQ) + while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr)) + & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) { *(volatile uint16_t *)(ata_reg) = *lbuf++; /* only 16 bit data port */ cnt += 2; (*pos) += 2; - + if((*pos) == llength) { (*pos) = 0; (*cbuf)++; @@ -657,7 +657,7 @@ void mpc5200_pcmciaide_initialize(int minor) #if IDE_USE_DMA mpc5200_pcmciaide_dma_init(minor); -#endif +#endif } diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h index 6141fbf1be..7ba3538da5 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h @@ -25,7 +25,7 @@ #include <bspopts.h> -#include <libcpu/powerpc-utility.h> +#include <libcpu/powerpc-utility.h> /* * Some symbols defined in the linker command file. @@ -109,7 +109,7 @@ LINKER_SYMBOL(MBAR); /* * Codename: IceCube * Compatible Boards: - * Freescape MPC5200LITE + * Freescape MPC5200LITE * Embedded Planet EP5200 */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c b/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c index 78a3484e32..fd15c681ad 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c +++ b/c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c @@ -162,7 +162,7 @@ bool mscan_set_bit_rate( mscan *m, unsigned can_bit_rate) if (prescale_val > 64) { /* Leave initialization mode */ mscan_initialization_mode_leave( m, &context); - + return false; } @@ -454,7 +454,7 @@ uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i) &m->idar6, &m->idar7 }; - + return idar [i]; } @@ -476,7 +476,7 @@ uint8_t *mscan_id_mask_register( mscan *m, unsigned i) &m->idmr6, &m->idmr7 }; - + return idmr [i]; } diff --git a/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c b/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c index 8b4ede4d08..397667f56e 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c +++ b/c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c @@ -115,7 +115,7 @@ static TaskId txTaskId; /* SDMA TX task ID */ * The number of transmit buffer descriptors has to be quite large * since a single frame often uses four or more buffer descriptors. */ -#define RX_BUF_COUNT SDMA_BD_RX_NUM +#define RX_BUF_COUNT SDMA_BD_RX_NUM #define TX_BUF_COUNT SDMA_BD_TX_NUM #define TX_BD_PER_BUF 1 @@ -272,10 +272,10 @@ static void mpc5200_fec_rx_bd_init(struct mpc5200_enet_struct *sc) { m->m_pkthdr.rcvif = ifp; sc->rxMbuf[rxBdIndex] = m; - bdi = TaskBDAssign( rxTaskId, + bdi = TaskBDAssign( rxTaskId, mtod(m, void *), - NULL, - ETHER_MAX_LEN, + NULL, + ETHER_MAX_LEN, 0 ); if (bdi != rxBdIndex) { rtems_panic("network rx buffer indices out of sync"); @@ -526,7 +526,7 @@ static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) { */ mpc5200.rfifo_status &= FEC_FIFO_STAT_ERROR; mpc5200.tfifo_status &= FEC_FIFO_STAT_ERROR; - + /* * reset the FIFOs */ @@ -535,17 +535,17 @@ static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) { for (delay = 0;delay < 16*4;delay++) {}; mpc5200.reset_cntrl = 0x01000000; - + /* * Issue a reset command to the FEC chip */ mpc5200.ecntrl |= FEC_ECNTRL_RESET; - + /* * wait at least 16 clock cycles */ for (delay = 0;delay < 16*4;delay++) {}; - + return true; } @@ -564,7 +564,7 @@ static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) { void mpc5200_fec_off(struct mpc5200_enet_struct *sc) { int counter = 0xffff; - + #if defined(ETH_DEBUG) unsigned short phyStatus, i; @@ -619,7 +619,7 @@ void mpc5200_fec_off(struct mpc5200_enet_struct *sc) */ mpc5200.ecntrl &= ~(FEC_ECNTRL_OE | FEC_ECNTRL_EN); - /* + /* * cleanup all buffers */ mpc5200_fec_rx_bd_cleanup(sc); @@ -655,7 +655,7 @@ void mpc5200_fec_irq_handler(rtems_irq_hdl_param handle) if (ievent & FEC_INTR_RFIFO_ERR) { sc->rxOverrun++; } - /* + /* * fatal error ocurred? */ if (ievent & (FEC_INTR_XFIFO_ERR | FEC_INTR_RFIFO_ERR)) { @@ -678,7 +678,7 @@ void mpc5200_smartcomm_rx_irq_handler(rtems_irq_hdl_param unused) bestcomm_glue_irq_disable(FEC_RECV_TASK_NO);/*Disable receive ints*/ enet_driver[0].rxInterrupts++; /* Rx int has occurred */ - + rtems_event_send(enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); } @@ -728,7 +728,7 @@ static void mpc5200_fec_retire_tbd(struct mpc5200_enet_struct *sc, * Clear already transmitted BDs first. Will not work calling same * from fecExceptionHandler(TFINT). */ - + while ((sc->txBdActiveCount > 0) && (force || (bdRing[sc->txBdTail].Status == 0x0))) { if (sc->txMbuf[sc->txBdTail] != NULL) { @@ -741,7 +741,7 @@ static void mpc5200_fec_retire_tbd(struct mpc5200_enet_struct *sc, sc->txBdActiveCount--; if(++sc->txBdTail >= sc->txBdCount) { sc->txBdTail = 0; - } + } } } @@ -762,7 +762,7 @@ static void mpc5200_fec_tx_bd_requeue(struct mpc5200_enet_struct *sc) * Clear already transmitted BDs first. Will not work calling same * from fecExceptionHandler(TFINT). */ - + while (sc->txBdActiveCount > 0) { if (sc->txMbuf[sc->txBdHead] != NULL) { /* @@ -774,7 +774,7 @@ static void mpc5200_fec_tx_bd_requeue(struct mpc5200_enet_struct *sc) sc->txBdActiveCount--; if(--sc->txBdHead < 0) { sc->txBdHead = sc->txBdCount-1; - } + } } } #endif @@ -811,12 +811,12 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { * Wait for buffer descriptor to become available. */ if((sc->txBdActiveCount + nAdded) == sc->txBdCount) { - + /* * Clear old events */ SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_XMIT_TASK_NO); - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -830,11 +830,11 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { * an interrupt. */ mpc5200_fec_retire_tbd(sc,false); - + while((sc->txBdActiveCount + nAdded) == sc->txBdCount) { bestcomm_glue_irq_enable(FEC_XMIT_TASK_NO); - rtems_bsdnet_event_receive(INTERRUPT_EVENT, - RTEMS_WAIT | RTEMS_EVENT_ANY, + rtems_bsdnet_event_receive(INTERRUPT_EVENT, + RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); mpc5200_fec_retire_tbd(sc,false); } @@ -846,7 +846,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { */ struct mbuf *n; MFREE(m, n); - m = n; + m = n; if(l != NULL) { l->m_next = m; } @@ -866,7 +866,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { * FIXME: do not send interrupt after every frame * doing this every quarter of BDs is much more efficent */ - status = ((m->m_next == NULL) + status = ((m->m_next == NULL) ? TASK_BD_TFD | TASK_BD_INT : 0); /* @@ -878,7 +878,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { } else { firstBd = thisBd; - } + } data_ptr = mtod(m, void *); data_len = (uint32)m->m_len; @@ -904,7 +904,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) { if(nAdded) { firstBd->Status |= SDMA_BD_MASK_READY; SDMA_TASK_ENABLE(SDMA_TCR, txTaskId); - sc->txBdActiveCount += nAdded; + sc->txBdActiveCount += nAdded; } break; } @@ -927,9 +927,9 @@ void mpc5200_fec_txDaemon(void *arg) * Wait for packet */ bestcomm_glue_irq_enable(FEC_XMIT_TASK_NO); - rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, + rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, &events); /* @@ -978,7 +978,7 @@ static void mpc5200_fec_rxDaemon(void *arg){ * Input packet handling loop */ rxBdIndex = 0; - + for (;;) { /* * Clear old events @@ -990,30 +990,30 @@ static void mpc5200_fec_rxDaemon(void *arg){ bd = bdRing + rxBdIndex; status = bd->Status; len = (uint16)GET_BD_LENGTH( bd ); - + /* * Loop through BDs until we find an empty one. This indicates that * the SmartDMA is still using it. */ while( !(status & SDMA_BD_MASK_READY) ) { - + /* * Remember the data pointer from this transfer. */ dptr = (void *)bd->DataPtr[0]; m = sc->rxMbuf[rxBdIndex]; - m->m_len = m->m_pkthdr.len = (len - - sizeof(uint32_t) + m->m_len = m->m_pkthdr.len = (len + - sizeof(uint32_t) - sizeof(struct ether_header)); eh = mtod(m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input(ifp, eh, m); - + /* * Done w/ the BD. Clean it. */ sc->rxMbuf[rxBdIndex] = NULL; - + /* * Add a new buffer to the ring. */ @@ -1026,7 +1026,7 @@ static void mpc5200_fec_rxDaemon(void *arg){ bd->DataPtr[0] = (uint32)mtod(m, void *); bd->Status = ( ( (uint32)SDMA_DRD_MASK_LENGTH & (uint32)size) | ((uint32)SDMA_BD_MASK_READY)); - + /* * advance to next BD */ @@ -1038,15 +1038,15 @@ static void mpc5200_fec_rxDaemon(void *arg){ */ bd = bdRing + rxBdIndex; status = bd->Status; - len = (uint16)GET_BD_LENGTH( bd ); + len = (uint16)GET_BD_LENGTH( bd ); } /* * Unmask RXF (Full frame received) event */ bestcomm_glue_irq_enable(FEC_RECV_TASK_NO); - - rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT, - RTEMS_WAIT | RTEMS_EVENT_ANY, + + rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT, + RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); if (events & FATAL_INT_EVENT) { /* @@ -1091,10 +1091,10 @@ static void mpc5200_fec_initialize_hardware(struct mpc5200_enet_struct *sc) * Set FEC-Lite receive control register (R_CNTRL) * frame length=1518, MII mode for 18-wire-transceiver */ - mpc5200.r_cntrl = ((ETHER_MAX_LEN << FEC_RCNTRL_MAX_FL_SHIFT) - | FEC_RCNTRL_FCE + mpc5200.r_cntrl = ((ETHER_MAX_LEN << FEC_RCNTRL_MAX_FL_SHIFT) + | FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE); - + /* * Set FEC-Lite transmit control register (X_CNTRL) * full-duplex, heartbeat disabled @@ -1301,7 +1301,7 @@ static void mpc5200_sdma_task_setup(struct mpc5200_enet_struct *sc) { rxParam.SzSrc = sizeof(uint32_t); rxParam.StartAddrDst = (uint32)NULL; rxParam.IncrDst = sizeof(uint32_t); - rxParam.SzDst = sizeof(uint32_t); + rxParam.SzDst = sizeof(uint32_t); rxTaskId = TaskSetup(TASK_FEC_RX,&rxParam ); /* @@ -1316,7 +1316,7 @@ static void mpc5200_sdma_task_setup(struct mpc5200_enet_struct *sc) { txParam.StartAddrDst = (uint32)&(mpc5200.tfifo_data); txParam.IncrDst = 0; txParam.SzDst = sizeof(uint32_t); - + txTaskId = TaskSetup( TASK_FEC_TX, &txParam ); } @@ -1361,18 +1361,18 @@ static void mpc5200_fec_init(void *arg) /* * Allocate a set of mbuf pointers */ - sc->rxMbuf = + sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = + sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); - + if(!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers"); bestcomm_glue_init(); mpc5200_sdma_task_setup(sc); - + /* * Set up interrupts */ @@ -1413,7 +1413,7 @@ static void mpc5200_fec_init(void *arg) * Clear SmartDMA task interrupt pending bits. */ TaskIntClear( rxTaskId ); - + /* * Enable the SmartDMA receive task. */ @@ -1452,7 +1452,7 @@ static void enet_stats (struct mpc5200_enet_struct *sc) printf (" Bad CRC:%-8lu", sc->rxBadCRC); printf (" Overrun:%-8lu", sc->rxOverrun); printf (" Collision:%-8lu\n", sc->rxCollision); - + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); printf (" Deferred:%-8lu", sc->txDeferred); printf (" Late Collision:%-8lu\n", sc->txLateCollision); @@ -1464,12 +1464,12 @@ static void enet_stats (struct mpc5200_enet_struct *sc) /* * restart the driver, reinit the fec - * this function is responsible to reinitialize the FEC in case a fatal + * this function is responsible to reinitialize the FEC in case a fatal * error has ocurred. This is needed, wen a RxFIFO Overrun or a TxFIFO underrun * has ocurred. In these cases, the FEC is automatically disabled, and * both FIFOs must be reset and the BestComm tasks must be restarted * - * Note: the daemon tasks will continue to run + * Note: the daemon tasks will continue to run * (in fact this function will be called in the context of the rx daemon task) */ #define NEW_SDMA_SETUP @@ -1530,7 +1530,7 @@ static void mpc5200_fec_restart(struct mpc5200_enet_struct *sc) * Clear SmartDMA task interrupt pending bits. */ TaskIntClear( rxTaskId ); - + /* * Enable the SmartDMA receive/transmit task. */ @@ -1587,7 +1587,7 @@ static int mpc5200_fec_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_ error = (command == SIOCADDMULTI) ? ether_addmulti(ifr, &sc->arpcom) : ether_delmulti(ifr, &sc->arpcom); - + if (error == ENETRESET) { if (ifp->if_flags & IFF_RUNNING) error = mpc5200_fec_setMultiFilter(ifp); diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S index 4e81be6c64..a5206351f6 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S +++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S @@ -104,7 +104,7 @@ .set SDRAMCS1, 0x38 .set BOOTSTR, 0x4C .set BOOTSTP, 0x50 -.set ADREN, 0x54 +.set ADREN, 0x54 .set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */ .set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */ .set CFG, 0x20C @@ -122,7 +122,7 @@ /* Register offsets of MPC5x00 GPIO registers needed */ .set GPIOPCR, 0xb00 -.set GPIOWE, 0xc00 +.set GPIOWE, 0xc00 .set GPIOWOD, 0xc04 .set GPIOWDD, 0xc08 .set GPIOWDO, 0xc0c @@ -156,7 +156,7 @@ .extern boot_card -.section ".entry" +.section ".entry" PUBLIC_VAR (start) start: /* 1st: initialization work (common for RAM/ROM startup) */ @@ -164,9 +164,9 @@ start: SETBITS r30, r29, MSR_ME|MSR_RI CLRBITS r30, r29, MSR_EE mtmsr r30 /* Set RI/ME, Clr EE in MSR */ - + #if defined(HAS_UBOOT) -/* store pointer to UBoot bd_info board info structure */ +/* store pointer to UBoot bd_info board info structure */ LWI r31,bsp_uboot_board_info_ptr stw r3,0(r31) #endif /* defined(HAS_UBOOT) */ @@ -176,8 +176,8 @@ start: LWI r31, MBAR_RESET LWI r29, MBAR rlwinm r30, r29,16,16,31 - stw r30, 0(r31) /* Set the MBAR */ -#endif + stw r30, 0(r31) /* Set the MBAR */ +#endif LWI r31, MBAR /* set r31 to current MBAR */ /* init GPIOPCR */ @@ -188,70 +188,70 @@ start: LWI r30, GPIOPCR_INITVAL or r29,r29,r30 stw r29, GPIOPCR(r31) - -/* further initialization work (common RAM/ROM startup) */ - bl TLB_init /* Initialize TLBs */ - - + +/* further initialization work (common RAM/ROM startup) */ + bl TLB_init /* Initialize TLBs */ + + bl FID_DCache /* Flush, inhibit and disable data cache */ - - + + bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */ - - - bl FPU_init /* Initialize FPU */ - - + + + bl FPU_init /* Initialize FPU */ + + #if defined(NEED_LOW_LEVEL_INIT) - bl SPRG_init /* Initialize special purpose registers */ -#endif - + bl SPRG_init /* Initialize special purpose registers */ +#endif + #if defined(NEED_LOW_LEVEL_INIT) /* detect RAM/ROM startup (common for RAM/ROM startup) */ LWI r20, bsp_rom_start /* set the relocation offset */ - - + + LWI r30, CFG_VAL /* get CFG register content */ lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */ - - + + lwz r30, ADREN(r31) /* get content of ADREN */ - - - + + + TSTBITS r30, r29, ADREN_BOOT_EN bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */ -/* do some board dependent configuration (unique for ROM startup) */ - bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */ - - +/* do some board dependent configuration (unique for ROM startup) */ + bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */ + + LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */ stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */ - - + + #ifdef BRS5L LWI r30, CSBOOTROM_VAL stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */ - - + + #endif - + /* FIXME: map BOOT ROM into final location with CS0 registers */ LWI r30, bsp_rom_start rlwinm r30, r30,17,15,31 - stw r30, CS0STR(r31) /* Set CS0STR */ - + stw r30, CS0STR(r31) /* Set CS0STR */ + LWI r30, bsp_rom_end - + rlwinm r30, r30,17,15,31 stw r30, CS0STP(r31) /* Set CS0STP */ - + lwz r30, ADREN(r31) /* get content of ADREN */ - SETBITS r30, r29, ADREN_CS0_EN + SETBITS r30, r29, ADREN_CS0_EN stw r30, ADREN(r31) /* enable CS0 mapping */ isync /* jump to same code in final BOOT ROM location */ @@ -262,13 +262,13 @@ start: add r30,r30,r29 mtctr r30 bctr - -reloc_in_CS0: + +reloc_in_CS0: /* disable CSBOOT (or map it to CS0 range) */ lwz r30, ADREN(r31) /* get content of ADREN */ - CLRBITS r30, r29, ADREN_BOOT_EN + CLRBITS r30, r29, ADREN_BOOT_EN stw r30, ADREN(r31) /* disable BOOT mapping */ - + /* init SDRAM */ LWI r30, bsp_ram_start ori r30, r30, 0x1a /* size code: bank is 128MByte */ @@ -278,96 +278,96 @@ reloc_in_CS0: srawi r30, r30, 1 ori r30, r30, 0x1a /* size code: bank is 128MByte */ stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */ - + bl SDRAM_init /* Initialize SDRAM controller */ /* init arbiter and stuff... */ LWI r30, 0x8000a06e stw r30, ARBCFG(r31) /* Set ARBCFG */ - + LWI r30, 0x000000ff stw r30, ARBMPREN(r31) /* Set ARBMPREN */ - + LWI r30, 0x00001234 - stw r30, ARBMPRIO(r31) /* Set ARBPRIO */ + stw r30, ARBMPRIO(r31) /* Set ARBPRIO */ LWI r30, 0x0000001e - stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */ + stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */ /* copy .text section from ROM to RAM location (unique for ROM startup) */ LA r30, bsp_section_text_start /* get start address of text section in RAM */ - - + + add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */ - - + + LA r29, bsp_section_text_start /* get start address of text section in RAM */ - + LA r28, bsp_section_text_size /* get size of RAM image */ - - + + bl copy_image /* copy text section from ROM to RAM location */ - + /* copy .data section from ROM to RAM location (unique for ROM startup) */ LA r30, bsp_section_data_start /* get start address of data section in RAM */ - - + + add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */ - - + + LA r29, bsp_section_data_start /* get start address of data section in RAM */ - - + + LA r28, bsp_section_data_size /* get size of RAM image */ - - + + bl copy_image /* copy initialized data section from ROM to RAM location */ - + LA r29, remap_rom /* get compile time address of label */ mtlr r29 - + blrl /* now further execution RAM */ -remap_rom: +remap_rom: /* remap BOOT ROM to CS0 (common for RAM/ROM startup) */ lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */ - - - - CLRBITS r30, r29, CSCONF_CE - stw r30, CSBOOTROM(r31) /* disable BOOT CS */ - - + + + + CLRBITS r30, r29, CSCONF_CE + stw r30, CSBOOTROM(r31) /* disable BOOT CS */ + + lwz r30, ADREN(r31) /* get content of ADREN */ - - + + mr r29, r30 /* move content of r30 to r29 */ - - + + LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */ - andc r29,r29,r30 - - + andc r29,r29,r30 + + LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */ - or r29,r29,r30 - - + or r29,r29,r30 + + stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */ - - - + + + lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */ - - - - SETBITS r30, r29, CSCONF_CE - stw r30, CSBOOTROM(r31) /* disable BOOT CS */ - - + + + + SETBITS r30, r29, CSCONF_CE + stw r30, CSBOOTROM(r31) /* disable BOOT CS */ + + skip_ROM_start: /* configure external DPRAM CS1 */ @@ -384,62 +384,62 @@ skip_ROM_start: stw r30, CS1STP(r31) lwz r30, ADREN(r31) /* get content of ADREN */ - + LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */ - or r30, r30,r29 - + or r30, r30,r29 + stw r30, ADREN(r31) /* enable CS1 */ /* clear entire on chip SRAM (unique for ROM startup) */ lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */ ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */ - + bl clr_mem /* Clear onchip SRAM */ - + #endif /* defined(BRS5L) */ /* clear .bss section (unique for ROM startup) */ LWI r30, bsp_section_bss_start /* get start address of bss section */ LWI r29, bsp_section_bss_size /* get size of bss section */ - + bl clr_mem /* Clear the bss section */ - + /* set stack pointer (common for RAM/ROM startup) */ - LA r1, bsp_section_text_start + LA r1, bsp_section_text_start addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ bl __eabi /* Set up EABI and SYSV environment */ - + /* enable dynamic power management(common for RAM/ROM startup) */ bl PPC_HID0_rd /* Get the content of HID0 */ - - SETBITS r30, r29, HID0_DPM + + SETBITS r30, r29, HID0_DPM bl PPC_HID0_wr /* Set DPM in HID0 */ /* clear arguments and do further init. in C (common for RAM/ROM startup) */ /* Clear cmdline */ xor r3, r3, r3 - + bl SYM (boot_card) /* Call the first C routine */ #if defined(BRS5L) -twiddle: +twiddle: b twiddle /* We don't expect to return from boot_card but if we do */ /* wait here for watchdog to kick us into hard reset */ -SDRAM_init: +SDRAM_init: #if defined (BRS5L) /* set GPIO_WKUP7 pin low for 66MHz buffering */ /* or high for 133MHz registered buffering */ LWI r30, 0x80000000 - + lwz r29, GPIOWE(r31) or r29,r29,r30 /* set bit 0 in r29/GPIOWE */ stw r29,GPIOWE(r31) - + lwz r29, GPIOWOD(r31) andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */ stw r29,GPIOWOD(r31) @@ -447,7 +447,7 @@ SDRAM_init: lwz r29, GPIOWDO(r31) andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */ stw r29,GPIOWDO(r31) - + lwz r29, GPIOWDD(r31) or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */ stw r29,GPIOWDD(r31) @@ -459,66 +459,66 @@ SDRAM_init: #endif #if 0 - LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ - stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ + LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ + stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ /* Refr.2No-Read delay=0x06, Write latency=0x0 */ #else /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */ /* set 5 delays to their maximum to support two banks */ - LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ - stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ + LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ + stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ /* Refr.2No-Read delay=0x06, Write latency=0x0 */ -#endif - - LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ +#endif + + LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */ - + #ifdef BRS5L LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ stw r30, CTRL(r31) /* Refresh counter=0xFFFF */ - - + + #else LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */ stw r30, CTRL(r31) /* Refresh counter=0xFFFF */ - - -#endif - lwz r30, CTRL(r31) - + + +#endif + lwz r30, CTRL(r31) + SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */ stw r30, CTRL(r31) - - + + stw r30, CTRL(r31) - - - + + + lwz r30, CTRL(r31) - - + + SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */ stw r30, CTRL(r31) - - + + stw r30, CTRL(r31) - - - + + + LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */ - stw r30, MOD(r31) - - + stw r30, MOD(r31) + + + + lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */ + - lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */ - - CLRBITS r30, r29, CTRL_BA1 stw r30, CTRL(r31) - - - + + + blr @@ -526,21 +526,21 @@ copy_image: mr r27, r28 srwi r28, r28, 2 mtctr r28 - - + + slwi r28, r28, 2 sub r27, r27, r28 /* maybe some residual bytes */ - - + + copy_image_word: lswi r28, r30, 0x04 - + stswi r28, r29, 0x04 /* do word copy ROM -> RAM */ - + addi r30, r30, 0x04 /* increment source pointer */ addi r29, r29, 0x04 /* increment destination pointer */ - + bdnz copy_image_word /* decrement ctr and branch if not 0 */ cmpwi r27, 0x00 /* copy image finished ? */ @@ -548,24 +548,24 @@ copy_image_word: mtctr r27 /* reload counter for residual bytes */ copy_image_byte: lswi r28, r30, 0x01 - + stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */ - - + + addi r30, r30, 0x01 /* increment source pointer */ addi r29, r29, 0x01 /* increment destination pointer */ - + bdnz copy_image_byte /* decrement ctr and branch if not 0 */ - + copy_image_end: blr #endif /* defined(BRS5L) */ FID_DCache: - mflr r26 - - bl PPC_HID0_rd - TSTBITS r30, r29, HID0_DCE + mflr r26 + + bl PPC_HID0_rd + TSTBITS r30, r29, HID0_DCE bne FID_DCache_exit /* If data cache is switched of, skip further actions */ li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ @@ -573,9 +573,9 @@ FID_DCache: FID_DCache_loop_1: lwz r27, 0(r28) /* Load data at address */ - + addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */ - subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ + subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ cmpwi r29, 0x0 bne FID_DCache_loop_1 /* Loop until cache size is reached */ @@ -583,17 +583,17 @@ FID_DCache_loop_1: LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */ xor r27, r27, r27 FID_DCache_loop_2: - + dcbf r27, r28 /* Flush and invalidate cache */ - + addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */ - subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ + subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */ cmpwi r29, 0x0 bne FID_DCache_loop_2 /* Loop around until cache size is reached */ - bl PPC_HID0_rd /* Read HID0 */ + bl PPC_HID0_rd /* Read HID0 */ CLRBITS r30, r29, HID0_DCE - bl PPC_HID0_wr /* Clear DCE */ + bl PPC_HID0_wr /* Clear DCE */ FID_DCache_exit: mtlr r26 @@ -601,33 +601,33 @@ FID_DCache_exit: IDUL_ICache: mflr r26 - - bl PPC_HID0_rd + + bl PPC_HID0_rd TSTBITS r30, r29, HID0_ICE bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */ - CLRBITS r30, r29, HID0_ICE + CLRBITS r30, r29, HID0_ICE bl PPC_HID0_wr /* Disable ICE bit */ - SETBITS r30, r29, HID0_ICFI + SETBITS r30, r29, HID0_ICFI bl PPC_HID0_wr /* Invalidate instruction cache */ - - CLRBITS r30, r29, HID0_ICFI + + CLRBITS r30, r29, HID0_ICFI bl PPC_HID0_wr /* Disable cache invalidate */ - - CLRBITS r30, r29, HID0_ILOCK - bl PPC_HID0_wr /* Disable instruction cache lock */ + + CLRBITS r30, r29, HID0_ILOCK + bl PPC_HID0_wr /* Disable instruction cache lock */ IDUL_ICache_exit: mtlr r26 blr - - + + TLB_init: /* Initialize translation lookaside buffers (TLBs) */ xor r30, r30, r30 - xor r29, r29, r29 - -TLB_init_loop: + xor r29, r29, r29 + +TLB_init_loop: tlbie r29 tlbsync addi r29, r29, 0x1000 @@ -638,16 +638,16 @@ TLB_init_loop: FPU_init: mfmsr r30 /* get content of MSR */ - - + + SETBITS r30, r29, MSR_FP mtmsr r30 /* enable FPU and FPU exceptions */ - -#if 0 + +#if 0 LA r29, bsp_ram_start stw r29, 0x0(r29) -#endif - +#endif + lfd f0, 0(r29) fmr f1, f0 fmr f2, f0 @@ -680,8 +680,8 @@ FPU_init: fmr f29, f0 fmr f30, f0 fmr f31, f0 - - + + mtfsfi 0, 0 /* initialize bit positons in FPSCR */ mtfsfi 1, 0 mtfsfi 2, 0 @@ -690,12 +690,12 @@ FPU_init: mtfsfi 5, 0 mtfsfi 6, 0 mtfsfi 7, 0 - + blr SPRG_init: /* initialize registers */ xor r30, r30, r30 - + mtspr XER, r30 mtspr CTR, r30 mtspr DSISR, r30 @@ -709,7 +709,7 @@ SPRG_init: /* initialize registers */ mtspr SPRG0, r30 mtspr SPRG1, r30 mtspr SPRG2, r30 - mtspr SPRG3, r30 + mtspr SPRG3, r30 mtspr SPRG4, r30 mtspr SPRG5, r30 mtspr SPRG6, r30 @@ -771,74 +771,74 @@ SPRG_init: /* initialize registers */ mtsr SR13, r30 mtsr SR14, r30 mtsr SR15, r30 - - - - - + + + + + blr SPRG_brk_init: xor r30, r30, r30 - + mtspr DABR2, r30 mtspr DBCR, r30 mtspr IBCR, r30 mtspr IABR, r30 mtspr HID2, r30 mtspr DABR, r30 - mtspr IABR2, r30 + mtspr IABR2, r30 + + + - - - blr - + PPC_HID0_rd: /* get HID0 content to r30 */ - - + + mfspr r30, HID0 - + blr PPC_HID0_wr: /* put r30 content to HID0 */ - - + + mtspr HID0, r30 - + blr clr_mem: - mr r28, r29 + mr r28, r29 srwi r29, r29, 2 mtctr r29 /* set ctr reg */ - - + + slwi r29, r29, 2 sub r28, r28, r29 /* maybe some residual bytes */ - xor r29, r29, r29 - - + xor r29, r29, r29 + + clr_mem_word: stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */ addi r30, r30, 0x04 /* increment r30 */ - + bdnz clr_mem_word /* dec counter and loop */ - - + + cmpwi r28, 0x00 /* clear mem. finished ? */ beq clr_mem_end; mtctr r28 /* reload counter for residual bytes */ clr_mem_byte: stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */ addi r30, r30, 0x01 /* update r30 */ - + bdnz clr_mem_byte /* dec counter and loop */ - + clr_mem_end: blr /* return */ - - + + diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/bspreset.c b/c/src/lib/libbsp/powerpc/gen5200/startup/bspreset.c index 4690b2a168..42d922f0d3 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/bspreset.c +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/bspreset.c @@ -21,7 +21,7 @@ void bsp_reset( void ) BSP_IRQ_Benchmarking_Report(); } #endif - + /* * Now reset the CPU */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c b/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c index ce621c881c..f5d74c1571 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c @@ -144,7 +144,7 @@ void bsp_start(void) #if defined(HAS_UBOOT) bsp_uboot_board_info = *bsp_uboot_board_info_ptr; - #endif + #endif #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS) { diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c index a2e988279a..289dc6d7e8 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c @@ -98,18 +98,18 @@ static void calc_dbat_regvals( while ((end_addr & block_mask) != (base_addr & block_mask)) { block_mask <<= 1; } - - bat_ptr->batu.bepi = base_addr >> (32 - 15); + + bat_ptr->batu.bepi = base_addr >> (32 - 15); bat_ptr->batu.bl = ~(block_mask >> (28 - 11)); bat_ptr->batu.vs = 1; bat_ptr->batu.vp = 1; - - bat_ptr->batl.brpn = base_addr >> (32 - 15); - bat_ptr->batl.w = flg_w; - bat_ptr->batl.i = flg_i; - bat_ptr->batl.m = flg_m; - bat_ptr->batl.g = flg_g; - bat_ptr->batl.pp = flg_bpp; + + bat_ptr->batl.brpn = base_addr >> (32 - 15); + bat_ptr->batl.w = flg_w; + bat_ptr->batl.i = flg_i; + bat_ptr->batl.m = flg_m; + bat_ptr->batl.g = flg_g; + bat_ptr->batl.pp = flg_bpp; } #if defined (BRS5L) @@ -170,7 +170,7 @@ void cpu_init_bsp(void) { BAT dbat; uint32_t start = 0; - + /* * Program BAT0 for RAM */ @@ -272,7 +272,7 @@ void cpu_init(void) /* Update MSR */ ppc_set_machine_state_register( msr); - /* + /* * Enable data cache. * * NOTE: TRACE32 now supports data cache for MGT5x00. diff --git a/c/src/lib/libbsp/powerpc/gen5200/tod/pcf8563.c b/c/src/lib/libbsp/powerpc/gen5200/tod/pcf8563.c index a925bd28e4..4fc35f7a25 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/tod/pcf8563.c +++ b/c/src/lib/libbsp/powerpc/gen5200/tod/pcf8563.c @@ -30,7 +30,7 @@ * RTC I2C device address. * * Based on a ds1307 driver from: - * + * * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia * Author: Victor V. Vengerov <vvv@oktet.ru> * @@ -74,7 +74,7 @@ pcf8563_initialize(int minor) /* Read SECONDS register */ try = 0; do { - status = i2c_wbrd(bus, addr, PCF8563_CONTROL1_ADR, + status = i2c_wbrd(bus, addr, PCF8563_CONTROL1_ADR, &ctrl1, sizeof(ctrl1)); try++; } while ((status != I2C_SUCCESSFUL) && (try < 15)); @@ -134,7 +134,7 @@ pcf8563_get_time(int minor, rtems_time_of_day *time) v1 = info[PCF8563_YEAR_ADR-PCF8563_SECOND_ADR]; v2 = From_BCD(v1); - if ((info[PCF8563_MONTH_ADR-PCF8563_SECOND_ADR] + if ((info[PCF8563_MONTH_ADR-PCF8563_SECOND_ADR] & PCF8563_MONTH_CENTURY) == 0) { time->year = 1900 + v2; } @@ -198,10 +198,10 @@ pcf8563_set_time(int minor, const rtems_time_of_day *time) info[1 + PCF8563_MINUTE_ADR-PCF8563_SECOND_ADR] = To_BCD(time->minute); info[1 + PCF8563_SECOND_ADR-PCF8563_SECOND_ADR] = To_BCD(time->second); /* Do not set day of week */ - info[1 + PCF8563_DAY_OF_WEEK_ADR-PCF8563_SECOND_ADR] = 1; + info[1 + PCF8563_DAY_OF_WEEK_ADR-PCF8563_SECOND_ADR] = 1; /* - * add century info + * add century info */ if (time->year >= 2000) { info[1 + PCF8563_MONTH_ADR -PCF8563_SECOND_ADR] |= PCF8563_MONTH_CENTURY; |