2010-11-12 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* make/custom/dp2.cfg, startup/linkcmds.dp2: New files.
	* Makefile.am, preinstall.am: Reflect change above.  Install
	<bsp/utility.h>.  Install BestComm header files.
	* configure.ac: Changed BSP options.
	* include/mpc5200.h: Added module structures and register defines.
	* bestcomm/bestcomm_api.c, bestcomm/bestcomm_api.h,
	bestcomm/bestcomm_glue.c, bestcomm/bestcomm_glue.h,
	bestcomm/bestcomm_priv.h, bestcomm/load_task.c,
	bestcomm/tasksetup_bdtable.c, bestcomm/task_api/bestcomm_cntrl.h: C++
	compatibility.  Use special heap to manage the SRAM region.  Use
	interrupt extension API.  Fixed warnings.
	* console/console.c: Fixed console registration.  Fixed warnings.
	Added GPS module registration.
	* ide/pcmcia_ide.h: Fixed clock value macros.
	* ide/pcmcia_ide.c: Update for BestComm API changes.
	DP2 specific initialization.  Removed zero loop in PIO receive
	function.
	* include/bsp.h: Added DP2 variant.  Removed obsolete defines.
	* include/mscan-base.h, mscan/mscan-base.c: Use volatile qualifier.
	Format.
	* irq/irq.c: Fixed peripheral interrupt handling.
	* network_5200/network.c: Update for BestComm API changes.
	* start/start.S: U-Boot fixes.
	* startup/cpuinit.c: Enable write-back cache strategy.  Added special
	memory regions.
	* startup/linkcmds.brs5l: Fixed memory size.

1 files changed, 41 insertions, 10 deletions

diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
index 289dc6d7e8..549972a4d9 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
+++ b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
@@ -112,16 +112,16 @@ static void calc_dbat_regvals(
   bat_ptr->batl.pp   = flg_bpp;
 }
 
-#if defined (BRS5L)
-void cpu_init_bsp(void)
+static void cpu_init_bsp(void)
 {
+#if defined (BRS5L)
   BAT dbat;
 
   calc_dbat_regvals(
     &dbat,
     (uint32_t) bsp_ram_start,
     (uint32_t) bsp_ram_size,
-    true,
+    false,
     false,
     false,
     false,
@@ -133,7 +133,7 @@ void cpu_init_bsp(void)
     &dbat,
     (uint32_t) bsp_rom_start,
     (uint32_t) bsp_rom_size,
-    true,
+    false,
     false,
     false,
     false,
@@ -164,10 +164,7 @@ void cpu_init_bsp(void)
     BPP_RW
   );
   SET_DBAT(3,dbat.batu,dbat.batl);
-}
 #elif defined (HAS_UBOOT)
-void cpu_init_bsp(void)
-{
   BAT dbat;
   uint32_t start = 0;
 
@@ -178,7 +175,7 @@ void cpu_init_bsp(void)
     &dbat,
     bsp_uboot_board_info.bi_memstart,
     bsp_uboot_board_info.bi_memsize,
-    true,
+    false,
     false,
     false,
     false,
@@ -203,7 +200,7 @@ void cpu_init_bsp(void)
     &dbat,
     start,
     bsp_uboot_board_info.bi_flashsize,
-    true,
+    false,
     false,
     false,
     false,
@@ -242,11 +239,45 @@ void cpu_init_bsp(void)
     );
     SET_DBAT(3,dbat.batu,dbat.batl);
   }
-}
 #else
 #warning "Using BAT register values set by environment"
 #endif
 
+#if defined(BSP_TYPE_DP2)
+  /* Enable BAT4-7 */
+  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13));
+
+  /* FPGA */
+  calc_dbat_regvals(
+    &dbat,
+    0xf0020000,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(4, dbat.batu, dbat.batl);
+#elif defined(PM520_ZE30)
+  /* Enable BAT4-7 */
+  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13));
+
+  /* External CC770 CAN controller available in version 2 */
+  calc_dbat_regvals(
+    &dbat,
+    0xf2000000,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(4, dbat.batu, dbat.batl);
+#endif
+}
+
 void cpu_init(void)
 {
   uint32_t msr;