Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier

<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:

  + BSPs for many variations on the Motorola MBX8xx board series
  + Cache Manager including initial support for m68040
    and PowerPC
  + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
    same code base.
  + Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860.

2 files changed, 0 insertions, 245 deletions

diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c
deleted file mode 100644
index b43cb4877b..0000000000
--- a/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * MPC860 buffer descriptor allocation routines
- *
- * Modified from original code by Jay Monkman (jmonkman@frasca.com)
- *
- * Original was written by:
- * W. Eric Norum
- * Saskatchewan Accelerator Laboratory
- * University of Saskatchewan
- * Saskatoon, Saskatchewan, CANADA
- * eric@skatter.usask.ca
- *
- *  $Id$
- */
-
-#include <rtems.h>
-#include <bsp.h>
-#include <rtems/rtems/intr.h>
-#include <rtems/error.h>
-#include <mpc860.h>
-#include <info.h>
-
-/*
- * Send a command to the CPM RISC processer
- */
-void M860ExecuteRISC(rtems_unsigned16 command)
-{
-  rtems_unsigned16 lvl;
-  
-  rtems_interrupt_disable(lvl);
-  while (m860.cpcr & M860_CR_FLG) {
-    continue;
-  }
-
-  m860.cpcr = command | M860_CR_FLG;
-  rtems_interrupt_enable (lvl);
-}
-
-
-/*
- * Allocation order:
- *      - Dual-Port RAM section 0
- *      - Dual-Port RAM section 1
- *      - Dual-Port RAM section 2
- *      - Dual-Port RAM section 3
- *      - Dual-Port RAM section 4
- */
-static struct {
-  char          *base;
-  unsigned int  size;
-  unsigned int  used;
-} bdregions[] = {
-  { (char *)&m860.dpram0[0],    sizeof m860.dpram0,     0 },
-  { (char *)&m860.dpram1[0],    sizeof m860.dpram1,     0 },
-  { (char *)&m860.dpram2[0],    sizeof m860.dpram2,     0 },
-  { (char *)&m860.dpram3[0],    sizeof m860.dpram3,     0 },
-  { (char *)&m860.dpram4[0],    sizeof m860.dpram4,     0 },
-};
-
-void *
-M860AllocateBufferDescriptors (int count)
-{
-  unsigned int i;
-  ISR_Level level;
-  void *bdp = NULL;
-  unsigned int want = count * sizeof(m860BufferDescriptor_t);
-  
-  /*
-   * Running with interrupts disabled is usually considered bad
-   * form, but this routine is probably being run as part of an
-   * initialization sequence so the effect shouldn't be too severe.
-   */
-  _ISR_Disable (level);
-  for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) {
-    /*
-     * Verify that the region exists.
-     * This test is necessary since some chips have
-     * less dual-port RAM.
-     */
-    if (bdregions[i].used == 0) {
-      volatile unsigned char *cp = bdregions[i].base;
-      *cp = 0xAA;
-      if (*cp != 0xAA) {
-        bdregions[i].used = bdregions[i].size;
-        continue;
-      }
-      *cp = 0x55;
-      if (*cp != 0x55) {
-        bdregions[i].used = bdregions[i].size;
-        continue;
-      }
-      *cp = 0x0;
-    }
-    if (bdregions[i].size - bdregions[i].used >= want) {
-      bdp = bdregions[i].base + bdregions[i].used;
-      bdregions[i].used += want;
-      break;
-    }
-  }
-  _ISR_Enable(level);
-  if (bdp == NULL)
-    rtems_panic("Can't allocate %d buffer descriptor(s).\n", count);
-  return bdp;
-}
-
-void *
-M860AllocateRiscTimers (int count)
-{
-  /*
-   * Convert the count to the number of buffer descriptors
-   * of equal or larger size.  This ensures that all buffer
-   * descriptors are allocated with appropriate alignment.
-   */
-  return M860AllocateBufferDescriptors (((count * 4) +
-                                         sizeof(m860BufferDescriptor_t) - 1) / 
-                                        sizeof(m860BufferDescriptor_t));
-}
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c
deleted file mode 100644
index 04f29a9397..0000000000
--- a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* 
- *  mmu.c - this file contains functions for initializing the MMU 
- *
- *  Written by Jay Monkman (jmonkman@frasca.com)
- * 
- *  $Id$
- */
-
-#include <bsp.h>
-#include <mpc860.h>
-
-/* Macros for handling all the MMU SPRs */
-#define PUT_MI_CTR(r)   __asm__ volatile ("mtspr 0x310,%0\n" ::"r"(r))
-#define GET_MI_CTR(r)   __asm__ volatile ("mfspr %0,0x310\n" :"=r"(r))
-#define PUT_MD_CTR(r)   __asm__ volatile ("mtspr 0x318,%0\n" ::"r"(r))
-#define GET_MD_CTR(r)   __asm__ volatile ("mfspr %0,0x318\n" :"=r"(r))
-#define PUT_M_CASID(r)  __asm__ volatile ("mtspr 0x319,%0\n" ::"r"(r))
-#define GET_M_CASID(r)  __asm__ volatile ("mfspr %0,0x319\n" :"=r"(r))
-#define PUT_MI_EPN(r)   __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r))
-#define GET_MI_EPN(r)   __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r))
-#define PUT_MI_TWC(r)   __asm__ volatile ("mtspr 0x315,%0\n" ::"r"(r))
-#define GET_MI_TWC(r)   __asm__ volatile ("mfspr %0,0x315\n" :"=r"(r))
-#define PUT_MI_RPN(r)   __asm__ volatile ("mtspr 0x316,%0\n" ::"r"(r))
-#define GET_MI_RPN(r)   __asm__ volatile ("mfspr %0,0x316\n" :"=r"(r))
-#define PUT_MD_EPN(r)   __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r))
-#define GET_MD_EPN(r)   __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r))
-#define PUT_M_TWB(r)    __asm__ volatile ("mtspr 0x31c,%0\n" ::"r"(r))
-#define GET_M_TWB(r)    __asm__ volatile ("mfspr %0,0x31c\n" :"=r"(r))
-#define PUT_MD_TWC(r)   __asm__ volatile ("mtspr 0x31d,%0\n" ::"r"(r))
-#define GET_MD_TWC(r)   __asm__ volatile ("mfspr %0,0x31d\n" :"=r"(r))
-#define PUT_MD_RPN(r)   __asm__ volatile ("mtspr 0x31e,%0\n" ::"r"(r))
-#define GET_MD_RPN(r)   __asm__ volatile ("mfspr %0,0x31e\n" :"=r"(r))
-#define PUT_MI_AP(r)    __asm__ volatile ("mtspr 0x312,%0\n" ::"r"(r))
-#define GET_MI_AP(r)    __asm__ volatile ("mfspr %0,0x312\n" :"=r"(r))
-#define PUT_MD_AP(r)    __asm__ volatile ("mtspr 0x31a,%0\n" ::"r"(r))
-#define GET_MD_AP(r)    __asm__ volatile ("mfspr %0,0x31a\n" :"=r"(r))
-#define PUT_M_TW(r)     __asm__ volatile ("mtspr 0x31f,%0\n" ::"r"(r))
-#define GET_M_TW(r)     __asm__ volatile ("mfspr %0,0x31f\n" :"=r"(r))
-#define PUT_MI_DCAM(r)  __asm__ volatile ("mtspr 0x330,%0\n" ::"r"(r))
-#define GET_MI_DCAM(r)  __asm__ volatile ("mfspr %0,0x330\n" :"=r"(r))
-#define PUT_MI_DRAM0(r) __asm__ volatile ("mtspr 0x331,%0\n" ::"r"(r))
-#define GET_MI_DRAM0(r) __asm__ volatile ("mfspr %0,0x331\n" :"=r"(r))
-#define PUT_MI_DRAM1(r) __asm__ volatile ("mtspr 0x332,%0\n" ::"r"(r))
-#define GET_MI_DRAM1(r) __asm__ volatile ("mfspr %0,0x332\n" :"=r"(r))
-#define PUT_MD_DCAM(r)  __asm__ volatile ("mtspr 0x338,%0\n" ::"r"(r))
-#define GET_MD_DCAM(r)  __asm__ volatile ("mfspr %0,0x338\n" :"=r"(r))
-#define PUT_MD_DRAM0(r) __asm__ volatile ("mtspr 0x339,%0\n" ::"r"(r))
-#define GET_MD_DRAM0(r) __asm__ volatile ("mfspr %0,0x339\n" :"=r"(r))
-#define PUT_MD_DRAM1(r) __asm__ volatile ("mtspr 0x33a,%0\n" ::"r"(r))
-#define GET_MD_DRAM1(r) __asm__ volatile ("mfspr %0,0x33a\n" :"=r"(r))
-#define PUT_IC_CST(r)   __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
-#define GET_IC_CST(r)   __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
-#define PUT_DC_CST(r)   __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
-#define GET_DC_CST(r)   __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
-#define PUT_IC_ADR(r)   __asm__ volatile ("mtspr 0x231,%0\n" ::"r"(r))
-#define GET_IC_ADR(r)   __asm__ volatile ("mfspr %0,0x231\n" :"=r"(r))
-#define PUT_IC_DAT(r)   __asm__ volatile ("mtspr 0x232,%0\n" ::"r"(r))
-#define GET_IC_DAT(r)   __asm__ volatile ("mfspr %0,0x232\n" :"=r"(r))
-
-extern rtems_configuration_table BSP_Configuration;
-
-void mmu_init(void)
-{
-  register unsigned long t1, t2;
-
-  /* Let's clear MSR[IR] and MSR[DR] */ 
-  t2 = PPC_MSR_IR | PPC_MSR_DR;
-  __asm__ volatile (
-    "mfmsr    %0\n"
-    "andc     %0, %0, %1\n"
-    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
-    "1"(t2));
-
-  /* Invalidate the TLBs */
-  __asm__ volatile ("tlbia\n"::);
-  __asm__ volatile ("isync\n"::);
-
-  /* make sure no TLB entries are reserved */
-  t1 = 0;
-  PUT_MI_CTR(t1);
-
-  t1 = M860_MD_CTR_TWAM;   /* 4K pages */
-  /*  PUT_MD_CTR(t1); */
-
-  t1 = M860_MI_EPN_VALID;    /* make entry valid */
-  /*  PUT_MD_EPN(t1); */
-  PUT_MI_EPN(t1);
-
-  t1 = M860_MI_TWC_PS8 | M860_MI_TWC_VALID;   /* 8 MB pages, valid */
-  /*  PUT_MD_TWC(t1); */
-  PUT_MI_TWC(t1);
-
-  t1 = M860_MD_RPN_CHANGE | M860_MD_RPN_F | M860_MD_RPN_16K | 
-       M860_MD_RPN_SHARED | M860_MD_RPN_VALID;
-  /*  PUT_MD_RPN(t1); */
-  PUT_MI_RPN(t1);
-
-  t1 = M860_MI_AP_Kp << 30;  
-  PUT_MI_AP(t1);
-  /*  PUT_MD_AP(t1); */
-  
-  t1 = M860_CACHE_CMD_UNLOCK;
-  /*  PUT_DC_CST(t1); */
-  PUT_IC_CST(t1);
-
-  t1 = M860_CACHE_CMD_INVALIDATE;
-  /*  PUT_DC_CST(t1); */
-  PUT_IC_CST(t1);
-
-  t1 = M860_CACHE_CMD_ENABLE;
-  PUT_IC_CST(t1);
-
-  t1 = M860_CACHE_CMD_SFWT;
-  /*  PUT_DC_CST(t1); */
-  t1 = M860_CACHE_CMD_ENABLE;
-  /*  PUT_DC_CST(t1);*/
-
-
-
-  /* Let's set MSR[IR]  */ 
-  t2 = PPC_MSR_IR;
-  __asm__ volatile (
-    "mfmsr    %0\n"
-    "or       %0, %0, %1\n"
-    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
-    "1"(t2));
-
-}