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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 19:57:02 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 19:57:02 +0000 |
commit | 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 (patch) | |
tree | 9253f150814c99167239f7c2cc850cdd9d92c003 /c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c | |
parent | Ensure that when -msoft-float is specified for multilib builds, that (diff) | |
download | rtems-8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52.tar.bz2 |
Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
Diffstat (limited to 'c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c')
-rw-r--r-- | c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c new file mode 100644 index 0000000000..2153ccccab --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c @@ -0,0 +1,45 @@ +/* + * mmutlbtab.c + * + * This file defines the MMU_TLB_table for the eth_comm board. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + */ + +#include <bsp.h> +#include <mpc8xx/mmu.h> + +/* + * This MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of the MPC860 processor. + * + * We initialize the entries in both the instruction and data TLBs + * with the same values - a few bits relevant to the data TLB are unused + * in the instruction TLB. + * + * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and + * Real Page Number (RPN) value are supplied in the table for each TLB entry. + * + * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must + * not have more than 32 lines in it! + * + * We set up the virtual memory map so that virtual address of a + * location is equal to its real address. + */ +MMU_TLB_table_t MMU_TLB_table[] = { + /* + * DRAM: CS1, Start address 0x00000000, 8M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * R/W,X for supervisor, no ASID comparison, not cache-inhibited. + * EPN TWC RPN + */ + { 0x00000200, 0x0D, 0x000001FD } /* DRAM - PS=PS=8M */ +}; + +/* + * MMU_N_TLB_Table_Entries is defined here because the size of the + * MMU_TLB_table is only known in this file. + */ +int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) ); |