or1k: New cache manager.

Implement new cache functions for or1k and create new bspstart function
for or1ksim to initialize instruction and data caches. Also, sim.cfg
is modified to enable/confiure cache units.

5 files changed, 85 insertions, 15 deletions

diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am
index 7af4fd0a02..bfc5dc5d63 100644
--- a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am
+++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am
@@ -30,6 +30,7 @@ include_bsp_HEADERS += ../../shared/include/irq-info.h
 include_bsp_HEADERS += ../../shared/include/stackalloc.h
 include_bsp_HEADERS += ../../shared/include/uart-output-char.h
 include_bsp_HEADERS += ../../shared/tod.h
+include_bsp_HEADERS += ../shared/include/cache_.h
 include_bsp_HEADERS += include/irq.h
 include_bsp_HEADERS += include/uart.h
 include_bsp_HEADERS += include/or1ksim.h
@@ -61,8 +62,8 @@ libbsp_a_CPPFLAGS =
 libbsp_a_LIBADD =
 
 # Startup
-libbsp_a_SOURCES += ../../shared/bspstart.c
 libbsp_a_SOURCES += ../../shared/bspreset.c
+libbsp_a_SOURCES += startup/bspstart.c
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -72,8 +73,6 @@ libbsp_a_SOURCES += ../../shared/bsplibc.c
 libbsp_a_SOURCES += ../../shared/bsppost.c
 libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
 libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
-libbsp_a_SOURCES += ../../shared/cpucounterread.c
-libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
 libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
 libbsp_a_SOURCES += ../../shared/sbrk.c
 libbsp_a_SOURCES += ../../shared/src/stackalloc.c
@@ -100,9 +99,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
 libbsp_a_SOURCES += irq/irq.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../shared/include
+libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
 
 ###############################################################################
 #                  Special Rules                                              #
diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am
index 1561b188ac..c0fa6b85b6 100644
--- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am
+++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am
@@ -86,6 +86,10 @@ $(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirsta
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
 
+$(PROJECT_INCLUDE)/bsp/cache_.h: ../shared/include/cache_.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/cache_.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/cache_.h
+
 $(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
diff --git a/c/src/lib/libbsp/or1k/or1ksim/sim.cfg b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg
index 061f61a6c5..1032f0d4ce 100644
--- a/c/src/lib/libbsp/or1k/or1ksim/sim.cfg
+++ b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg
@@ -35,23 +35,23 @@ section mc
 end
 
 section ic
-  enabled   =   0
+  enabled   =   1
   nsets     = 256
   nways     =   1
-  blocksize =  16
+  blocksize =  32
   hitdelay  =  20
-  missdelay =  20
+  missdelay =  60
 end
 
 section dc
-  enabled = 0
+  enabled = 1
   nsets = 256
   nways = 1
-  blocksize = 16
-  load_hitdelay = 0
-  load_missdelay = 0
-  store_hitdelay = 0
-  store_missdelay = 0
+  blocksize = 32
+  load_hitdelay = 40
+  load_missdelay = 120
+  store_hitdelay = 40
+  store_missdelay = 120
 end
 
 section pic
@@ -78,6 +78,7 @@ section cpu
   ver = 0x12
   cfg = 0x00
   rev = 0x0001
+  upr = 0x0000075f
   superscalar = 0
   hazards = 0
   dependstats = 0
diff --git a/c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c b/c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c
new file mode 100644
index 0000000000..518c71e850
--- /dev/null
+++ b/c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c
@@ -0,0 +1,25 @@
+/**
+ * @file
+ *
+ * @ingroup or1ksim
+ *
+ * @brief Benchmark timer support.
+ */
+
+/*
+ * Copyright (c) 2014 by Hesham ALMatary
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <libcpu/cache.h>
+
+void bsp_start( void )
+{
+  _CPU_cache_enable_instruction();
+  _CPU_cache_enable_data();
+}
diff --git a/c/src/lib/libbsp/or1k/shared/include/cache_.h b/c/src/lib/libbsp/or1k/shared/include/cache_.h
new file mode 100644
index 0000000000..ed2053858e
--- /dev/null
+++ b/c/src/lib/libbsp/or1k/shared/include/cache_.h
@@ -0,0 +1,43 @@
+/*
+ * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_OR1K_SHARED_CACHE_H
+#define LIBBSP_OR1K_SHARED_CACHE_H
+
+#include <assert.h>
+#include <bsp.h>
+#include <rtems/rtems/intr.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* These two defines also ensure that the rtems_cache_* functions have bodies */
+#define CPU_DATA_CACHE_ALIGNMENT        32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
+
+#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1
+
+static inline size_t
+_CPU_cache_get_data_cache_size( const uint32_t level )
+{
+  return (level == 0 || level == 1)? 8192 : 0;
+}
+
+static inline size_t
+_CPU_cache_get_instruction_cache_size( const uint32_t level )
+{
+  return (level == 0 || level == 1)? 8192 : 0;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_OR1K_SHARED_CACHE_H */