Remove stray white spaces.

6 files changed, 92 insertions, 92 deletions

diff --git a/c/src/lib/libbsp/mips/p4000/console/console.c b/c/src/lib/libbsp/mips/p4000/console/console.c
index 43d63b1ef2..1183b06237 100644
--- a/c/src/lib/libbsp/mips/p4000/console/console.c
+++ b/c/src/lib/libbsp/mips/p4000/console/console.c
@@ -65,16 +65,16 @@ rtems_device_driver console_initialize(
 )
 {
   rtems_status_code status;
- 
+
   status = rtems_io_register_name(
     "/dev/console",
     major,
     (rtems_device_minor_number) 0
   );
- 
+
   if (status != RTEMS_SUCCESSFUL)
     rtems_fatal_error_occurred(status);
- 
+
   return RTEMS_SUCCESSFUL;
 }
 
@@ -179,7 +179,7 @@ rtems_device_driver console_open(
 #endif
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Close entry point
  */
@@ -211,7 +211,7 @@ rtems_device_driver console_read(
   char *buffer;
   int maximum;
   int count = 0;
- 
+
   rw_args = (rtems_libio_rw_args_t *) arg;
 
   buffer = rw_args->buffer;
@@ -230,7 +230,7 @@ rtems_device_driver console_read(
 }
 
 /*
- * write bytes to the serial port. Stdout and stderr are the same. 
+ * write bytes to the serial port. Stdout and stderr are the same.
  */
 
 rtems_device_driver console_write(
diff --git a/c/src/lib/libbsp/mips/p4000/include/bsp.h b/c/src/lib/libbsp/mips/p4000/include/bsp.h
index 82aee0b5b7..4f78ec1106 100644
--- a/c/src/lib/libbsp/mips/p4000/include/bsp.h
+++ b/c/src/lib/libbsp/mips/p4000/include/bsp.h
@@ -73,8 +73,8 @@ extern uint32_t   mips_get_timer( void );
  *  Simple spin delay in microsecond units for device drivers.
  *  This is very dependent on the clock speed of the target.
  *
- *  NOTE: This macro generates a warning like "integer constant out 
- *        of range" which is safe to ignore.  In 64 bit mode, uint32_t  
+ *  NOTE: This macro generates a warning like "integer constant out
+ *        of range" which is safe to ignore.  In 64 bit mode, uint32_t
  *        types are actually 64 bits long so that comparisons between
  *        uint32_t   types and pointers are valid.  The warning is caused
  *        by code in the delay macro that is necessary for 64 bit mode.
@@ -108,7 +108,7 @@ extern rtems_configuration_table BSP_Configuration;
 /*
  * NOTE: Use the standard Console driver entry
  */
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
diff --git a/c/src/lib/libbsp/mips/p4000/start/start.S b/c/src/lib/libbsp/mips/p4000/start/start.S
index 1421c8b8d2..4bcd885e6a 100644
--- a/c/src/lib/libbsp/mips/p4000/start/start.S
+++ b/c/src/lib/libbsp/mips/p4000/start/start.S
@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
   $Id$
-*/ 
+*/
 
 /*************************************************************************
 **
@@ -44,7 +44,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 	.text
 
 
-#define TMP_STKSIZE  1024 
+#define TMP_STKSIZE  1024
 
 /**************************************************************************
 **
@@ -57,7 +57,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **		c) Clear all IntMask Enables
 **		d) Set kernel/disabled mode
 **	2)  Initialize Cause Register
-**		a)  clear software interrupt bits       
+**		a)  clear software interrupt bits
 **	3)  Determine FPU installed or not
 **		if not, clear CoProcessor 1 usable bit
 **	4)  Clear bss area
@@ -69,15 +69,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **	9)  Flush Instruction and Data caches
 ** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
 ** 	11)  Execute initialization code if the IDT/c library is to be used
-** 
+**
 ** 	12)  Jump to user's "main()" (boot_card() for RTEMS)
 ** 	13)  Jump to promexit
 **
-**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
 **	This is used to mark code specific to R3xxx or R4xxx processors.
-**	IDT/C 6.x defines __mips to be the ISA level for which we're 
-**	generating code. This is used to make sure the stack etc. is 
-**	double word aligned, when using -mips3 (default) or -mips2, 
+**	IDT/C 6.x defines __mips to be the ISA level for which we're
+**	generating code. This is used to make sure the stack etc. is
+**	double word aligned, when using -mips3 (default) or -mips2,
 **	when compiling with IDT/C6.x
 **
 ***************************************************************************/
@@ -109,10 +109,10 @@ FRAME(start,sp,0,ra)
 #endif
 
 /*
-**	check to see if an fpu is really plugged in 
+**	check to see if an fpu is really plugged in
 */
 	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
-	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	t3,fp0			/* try to write them into fp0   */
 	mtc1	zero,fp1		/* try to write zero in fp	*/
 	mfc1	t0,fp0
 	mfc1	t1,fp1
@@ -136,13 +136,13 @@ FRAME(start,sp,0,ra)
 
 	mtc0	v0, C0_SR		/* reset status register */
 2:
-	la  	gp, _gp			
+	la  	gp, _gp
 
 	la	v0,_fbss 		/* clear bss before using it */
 	la	v1,end 			/* end of bss */
 3:	sw	zero,0(v0)
 	bltu	v0,v1,3b
-	add	v0,4 
+	add	v0,4
 
 
 /************************************************************************
@@ -156,7 +156,7 @@ FRAME(start,sp,0,ra)
 *************************************************************************/
 #if __mips==3
 	/* For MIPS 3, we need to be sure that the stack is aligned on a
-	 * double word boundary. 
+	 * double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 11f   /* Last three bits Zero, already aligned */
@@ -169,11 +169,11 @@ FRAME(start,sp,0,ra)
 	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
 	sub	v1, v1, (4*4)		/* overhead */
 	move	sp, v1			/* set sp to top of stack */
-4:	sw	zero, 0(v0)  
+4:	sw	zero, 0(v0)
 	bltu	v0, v1, 4b		/* clear out temp stack */
-	add	v0, 4 
-	
-	jal	mips_install_isr_entries/* install exception handlers */ 
+	add	v0, 4
+
+	jal	mips_install_isr_entries/* install exception handlers */
 	nop				/* MUST do before memory probes */
 
 	la	v0, 5f
@@ -191,7 +191,7 @@ FRAME(start,sp,0,ra)
 	jal	config_Icache
 	nop
 	jal	config_Dcache		/* determine size of D & I caches */
-	nop	
+	nop
 #endif
 #ifdef _R4000
 	jal	config_cache		/* determine size of D & I caches */
@@ -202,7 +202,7 @@ FRAME(start,sp,0,ra)
 
 #if __mips==3
 	/* For MIPS 3, we need to be sure that the stack (and hence v0
-	 * here) is aligned on a double word boundary. 
+	 * here) is aligned on a double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 12f   /* Last three bits Zero, already aligned */
@@ -221,9 +221,9 @@ FRAME(start,sp,0,ra)
 
 /**************************************************************************
 **
-**  Permanent Stack - now know top of memory, put permanent stack there	
+**  Permanent Stack - now know top of memory, put permanent stack there
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	la	t2, _fbss		/* cache mode as linked */
 	and	t2, 0xF0000000		/* isolate segment */
@@ -237,16 +237,16 @@ FRAME(start,sp,0,ra)
 	move	v1, v0
 	subu	v1, P_STACKSIZE 	/* clear requested stack size */
 
-7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */
 	bltu	v1,v0,7b
-	add	v1, 4 
+	add	v1, 4
 	.set	reorder
 
-#ifdef _R3000 
-	jal	flush_Icache	
+#ifdef _R3000
+	jal	flush_Icache
 	jal	flush_Dcache		/* flush Data & Instruction caches */
 #endif
-#ifdef _R4000 
+#ifdef _R4000
 	jal	flush_cache_nowrite	/* flush Data & Instruction caches */
 #endif
 
@@ -256,7 +256,7 @@ FRAME(start,sp,0,ra)
 **
 **	If this chip supports a Translation Lookaside Buffer, clear it
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	.set	noreorder
 	mfc0	t1,  C0_SR		/* look at Status Register */
@@ -265,7 +265,7 @@ FRAME(start,sp,0,ra)
 #ifdef _R3000
 	li	t2, SR_TS		/* TLB Shutdown bit */
 	and 	t1,t2      		/* TLB Shutdown if 1 */
-	bnez	t1, 8f			/* skip clearing if no TLB */	
+	bnez	t1, 8f			/* skip clearing if no TLB */
 #endif
 
 #ifndef R4650
@@ -275,7 +275,7 @@ FRAME(start,sp,0,ra)
 
 /************************************************************************
 **
-**  Initialization required if using IDT/c or libc.a, standard C Lib 
+**  Initialization required if using IDT/c or libc.a, standard C Lib
 **
 **  can SKIP if not necessary for application
 **
diff --git a/c/src/lib/libbsp/mips/p4000/startup/bspstart.c b/c/src/lib/libbsp/mips/p4000/startup/bspstart.c
index 7ff8a8e381..a9fb9bce0a 100644
--- a/c/src/lib/libbsp/mips/p4000/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/p4000/startup/bspstart.c
@@ -26,7 +26,7 @@
 #include <bsp.h>
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
- 
+
 /*
  *  The original table from the application and our copy of it with
  *  some changes.
@@ -43,7 +43,7 @@ char *rtems_progname;
 /*
  *  Use the shared implementations of the following routines
  */
- 
+
 void bsp_postdriver_hook(void);
 void bsp_libc_init( void *, uint32_t, int );
 
@@ -60,7 +60,7 @@ void bsp_libc_init( void *, uint32_t, int );
  *      not yet initialized.
  *
  */
- 
+
 #define LIBC_HEAP_SIZE (64 * 1024)
 
 void bsp_pretasking_hook(void)
@@ -78,7 +78,7 @@ void bsp_pretasking_hook(void)
     rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
 #endif
 }
- 
+
 extern int end; /* defined by linker */
 
 /*
diff --git a/c/src/lib/libbsp/mips/p4000/startup/idtmem.S b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
index 3e2b373d72..eb843984ea 100644
--- a/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
+++ b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
@@ -34,8 +34,8 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **************************************************************************/
 
 /*
- * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack 
- * to set mem_size. 
+ * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
+ * to set mem_size.
  */
 
 #include <rtems/mips/iregdef.h>
@@ -44,12 +44,12 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
 	.data
 mem_size:
-	.word	0	
+	.word	0
 dcache_size:
-	.word 	0		
+	.word 	0
 icache_size:
 #if __mips == 1
-	.word	MINCACHE	
+	.word	MINCACHE
 #endif
 #if __mips == 3
 	.word	0
@@ -71,11 +71,11 @@ scache_linesize:
 		.text
 
 #if __mips == 1
-#define CONFIGFRM ((2*4)+4)	
+#define CONFIGFRM ((2*4)+4)
 
 /*************************************************************************
 **
-** Config_Dcache() -- determine size of Data cache 
+** Config_Dcache() -- determine size of Data cache
 **
 **************************************************************************/
 
@@ -100,7 +100,7 @@ FRAME(config_Dcache,sp, CONFIGFRM, ra)
 	addu	sp,CONFIGFRM		/* pop stack */
 	j	ra
 ENDFRAME(config_Dcache)
- 
+
 
 /*************************************************************************
 **
@@ -123,7 +123,7 @@ FRAME(config_Icache,sp, CONFIGFRM, ra)
 	.set	reorder
 	jal	_size_cache		/* returns instruction cache size */
 	.set	noreorder
-	mtc0	zero,C0_SR		/* swap back caches */  
+	mtc0	zero,C0_SR		/* swap back caches */
 	nop
 	and	s0,~SR_PE		/* do not inadvertantly clear PE */
 	mtc0	s0,C0_SR		/* restore SR */
@@ -198,7 +198,7 @@ ENDFRAME(_size_cache)
 **
 ****************************************************************************/
 FRAME(flush_Dcache,sp,FLUSHFRM,ra)
-	lw      t2, dcache_size		
+	lw      t2, dcache_size
 	.set	noreorder
 	mfc0	t3,C0_SR		/* save SR */
 	nop
@@ -240,7 +240,7 @@ ENDFRAME(flush_Dcache)
 **
 ****************************************************************************/
 FRAME(flush_Icache,sp,FLUSHFRM,ra)
-	lw	t1,icache_size 
+	lw	t1,icache_size
 	.set	noreorder
 	mfc0	t3,C0_SR		/* save SR */
 	nop
@@ -346,7 +346,7 @@ FRAME(clear_Icache,sp,0,ra)
 	 */
 	.set	noreorder
 	mfc0	t3,C0_SR		/* save SR */
-	nop 
+	nop
 	la	v0,1f
 	li	v1,K1BASE
 	or	v0,v1
@@ -386,7 +386,7 @@ ENDFRAME(clear_Icache)
 
 /**************************************************************************
 **
-**  get_mem_conf - get memory configuration 
+**  get_mem_conf - get memory configuration
 **
 ***************************************************************************/
 
@@ -398,7 +398,7 @@ FRAME(get_mem_conf,sp,0,ra)
 	lw	t7, icache_size
 	sw	t7, 4(a0)
 	lw	t8, dcache_size
-	sw	t8, 8(a0) 
+	sw	t8, 8(a0)
 	j	ra
 
 ENDFRAME(get_mem_conf)
@@ -429,24 +429,24 @@ label:
 
 /* This is a bit of a hack really because it relies on minaddr=a0 */
 #define _doop1(op1) \
-	cache	op1,0(a0) 
+	cache	op1,0(a0)
 
 #define _doop2(op1, op2) \
 	cache	op1,0(a0) ;		\
-	cache	op2,0(a0) 
+	cache	op2,0(a0)
 
 /* specials for cache initialisation */
 #define _doop1lw1(op1) \
 	cache	op1,0(a0) ;		\
 	lw	zero,0(a0) ;		\
-	cache	op1,0(a0) 
+	cache	op1,0(a0)
 
 #define _doop121(op1,op2) \
 	cache	op1,0(a0) ;		\
 	nop;				\
 	cache	op2,0(a0) ;		\
 	nop;				\
-	cache	op1,0(a0) 
+	cache	op1,0(a0)
 
 #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
 	.set	noreorder ;		\
@@ -481,7 +481,7 @@ label:
 
 /*
  * static void _size_cache()    R4000
- * 
+ *
  * Internal routine to determine cache sizes by looking at R4000 config
  * register.  Sizes are returned in registers, as follows:
  *	t2	icache size
@@ -508,20 +508,20 @@ LEAF(_size_cache)
 	and	t1,t0,CFG_IB
 	bnez	t1,1f
 	li	t4,16
-1:	
+1:
 
 	li	t5,32
 	and	t1,t0,CFG_DB
 	bnez	t1,1f
 	li	t5,16
-1:	
+1:
 
 	move	t6,zero			# default to no scache
 	move	t7,zero			#
 
 	and	t1,t0,CFG_C_UNCACHED	# test config register
 	bnez	t1,1f			# no scache if uncached/non-coherent
-	
+
 	li	t6,0x100000		# assume 1Mb scache <<-NOTE
 	and	t1,t0,CFG_SBMASK
 	srl	t1,CFG_SBSHIFT
@@ -533,7 +533,7 @@ END(_size_cache)
 
 /*
  * void config_cache()   R4000
- * 
+ *
  * Work out size of I, D & S caches, assuming they are already initialised.
  */
 LEAF(config_cache)
@@ -563,7 +563,7 @@ LEAF(_init_cache)
 	move	v0,ra
 	bal	_size_cache
 	move	ra,v0
-	
+
 	/*
 	 * The caches may be in an indeterminate state,
 	 * so we force good parity into them by doing an
@@ -603,7 +603,7 @@ LEAF(_init_cache)
 1:	mtc0	v0,C0_SR
 	j	ra
 END(_init_cache)
-	
+
 
 /*
  * void flush_cache (void)   R4000
@@ -620,7 +620,7 @@ LEAF(flush_cache)
 	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
 	b	2f
 
-1:	
+1:
 	lw	a2,icache_size
 	blez	a2,2f
 	lw	a3,icache_linesize
@@ -636,7 +636,7 @@ LEAF(flush_cache)
 
 2:	j	ra
 END(flush_cache)
-	
+
 /*
  * void flush_cache_nowrite (void)   R4000
  *
@@ -673,7 +673,7 @@ LEAF(flush_cache_nowrite)
 2:	mtc0	v0,C0_SR
 	j	ra
 END(flush_cache_nowrite)
-	
+
 /*
  * void clean_cache (unsigned kva, size_t n)   R4000
  *
@@ -706,7 +706,7 @@ XLEAF(clear_cache)
 
 2:	j	ra
 END(clean_cache)
-	
+
 /*
  * void clean_dcache (unsigned kva, size_t n)   R4000
  *
@@ -721,7 +721,7 @@ LEAF(clean_dcache)
 
 2:	j	ra
 END(clean_dcache)
-	
+
 /*
  * void clean_dcache_indexed (unsigned kva, size_t n)   R4000
  *
@@ -745,7 +745,7 @@ LEAF(clean_dcache_indexed)
 
 2:	j	ra
 END(clean_dcache_indexed)
-	
+
 /*
  * void clean_dcache_nowrite (unsigned kva, size_t n)   R4000
  *
@@ -760,7 +760,7 @@ LEAF(clean_dcache_nowrite)
 
 2:	j	ra
 END(clean_dcache_nowrite)
-	
+
 /*
  * void clean_dcache_nowrite_indexed (unsigned kva, size_t n)   R4000
  *
@@ -792,7 +792,7 @@ LEAF(clean_dcache_nowrite_indexed)
 2:	mtc0	v0,C0_SR
 	j	ra
 END(clean_dcache_nowrite_indexed)
-	
+
 /*
  * void clean_icache (unsigned kva, size_t n)   R4000
  *
@@ -807,7 +807,7 @@ LEAF(clean_icache)
 
 2:	j	ra
 END(clean_icache)
-	
+
 /*
  * void clean_icache_indexed (unsigned kva, size_t n)   R4000
  *
@@ -831,7 +831,7 @@ LEAF(clean_icache_indexed)
 
 2:	j	ra
 END(clean_icache_indexed)
-	
+
 
 
 /*
@@ -847,7 +847,7 @@ LEAF(clean_scache)
 
 2:	j	ra
 END(clean_scache)
-	
+
 /*
  * void clean_scache_indexed (unsigned kva, size_t n)   R4000
  *
@@ -862,7 +862,7 @@ LEAF(clean_scache_indexed)
 
 2:	j	ra
 END(clean_scache_indexed)
-	
+
 /*
  * void clean_scache_nowrite (unsigned kva, size_t n)   R4000
  *
@@ -877,7 +877,7 @@ LEAF(clean_scache_nowrite)
 
 2:	j	ra
 END(clean_scache_nowrite)
-	
+
 /*
  * void clean_scache_nowrite_indexed (unsigned kva, size_t n)   R4000
  *
@@ -900,7 +900,7 @@ LEAF(clean_scache_nowrite_indexed)
 2:	mtc0	v0,C0_SR
 	j	ra
 END(clean_scache_nowrite_indexed)
-	
+
 /**************************************************************************
 **
 **  get_mem_conf - get memory configuration  R4000
@@ -915,9 +915,9 @@ FRAME(get_mem_conf,sp,0,ra)
 	lw	t7, icache_size
 	sw	t7, 4(a0)
 	lw	t8, dcache_size
-	sw	t8, 8(a0) 
+	sw	t8, 8(a0)
 	lw	t7, scache_size
-	sw	t7, 12(a0) 
+	sw	t7, 12(a0)
 	j	ra
 
 ENDFRAME(get_mem_conf)
@@ -925,7 +925,7 @@ ENDFRAME(get_mem_conf)
 #endif /* __mips == 3 */
 
 /*
- * void set_mem_size (mem_size) 
+ * void set_mem_size (mem_size)
  *
  * config_memory()'s memory size gets written into mem_size here.
  * Now we don't need to call config_cache() with memory size - New to IDTC6.0
diff --git a/c/src/lib/libbsp/mips/p4000/startup/idttlb.S b/c/src/lib/libbsp/mips/p4000/startup/idttlb.S
index e1267dbbc8..bfe741afcc 100644
--- a/c/src/lib/libbsp/mips/p4000/startup/idttlb.S
+++ b/c/src/lib/libbsp/mips/p4000/startup/idttlb.S
@@ -186,7 +186,7 @@ ENDFRAME(ret_tlbhi)
 FRAME(ret_tlbpid,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	v0,C0_TLBHI		# fetch tlb high 
+	mfc0	v0,C0_TLBHI		# fetch tlb high
 	nop
 	and	v0,TLBHI_PIDMASK	# isolate and position
 	srl	v0,TLBHI_PIDSHIFT
@@ -219,8 +219,8 @@ FRAME(tlbprobe,sp,0,ra)
 	mfc0	t0,C0_SR		/* fetch status reg */
 	and	a0,TLBHI_VPNMASK	/* isolate just the vpn */
 	and	t0,~SR_PE		/* don't inadvertantly clear pe */
-	mtc0	zero,C0_SR 
-	mfc0	t1,C0_TLBHI	
+	mtc0	zero,C0_SR
+	mfc0	t1,C0_TLBHI
 	sll	a1,TLBHI_PIDSHIFT	/* possition the pid */
 	and	a1,TLBHI_PIDMASK
 	or	a0,a1			/* build entry hi value */
@@ -271,7 +271,7 @@ ENDFRAME(tlbprobe)
 FRAME(resettlb,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	t0,C0_TLBHI		# fetch the current hi 
+	mfc0	t0,C0_TLBHI		# fetch the current hi
 	mfc0	v0,C0_SR		# fetch the status reg.
 	li	t2,K0BASE&TLBHI_VPNMASK
 	and	v0,~SR_PE		# dont inadvertantly clear PE
@@ -329,13 +329,13 @@ FRAME(map_tlb,sp,0,ra)
 
 	mtc0	zero,C0_SR
 	mtc0	a1,C0_TLBHI		# set the hi entry
-	mtc0	a2,C0_TLBLO		# set the lo entry 
+	mtc0	a2,C0_TLBLO		# set the lo entry
 	mtc0	a0,C0_INX		# load the index
 	nop
 	tlbwi				# put the hi/lo in tlb entry indexed
 	nop
-	mtc0	a3,C0_TLBHI		# put back the tlb hi reg 
-	mtc0	v0,C0_SR		# restore the status register 
+	mtc0	a3,C0_TLBHI		# put back the tlb hi reg
+	mtc0	v0,C0_SR		# restore the status register
 	j	ra
 	nop
 	.set	reorder
@@ -357,7 +357,7 @@ FRAME(map_tlb4000,sp,0,ra)
 	mfc0	t1,C0_TLBHI		# save current TLBPID
 	mfc0	v0,C0_SR		# save SR and disable interrupts
 	mtc0	zero,C0_SR
-	mtc0	t2,C0_PAGEMASK		# set 
+	mtc0	t2,C0_PAGEMASK		# set
 	mtc0	a1,C0_TLBHI		# set VPN and TLBPID
 	mtc0	a2,C0_TLBLO0		# set PPN and access bits
 	mtc0	a3,C0_TLBLO1		# set PPN and access bits