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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 22:16:28 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 22:16:28 +0000 |
| commit | 7a677fd7d3127d3fd93e32140532d4bad637bb71 (patch) | |
| tree | 7634c790b2317c921145dbceca93824a5d875a18 /c/src/lib/libbsp/mips/jmr3904/wrapup | |
| parent | 2000-12-13 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-7a677fd7d3127d3fd93e32140532d4bad637bb71.tar.bz2 | |
2000-12-13 Joel Sherrill <joel@OARcorp.com>
* README: Updated. We are now vectoring a clock tick ISR handler.
But RTEMS is not returning from the ISR properly.
* clock/clockdrv.c: Now causes interrupts but has not been calibrated.
* include/bsp.h: Use <libcpu/tx3904.h>
* startup/Makefile.am: Add setvec.c from shared.
* startup/bspstart.c: Initialize the status register (SR) so
no interrupts are masked but global interrupts (SR_IEC) are off.
Added call to install the ISR prologue code.
* wrapup/Makefile.am: Pick up more pieces from libcpu.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am b/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am index 81b4604e8a..f5c532a23f 100644 --- a/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am +++ b/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am @@ -12,6 +12,8 @@ include $(top_srcdir)/../../../../../../automake/lib.am # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \ + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/shared/*/$(ARCH)/*.o) \ + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/tx39/*/$(ARCH)/*.o) \ $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \ $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) |