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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-04-20 13:14:55 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-04-20 13:14:55 +0000 |
| commit | b335c503112791edc634167b59ed98d377547701 (patch) | |
| tree | 144e316e346758a243a9d0e8babd35481bc76ff4 /c/src/lib/libbsp/mips/jmr3904/include/bsp.h | |
| parent | 2001-04-20 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-b335c503112791edc634167b59ed98d377547701.tar.bz2 | |
2001-04-20 Joel Sherrill <joel@OARcorp.com>
* include/bsp.h (Clear_tm27_intr): Stop the timer and disable
the interrupt. This was not quite right before and we were
getting uncontrolled interrupt nesting in tm27.
* timer/timer.c (Timer_Initialize): Added an extra reset and
changed the ITMR register so we will never get an interrupt.
(Read_timer): Fixed so the timer actually stops before it
is read. Before some times reported were outraguously high.
* start/start.S: Major clean including using stack in linkcmds,
deleting unused code, and zeroing the BSS using the linkcmds
information.
* startup/linkcmds: Put heap in lower memory than workspace
and move _clear_end so both are zeroed.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/mips/jmr3904/include/bsp.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h index 7f147040c2..3b0f52556c 100644 --- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h +++ b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h @@ -74,7 +74,11 @@ extern "C" { } while(0) #define Clear_tm27_intr() \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0x03 ); + do { \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ + } while(0) #define Lower_tm27_intr() \ mips_enable_in_interrupt_mask( 0xff01 ); |