diff options
author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-22 15:57:29 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-22 15:57:29 +0000 |
commit | 25964be6675edd80e3fb9d7ae1a0eb6664297c46 (patch) | |
tree | 94f24e923bb4b8bcee37a7fd97c501861dcb204d /c/src/lib/libbsp/mips/jmr3904/include/bsp.h | |
parent | 2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org> (diff) | |
download | rtems-25964be6675edd80e3fb9d7ae1a0eb6664297c46.tar.bz2 |
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libbsp/mips/jmr3904/include/bsp.h | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h index 2d632062d9..ce7f4a78af 100644 --- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h +++ b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h @@ -28,54 +28,6 @@ extern "C" { #include <rtems/clockdrv.h> #include <libcpu/tx3904.h> -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Following are for XXX and are board independent - * - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#if 0 -#define Install_tm27_vector( handler ) \ - (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \ - -#define Cause_tm27_intr() \ - asm volatile ( "syscall 0x01" : : ); - -#define CLOCK_VECTOR TX3904_IRQ_TMR0 - -#define Clear_tm27_intr() - -#define Lower_tm27_intr() -#else -#define Install_tm27_vector( handler ) \ - (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \ - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 20; \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \ - *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \ - } while(0) - -#define Clear_tm27_intr() \ - do { \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ - } while(0) - -#define Lower_tm27_intr() \ - mips_enable_in_interrupt_mask( 0xff01 ); - -#endif - /* Constants */ /* miscellaneous stuff assumed to exist */ |