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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-09-18 17:40:14 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-09-18 17:40:14 +0000 |
| commit | 89fc9341b77c628420135fd139fc95a500efba1d (patch) | |
| tree | 7ab8e421da0fd721af2e3a0414bb18bcff5509e8 /c/src/lib/libbsp/mips/csb350/include/tm27.h | |
| parent | 2008-09-18 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-89fc9341b77c628420135fd139fc95a500efba1d.tar.bz2 | |
2008-09-18 Joel Sherrill <joel.sherrill@oarcorp.com>
* include/bsp.h, include/tm27.h: Remove unnecessary boilerplate
comments.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/mips/csb350/include/tm27.h | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/c/src/lib/libbsp/mips/csb350/include/tm27.h b/c/src/lib/libbsp/mips/csb350/include/tm27.h index 21b9e110b9..206ba67de0 100644 --- a/c/src/lib/libbsp/mips/csb350/include/tm27.h +++ b/c/src/lib/libbsp/mips/csb350/include/tm27.h @@ -19,20 +19,33 @@ * Define the interrupt mechanism for Time Test 27 */ -#define MUST_WAIT_FOR_INTERRUPT 1 +int assert_sw_irw(uint32_t irqnum); +int negate_sw_irw(uint32_t irqnum); -#define Install_tm27_vector( handler ) +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + (void) set_vector(handler, AU1X00_IRQ_SW0, 1); #define Cause_tm27_intr() \ do { \ - ; \ + assert_sw_irq(0); \ } while(0) #define Clear_tm27_intr() \ do { \ - ; \ + negate_sw_irq(0); \ } while(0) -#define Lower_tm27_intr() +#if 0 +#define Lower_tm27_intr() \ + mips_enable_in_interrupt_mask( 0xff01 ); +#else +#define Lower_tm27_intr() \ + do { \ + continue;\ + } while(0) +#endif +#endif #endif |